mirror of https://github.com/PCSX2/pcsx2.git
microVU: Implemented 'extra' clamp mode (it was doing the same as 'normal' before)
Note: What extra clamp mode does is whenever an SSE ADD/SUB/MUL/DIV instruction is used in mVU, it will have its operands clamped. Currently seems to cause sps in some games instead of fixing it... There might be some reason for it that I'm not aware of yet, or it could be 'random' based on what a game is doing. A quick explanation of what mVU's clamp modes do: None - Does no clamping (fast) Normal - Clamp certain instructions which have proven to fix games Extra - Clamps every SSE instruction (slow) Extra + Preserve Sign - Same as extra but preserves sign of the NaN (super slow) git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2313 96395faa-99c1-11dd-bbfe-3dabce05a288
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@ -197,16 +197,7 @@ typedef u32 (__fastcall *mVUCall)(void*, void*);
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#define aWrap(x, m) ((x > m) ? 0 : x)
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#define shuffleSS(x) ((x==1)?(0x27):((x==2)?(0xc6):((x==4)?(0xe1):(0xe4))))
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#define _1mb (0x100000)
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//#undef CHECK_VU_OVERFLOW
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//#undef CHECK_VU_EXTRA_OVERFLOW
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//#undef CHECK_VU_SIGN_OVERFLOW
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//#undef CHECK_VU_UNDERFLOW
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//#define CHECK_VU_OVERFLOW 1
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//#define CHECK_VU_EXTRA_OVERFLOW 1
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//#define CHECK_VU_SIGN_OVERFLOW 1
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//#define CHECK_VU_UNDERFLOW 1
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#define clampE 0//CHECK_VU_EXTRA_OVERFLOW
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#define clampE CHECK_VU_EXTRA_OVERFLOW
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// Flag Info
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#define __Status (mVUregs.needExactMatch & 1)
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@ -455,11 +455,11 @@ void ADD_SS(microVU* mVU, int to, int from, int t1, int t2) {
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if (t2b) mVU->regAlloc->clearNeeded(t2);
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}
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#define clampOp(opX) { \
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/*mVUclamp3(mVU, to, t1, 0xf);*/ \
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/*mVUclamp3(mVU, from, t1, 0xf);*/ \
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opX(to, from); \
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/*mVUclamp4(to, t1, 0xf);*/ \
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#define clampOp(opX) { \
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mVUclamp3(mVU, to, t1, 0xf); \
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mVUclamp3(mVU, from, t1, 0xf); \
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opX(to, from); \
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mVUclamp4(to, t1, 0xf); \
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}
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void SSE_MAXPS(mV, int to, int from, int t1 = -1, int t2 = -1) {
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