mirror of https://github.com/PCSX2/pcsx2.git
IPU: Improve DMA/IPU call locations to reduce looping
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f2c032ba07
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@ -95,7 +95,7 @@ __fi void IPUProcessInterrupt()
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if (ipuRegs.ctrl.BUSY && !CommandExecuteQueued)
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IPUWorker();
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if (ipuRegs.ctrl.BUSY)
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if (ipuRegs.ctrl.BUSY && !IPU1Status.DataRequested && !(cpuRegs.interrupt & 1 << IPU_PROCESS))
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{
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CPU_INT(IPU_PROCESS, ProcessedData ? ProcessedData : 64);
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}
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@ -93,6 +93,8 @@ int IPU_Fifo_Input::write(const u32* pMem, int size)
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if (g_BP.IFC == 8)
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IPU1Status.DataRequested = false;
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CPU_INT(IPU_PROCESS, transfer_size * BIAS);
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return transfer_size;
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}
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@ -106,7 +108,7 @@ int IPU_Fifo_Input::read(void *value)
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if(ipu1ch.chcr.STR && cpuRegs.eCycle[4] == 0x9999)
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{
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CPU_INT( DMAC_TO_IPU, 4);
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CPU_INT( DMAC_TO_IPU, std::min(8U, ipu1ch.qwc));
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}
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if (g_BP.IFC == 0) return 0;
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@ -183,7 +185,7 @@ void WriteFIFO_IPUin(const mem128_t* value)
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{
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if (ipuRegs.ctrl.BUSY && !CommandExecuteQueued)
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{
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CommandExecuteQueued = true;
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CommandExecuteQueued = false;
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CPU_INT(IPU_PROCESS, 8);
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}
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}
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@ -983,7 +983,7 @@ __fi static void finishmpeg2sliceIDEC()
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__ri static bool mpeg2sliceIDEC()
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{
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u16 code;
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static bool ready_to_decode = true;
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switch (ipu_cmd.pos[0])
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{
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case 0:
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@ -1007,6 +1007,13 @@ __ri static bool mpeg2sliceIDEC()
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ipu_cmd.pos[0] = 2;
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while (1)
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{
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if (ready_to_decode == true)
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{
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ready_to_decode = false;
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CPU_INT(IPU_PROCESS, 64); // Should probably be much higher, but myst 3 doesn't like it right now.
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ipu_cmd.pos[0] = 2;
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return false;
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}
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// IPU0 isn't ready for data, so let's wait for it to be
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if ((!ipu0ch.chcr.STR || ipuRegs.ctrl.OFC || ipu0ch.qwc == 0) && ipu_cmd.pos[1] <= 2)
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{
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@ -1116,15 +1123,13 @@ __ri static bool mpeg2sliceIDEC()
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ipu_dither(rgb32, rgb16, decoder.dte);
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decoder.SetOutputTo(rgb16);
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}
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ProcessedData += decoder.ipu0_data;
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ipu_cmd.pos[1] = 2;
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return false;
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[[fallthrough]];
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case 2:
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{
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pxAssert(decoder.ipu0_data > 0);
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ready_to_decode = true;
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uint read = ipu_fifo.out.write((u32*)decoder.GetIpuDataPtr(), decoder.ipu0_data);
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decoder.AdvanceIpuDataBy(read);
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@ -1205,6 +1210,7 @@ __ri static bool mpeg2sliceIDEC()
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ipu_cmd.pos[1] = 0;
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ipu_cmd.pos[2] = 0;
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ready_to_decode = true;
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}
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finish_idec:
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@ -1269,6 +1275,7 @@ finish_idec:
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__fi static bool mpeg2_slice()
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{
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int DCT_offset, DCT_stride;
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static bool ready_to_decode = true;
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macroblock_8& mb8 = decoder.mb8;
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macroblock_16& mb16 = decoder.mb16;
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@ -1299,7 +1306,12 @@ __fi static bool mpeg2_slice()
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case 2:
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ipu_cmd.pos[0] = 2;
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if (ready_to_decode == true)
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{
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ready_to_decode = false;
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CPU_INT(IPU_PROCESS, 64); // Should probably be much higher, but myst 3 doesn't like it right now.
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return false;
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}
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// IPU0 isn't ready for data, so let's wait for it to be
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if ((!ipu0ch.chcr.STR || ipuRegs.ctrl.OFC || ipu0ch.qwc == 0) && ipu_cmd.pos[0] <= 3)
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{
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@ -1406,23 +1418,23 @@ __fi static bool mpeg2_slice()
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{
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if (decoder.macroblock_modes & MACROBLOCK_PATTERN)
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{
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switch(ipu_cmd.pos[1])
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switch (ipu_cmd.pos[1])
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{
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case 0:
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{
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// Get coded block pattern
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const CBPtab* tab;
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u16 code = UBITS(16);
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{
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// Get coded block pattern
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const CBPtab* tab;
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u16 code = UBITS(16);
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if (code >= 0x2000)
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tab = CBP_7 + (UBITS(7) - 16);
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else
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tab = CBP_9 + UBITS(9);
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if (code >= 0x2000)
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tab = CBP_7 + (UBITS(7) - 16);
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else
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tab = CBP_9 + UBITS(9);
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DUMPBITS(tab->len);
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decoder.coded_block_pattern = tab->cbp;
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}
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[[fallthrough]];
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DUMPBITS(tab->len);
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decoder.coded_block_pattern = tab->cbp;
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}
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[[fallthrough]];
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case 1:
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if (decoder.coded_block_pattern & 0x20)
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@ -1490,9 +1502,11 @@ __fi static bool mpeg2_slice()
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}
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break;
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jNO_DEFAULT;
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jNO_DEFAULT;
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}
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}
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else
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DevCon.Warning("No macroblock mode");
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}
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// Send The MacroBlock via DmaIpuFrom
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@ -1500,14 +1514,11 @@ __fi static bool mpeg2_slice()
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coded_block_pattern = decoder.coded_block_pattern;
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decoder.SetOutputTo(mb16);
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ProcessedData += decoder.ipu0_data;
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ipu_cmd.pos[0] = 3;
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return false;
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[[fallthrough]];
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case 3:
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{
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pxAssert(decoder.ipu0_data > 0);
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ready_to_decode = true;
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uint read = ipu_fifo.out.write((u32*)decoder.GetIpuDataPtr(), decoder.ipu0_data);
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decoder.AdvanceIpuDataBy(read);
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@ -1577,6 +1588,7 @@ __fi static bool mpeg2_slice()
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break;
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}
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ready_to_decode = true;
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return true;
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}
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@ -149,12 +149,6 @@ void IPU1dma()
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}
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}
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if (ipuRegs.ctrl.BUSY && !CommandExecuteQueued)
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{
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CommandExecuteQueued = true;
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CPU_INT(IPU_PROCESS, totalqwc * BIAS);
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}
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IPU_LOG("Completed Call IPU1 DMA QWC Remaining %x Finished %d In Progress %d tadr %x", ipu1ch.qwc, IPU1Status.DMAFinished, IPU1Status.InProgress, ipu1ch.tadr);
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}
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@ -198,13 +192,14 @@ void IPU0dma()
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dmacRegs.stadr.ADDR = ipu0ch.madr;
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}
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IPU_INT_FROM( readsize * BIAS );
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if (!ipu0ch.qwc)
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IPU_INT_FROM(readsize * BIAS);
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if (ipuRegs.ctrl.BUSY && !CommandExecuteQueued)
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{
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CommandExecuteQueued = true;
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CommandExecuteQueued = false;
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CPU_SET_DMASTALL(DMAC_FROM_IPU, true);
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CPU_INT(IPU_PROCESS, readsize * BIAS);
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IPUProcessInterrupt();
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}
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}
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