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Reverted shift register stuff back to how it was, my changes made no difference now and it was slightly more optimal before. 

Also fixed spaces (blame PSI :P )
This commit is contained in:
refractionpcsx2 2018-09-04 20:45:28 +01:00
parent f7fb0f686b
commit 3c5fad7ef6
4 changed files with 12 additions and 19 deletions
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2
pcsx2/MMI.cpp
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@ -1001,7 +1001,7 @@ void QFSRV() { // JayteeMaster: changed a bit to avoid screw up
GPR_reg Rd; GPR_reg Rd;
if (!_Rd_) return; if (!_Rd_) return;
u32 sa_amt = cpuRegs.sa; u32 sa_amt = cpuRegs.sa << 3;
DevCon.Warning("QFSRV %d", sa_amt); DevCon.Warning("QFSRV %d", sa_amt);
if (sa_amt == 0) { if (sa_amt == 0) {
cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.GPR.r[_Rt_].UD[0]; cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.GPR.r[_Rt_].UD[0];

8
pcsx2/R5900OpcodeImpl.cpp
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@ -1021,11 +1021,11 @@ void BREAK() {
void MFSA() { void MFSA() {
if (!_Rd_) return; if (!_Rd_) return;
cpuRegs.GPR.r[_Rd_].UD[0] = (u64)cpuRegs.sa / 8; cpuRegs.GPR.r[_Rd_].UD[0] = (u64)cpuRegs.sa;
} }
void MTSA() { void MTSA() {
cpuRegs.sa = (u32)cpuRegs.GPR.r[_Rs_].UD[0] * 8; cpuRegs.sa = (u32)cpuRegs.GPR.r[_Rs_].UD[0];
} }
// SNY supports three basic modes, two which synchronize memory accesses (related // SNY supports three basic modes, two which synchronize memory accesses (related
@ -1081,11 +1081,11 @@ void TLTIU() { if (cpuRegs.GPR.r[_Rs_].UD[0] < (u64)_Imm_) trap(); }
*********************************************************/ *********************************************************/
void MTSAB() { void MTSAB() {
cpuRegs.sa = ((cpuRegs.GPR.r[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF)) << 3; cpuRegs.sa = ((cpuRegs.GPR.r[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF));
} }
void MTSAH() { void MTSAH() {
cpuRegs.sa = ((cpuRegs.GPR.r[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 4; cpuRegs.sa = ((cpuRegs.GPR.r[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 1;
} }
} } } // end namespace R5900::Interpreter::OpcodeImpl } } } // end namespace R5900::Interpreter::OpcodeImpl

2
pcsx2/x86/iMMI.cpp
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@ -1500,7 +1500,6 @@ void recQFSRV()
int info = eeRecompileCodeXMM(XMMINFO_WRITED); int info = eeRecompileCodeXMM(XMMINFO_WRITED);
xMOV(eax, ptr32[&cpuRegs.sa]); xMOV(eax, ptr32[&cpuRegs.sa]);
xSHR(eax, 3);
xMOVDQU(xRegisterSSE(EEREC_D), ptr32[eax + &cpuRegs.GPR.r[_Rt_]]); xMOVDQU(xRegisterSSE(EEREC_D), ptr32[eax + &cpuRegs.GPR.r[_Rt_]]);
return; return;
} }
@ -1508,7 +1507,6 @@ void recQFSRV()
int info = eeRecompileCodeXMM( XMMINFO_READS | XMMINFO_READT | XMMINFO_WRITED ); int info = eeRecompileCodeXMM( XMMINFO_READS | XMMINFO_READT | XMMINFO_WRITED );
xMOV(eax, ptr32[&cpuRegs.sa]); xMOV(eax, ptr32[&cpuRegs.sa]);
xSHR(eax, 3);
xMOVDQA(ptr32[&tempqw[0]], xRegisterSSE(EEREC_T)); xMOVDQA(ptr32[&tempqw[0]], xRegisterSSE(EEREC_T));
xMOVDQA(ptr32[&tempqw[4]], xRegisterSSE(EEREC_S)); xMOVDQA(ptr32[&tempqw[4]], xRegisterSSE(EEREC_S));
xMOVDQU(xRegisterSSE(EEREC_D), ptr32[eax + &tempqw]); xMOVDQU(xRegisterSSE(EEREC_D), ptr32[eax + &tempqw]);

19
pcsx2/x86/iR5900Misc.cpp
View File

@ -96,12 +96,10 @@ void recMFSA()
mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rd_, MODE_WRITE); mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rd_, MODE_WRITE);
if( mmreg >= 0 ) { if( mmreg >= 0 ) {
xMOVL.PS(xRegisterSSE(mmreg), ptr[&cpuRegs.sa]); xMOVL.PS(xRegisterSSE(mmreg), ptr[&cpuRegs.sa]);
xPSRL.DQ(xRegisterSSE(mmreg), 3);
} }
else { else {
xMOV(eax, ptr[&cpuRegs.sa]); xMOV(eax, ptr[&cpuRegs.sa]);
xSHR(eax, 3);
_deleteEEreg(_Rd_, 0); _deleteEEreg(_Rd_, 0);
xMOV(ptr[&cpuRegs.GPR.r[_Rd_].UL[0]], eax); xMOV(ptr[&cpuRegs.GPR.r[_Rd_].UL[0]], eax);
xMOV(ptr32[&cpuRegs.GPR.r[_Rd_].UL[1]], 0); xMOV(ptr32[&cpuRegs.GPR.r[_Rd_].UL[1]], 0);
@ -112,48 +110,45 @@ void recMFSA()
void recMTSA() void recMTSA()
{ {
if( GPR_IS_CONST1(_Rs_) ) { if( GPR_IS_CONST1(_Rs_) ) {
xMOV(ptr32[&cpuRegs.sa], g_cpuConstRegs[_Rs_].UL[0] /*& 0xf*/ ); xMOV(ptr32[&cpuRegs.sa], g_cpuConstRegs[_Rs_].UL[0] & 0xf );
} }
else { else {
int mmreg; int mmreg;
if( (mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rs_, MODE_READ)) >= 0 ) { if( (mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rs_, MODE_READ)) >= 0 ) {
xPSLL.DQ(xRegisterSSE(mmreg), 3);
xMOVSS(ptr[&cpuRegs.sa], xRegisterSSE(mmreg)); xMOVSS(ptr[&cpuRegs.sa], xRegisterSSE(mmreg));
xPSRL.DQ(xRegisterSSE(mmreg), 3);
} }
else { else {
xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]); xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]);
xSHL(eax, 3);
xMOV(ptr[&cpuRegs.sa], eax); xMOV(ptr[&cpuRegs.sa], eax);
} }
xAND(ptr32[&cpuRegs.sa], 0xf);
} }
} }
void recMTSAB() void recMTSAB()
{ {
if( GPR_IS_CONST1(_Rs_) ) { if( GPR_IS_CONST1(_Rs_) ) {
xMOV(ptr32[&cpuRegs.sa], ((g_cpuConstRegs[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF)) << 3); xMOV(ptr32[&cpuRegs.sa], ((g_cpuConstRegs[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF)));
} }
else { else {
_eeMoveGPRtoR(eax, _Rs_); _eeMoveGPRtoR(eax, _Rs_);
xAND(eax, 0xF); xAND(eax, 0xF);
xXOR(eax, _Imm_&0xf); xXOR(eax, _Imm_&0xf);
xSHL(eax, 3);
xMOV(ptr[&cpuRegs.sa], eax); xMOV(ptr[&cpuRegs.sa], eax);
} }
} }
void recMTSAH() void recMTSAH()
{ {
if( GPR_IS_CONST1(_Rs_) ) { if( GPR_IS_CONST1(_Rs_) ) {
xMOV(ptr32[&cpuRegs.sa], ((g_cpuConstRegs[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 4); xMOV(ptr32[&cpuRegs.sa], ((g_cpuConstRegs[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 1);
} }
else { else {
_eeMoveGPRtoR(eax, _Rs_); _eeMoveGPRtoR(eax, _Rs_);
xAND(eax, 0x7); xAND(eax, 0x7);
xXOR(eax, _Imm_&0x7); xXOR(eax, _Imm_&0x7);
xSHL(eax, 4); xSHL(eax, 1);
xMOV(ptr[&cpuRegs.sa], eax); xMOV(ptr[&cpuRegs.sa], eax);
} }
} }