mirror of https://github.com/PCSX2/pcsx2.git
Rewrote hwRead32 in HW.cpp, which should give another little bit of speedup. Commented the daylights out of it while I was at it. :D
Fixed another small bug in the CRC display of the console. git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@647 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
Jake.Stine
Gregory Hainaut
parent
01ecf48a6c
commit
3bc7465b23
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@ -501,7 +501,7 @@ struct ElfObject
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void ElfApplyPatches()
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{
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string filename;
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ssprintf( filename, "%8.8x", params ElfCRC );
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ssprintf( filename, "%8.8x", ElfCRC );
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// if patches found the following status msg will be overwritten
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Console::SetTitle( fmt_string( "Game running [CRC=%hs]", &filename ) );
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249
pcsx2/Hw.cpp
249
pcsx2/Hw.cpp
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@ -113,8 +113,6 @@ __forceinline u16 hwRead16(u32 mem)
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if( mem >= 0x10002000 && mem < 0x10008000 )
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Console::Notice("hwRead16 to %x", params mem);
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SPR_LOG("Hardware read 16bit at %lx, ret %lx\n", mem, psHu16(mem));
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switch (mem) {
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case 0x10000000: ret = (u16)rcntRcount(0); break;
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case 0x10000010: ret = (u16)counters[0].modeval; break;
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@ -144,11 +142,8 @@ __forceinline u16 hwRead16(u32 mem)
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else ret = psHu32(mem);
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return (u16)ret;
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}
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if (mem < 0x10010000) {
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ret = psHu16(mem);
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}
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else ret = 0;
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HW_LOG("Unknown Hardware Read 16 at %x\n",mem);
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ret = psHu16(mem);
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HW_LOG("Hardware Read16 at 0x%x, value= 0x%x\n", ret, mem);
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break;
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}
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@ -157,14 +152,51 @@ __forceinline u16 hwRead16(u32 mem)
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__forceinline u32 hwRead32(u32 mem)
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{
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//IPU regs
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if ((mem>=0x10002000) && (mem<0x10003000)) {
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return ipuRead32(mem);
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// *Performance Warning* This function is called -A-LOT. Be weary when making changes. It
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// could impact FPS significantly.
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// Optimization Note:
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// Shortcut for the INTC_STAT register, which is checked *very* frequently as part of the EE's
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// vsynch timers. INTC_STAT has the disadvantage of being in the 0x1000f000 case, which has
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// a lot of additional registers in it, and combined with it's call frequency is a bad thing.
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if(mem == INTC_STAT)
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{
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// This one is checked alot, so leave it commented out unless you love 600 meg logfiles.
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//HW_LOG("DMAC_STAT Read 32bit %x\n", psHu32(0xe010));
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return psHu32(INTC_STAT);
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}
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// gauntlen uses 0x1001xxxx
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switch (mem)
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const u16 masked_mem = mem & 0xffff;
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// We optimize the hw register reads by breaking them into manageable 4k chunks (for a total of
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// 16 cases spanning the 64k PS2 hw register memory map). It helps also that the EE is, for
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// the most part, designed so that various classes of registers are sectioned off into these
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// 4k segments.
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// Notes: Breaks from the switch statement will return a standard hw memory read.
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// Special case handling of reads should use "return" directly.
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switch( masked_mem>>12 ) // switch out as according to the 4k page of the access.
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{
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// Counters Registers
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// This code uses some optimized trickery to produce more compact output.
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// See below for the "reference" block to get a better idea what this code does. :)
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case 0x0: // counters 0 and 1
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case 0x1: // counters 2 and 3
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{
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const uint cntidx = masked_mem >> 11; // neat trick to scale the counter HW address into 0-3 range.
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switch( (masked_mem>>4) & 0xf )
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{
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case 0x0: return (u16)rcntRcount(cntidx);
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case 0x1: return (u16)counters[cntidx].modeval;
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case 0x2: return (u16)counters[cntidx].target;
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case 0x3: return (u16)counters[cntidx].hold;
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}
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}
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#if 0 // Counters Reference Block (original case setup)
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case 0x10000000: return (u16)rcntRcount(0);
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case 0x10000010: return (u16)counters[0].modeval;
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case 0x10000020: return (u16)counters[0].target;
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@ -182,120 +214,109 @@ __forceinline u32 hwRead32(u32 mem)
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case 0x10001800: return (u16)rcntRcount(3);
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case 0x10001810: return (u16)counters[3].modeval;
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case 0x10001820: return (u16)counters[3].target;
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#ifdef PCSX2_DEVBUILD
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case 0x1000A000: //dma2 chcr
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HW_LOG("Hardware read DMA2_CHCR 32bit at %lx, ret %lx\n", mem, psHu32(mem));
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return psHu32(mem);
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case 0x1000A010: //dma2 madr
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HW_LOG("Hardware read DMA2_MADR 32bit at %lx, ret %lx\n", mem, psHu32(mem));
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return psHu32(mem);
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case 0x1000A020: //dma2 qwc
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HW_LOG("Hardware readDMA2_QWC 32bit at %lx, ret %lx\n", mem, psHu32(mem));
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return psHu32(mem);
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case 0x1000A030: //dma2 taddr
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HW_LOG("Hardware read DMA2_TADDR 32bit at %lx, ret %lx\n", mem, psHu32(mem));
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return psHu32(mem);
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case 0x1000A040: //dma2 asr0
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HW_LOG("Hardware read DMA2_ASR0 32bit at %lx, ret %lx\n", mem, psHu32(mem));
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return psHu32(mem);
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case 0x1000A050: //dma2 asr1
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HW_LOG("Hardware read DMA2_ASR1 32bit at %lx, ret %lx\n", mem, psHu32(mem));
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return psHu32(mem);
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case 0x1000A080: //dma2 saddr
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HW_LOG("Hardware read DMA2_SADDR 32 at %lx, ret %lx\n", mem, psHu32(mem));
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return psHu32(mem);
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case 0x1000B400: // dma4 chcr
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SPR_LOG("Hardware read IPU1_CHCR 32 at %lx, ret %x\n", mem, ((DMACh *)&PS2MEM_HW[0xb400])->chcr);
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return ((DMACh *)&PS2MEM_HW[0xb400])->chcr;
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case 0x1000e010: // DMAC_STAT
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HW_LOG("DMAC_STAT Read 32bit %x\n", psHu32(0xe010));
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return psHu32(0xe010);
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case 0x1000f000: // INTC_STAT
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//HW_LOG("INTC_STAT Read 32bit %x\n", psHu32(0xf000)); // this one tends to spam the logs..
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return psHu32(0xf000);
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case 0x1000f010: // INTC_MASK
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HW_LOG("INTC_MASK Read 32bit %x\n", psHu32(0xf010));
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return psHu32(0xf010);
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#endif
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case 0x1000f130:
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case 0x1000f260:// SIF?
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case 0x1000f410:
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case 0x1000f430://MCH_RICM
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return 0;
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break;
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case 0x1000f440://MCH_DRD
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case 0x2: return ipuRead32( mem );
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if( !((psHu32(0xf430) >> 6) & 0xF) )
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case 0xf:
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switch( (masked_mem >> 4) & 0xff )
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{
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switch ((psHu32(0xf430)>>16) & 0xFFF)
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{ //MCH_RICM: x:4|SA:12|x:5|SDEV:1|SOP:4|SBC:1|SDEV:5
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case 0x21://INIT
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if(rdram_sdevid < rdram_devices)
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{
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rdram_sdevid++;
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return 0x1F;
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}
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break;
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case 0x23://CNFGA
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return 0x0D0D; //PVER=3 | MVER=16 | DBL=1 | REFBIT=5
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case 0x24://CNFGB
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//0x0110 for PSX SVER=0 | CORG=8(5x9x7) | SPT=1 | DEVTYP=0 | BYTE=0
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return 0x0090; //SVER=0 | CORG=4(5x9x6) | SPT=1 | DEVTYP=0 | BYTE=0
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case 0x40://DEVID
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return psHu32(0xf430) & 0x1F; // =SDEV
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}
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}
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return 0;
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case 0x1000f520: // DMAC_ENABLER
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HW_LOG("DMAC_ENABLER Read 32bit %lx\n", psHu32(0xf590));
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return psHu32(0xf590);
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case 0x1000f240: // SIF?
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return psHu32(mem) | 0xF0000102;
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default:
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//if ((mem & 0xffffff0f) == 0x1000f200) {
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// SIF Control Registers
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/*1D000020 (word) - EE -> IOP status flag ( set to 0x10000 always ready )
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1D000030 (word) - IOP -> EE status flag
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1D000040 (word) - See psxMem.c ( Initially set to 0xF00042 and reset to
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to this value if 0x20 is written )
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1D000060 (word) - used to detect whether the SIF interface exists
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read must be 0x1D000060, or the top 20 bits must be zero
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*/
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// note, any changes you make in here, also make on recMemRead32
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/*if(mem ==0x1000f260) ret = 0;
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else if(mem == 0x1000F240) {
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ret = psHu32(mem) | 0xF0000102;
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//psHu32(mem) &= ~0x4000;
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}
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else ret = psHu32(mem);
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//#ifdef HW_LOG
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//__Log("%x: sif %x(%x) Read 32bit %x\n", cpuRegs.pc, mem, 0xbd000000 | (mem & 0xf0),ret);
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//#endif }
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case 0x01:
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HW_LOG("INTC_MASK Read32, value=0x%x", psHu32(INTC_MASK));
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break;
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case 0x13: // 0x1000f130
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case 0x26: // 0x1000f260 SBUS?
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case 0x41: // 0x1000f410
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case 0x43: // MCH_RICM
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return 0;
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case 0x24: // 0x1000f240: SBUS
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return psHu32(0xf240) | 0xF0000102;
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case 0x44: // 0x1000f440: MCH_DRD
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if( !((psHu32(0xf430) >> 6) & 0xF) )
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{
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switch ((psHu32(0xf430)>>16) & 0xFFF)
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{
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//MCH_RICM: x:4|SA:12|x:5|SDEV:1|SOP:4|SBC:1|SDEV:5
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case 0x21://INIT
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if(rdram_sdevid < rdram_devices)
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{
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rdram_sdevid++;
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return 0x1F;
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}
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return 0;
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case 0x23://CNFGA
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return 0x0D0D; //PVER=3 | MVER=16 | DBL=1 | REFBIT=5
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case 0x24://CNFGB
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//0x0110 for PSX SVER=0 | CORG=8(5x9x7) | SPT=1 | DEVTYP=0 | BYTE=0
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return 0x0090; //SVER=0 | CORG=4(5x9x6) | SPT=1 | DEVTYP=0 | BYTE=0
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case 0x40://DEVID
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return psHu32(0xf430) & 0x1F; // =SDEV
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}
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}
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return 0;
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}
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else */
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break;
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HW_LOG("Unknown Hardware Read 32 at %lx, ret %lx\n", mem, psHu32(mem));
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///////////////////////////////////////////////////////
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// Most of the following case handlers are for developer builds only (logging).
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// It'll all optimize to ziltch in public release builds.
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if (mem < 0x10010000)
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return psHu32(mem);
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else
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Console::Notice("*PCSX2* 32bit HW read of invalid address 0x%x", params mem);
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case 0x03:
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case 0x04:
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case 0x05:
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case 0x06:
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case 0x07:
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case 0x08:
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case 0x09:
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case 0x0a:
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{
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const char* regName = "Unknown";
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return 0;
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switch( mem )
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{
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case D2_CHCR: regName = "DMA2_CHCR"; break;
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case D2_MADR: regName = "DMA2_MADR"; break;
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case D2_QWC: regName = "DMA2_QWC"; break;
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case D2_TADR: regName = "DMA2_TADDR"; break;
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case D2_ASR0: regName = "DMA2_ASR0"; break;
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case D2_ASR1: regName = "DMA2_ASR1"; break;
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case D2_SADR: regName = "DMA2_SADDR"; break;
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}
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HW_LOG( "Hardware Read32 at 0x%x (%s), value=0x%x\n", regName, mem, psHu32(mem) );
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}
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break;
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case 0x0b:
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if( mem == D4_CHCR )
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HW_LOG("Hardware Read32 at 0x%x (IPU1:DMA4_CHCR), value=0x%x\n", mem, psHu32(mem));
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break;
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case 0x0c:
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case 0x0d:
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case 0x0e:
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if( mem == DMAC_STAT )
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HW_LOG("DMAC_STAT Read32, value=0x%x\n", psHu32(DMAC_STAT));
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break;
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jNO_DEFAULT;
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}
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// Optimization note: We masked 'mem' earlier, so it's safe to access PS2MEM_HW directly.
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// (checked disasm, and MSVC 2008 fails to optimize it on its own)
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//return psHu32(mem);
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return *((u32*)&PS2MEM_HW[masked_mem]);
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}
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__forceinline u64 hwRead64(u32 mem) {
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@ -124,6 +124,9 @@ struct DMACh {
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#define D2_MADR 0x1000A010
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#define D2_QWC 0x1000A020
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#define D2_TADR 0x1000A030
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#define D2_ASR0 0x1000A040
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#define D2_ASR1 0x1000A050
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#define D2_SADR 0x1000A080
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//fromIPU
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#define D3_CHCR 0x1000B000
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