mirror of https://github.com/PCSX2/pcsx2.git
some more FPU rec changes.
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@100 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
cottonvibes
Gregory Hainaut
parent
89ee414a38
commit
39637edee1
133
pcsx2/x86/iFPU.c
133
pcsx2/x86/iFPU.c
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@ -823,47 +823,56 @@ static void (*recComOpXMM_to_XMM[] )(x86SSERegType, x86SSERegType) = {
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static void (*recComOpM32_to_XMM[] )(x86SSERegType, uptr) = {
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SSE_ADDSS_M32_to_XMM, SSE_MULSS_M32_to_XMM, SSE_MAXSS_M32_to_XMM, SSE_MINSS_M32_to_XMM };
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int recCommutativeOp(int info, int regd, int op) {
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int recCommutativeOp(int info, int regd, int op)
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{
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int t0reg = _allocTempXMMreg(XMMT_FPS, -1);
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if (t0reg == -1) {SysPrintf("FPU: CommutativeOp Allocation Error!\n");}
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switch(info & (PROCESS_EE_S|PROCESS_EE_T) ) {
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case PROCESS_EE_S:
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if (regd == EEREC_S) recComOpM32_to_XMM[op](regd, (uptr)&fpuRegs.fpr[_Ft_]);
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if (regd == EEREC_S) {
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
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if ((CHECK_FPU_EXTRA_OVERFLOW) && (op < 2)) { fpuFloat(regd); fpuFloat(t0reg); }
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recComOpXMM_to_XMM[op](regd, t0reg);
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}
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else {
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SSE_MOVSS_XMM_to_XMM(regd, EEREC_S);
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recComOpM32_to_XMM[op](regd, (uptr)&fpuRegs.fpr[_Ft_]);
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SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.fpr[_Ft_]);
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if ((CHECK_FPU_EXTRA_OVERFLOW) && (op < 2)) { fpuFloat(regd); fpuFloat(EEREC_S); }
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recComOpXMM_to_XMM[op](regd, EEREC_S);
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}
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break;
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case PROCESS_EE_T:
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if (regd == EEREC_T) recComOpM32_to_XMM[op](regd, (uptr)&fpuRegs.fpr[_Fs_]);
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if (regd == EEREC_T) {
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Fs_]);
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if ((CHECK_FPU_EXTRA_OVERFLOW) && (op < 2)) { fpuFloat(regd); fpuFloat(t0reg); }
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recComOpXMM_to_XMM[op](regd, t0reg);
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}
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else {
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SSE_MOVSS_XMM_to_XMM(regd, EEREC_T);
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recComOpM32_to_XMM[op](regd, (uptr)&fpuRegs.fpr[_Fs_]);
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SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.fpr[_Fs_]);
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if ((CHECK_FPU_EXTRA_OVERFLOW) && (op < 2)) { fpuFloat(regd); fpuFloat(EEREC_T); }
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recComOpXMM_to_XMM[op](regd, EEREC_T);
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}
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break;
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case (PROCESS_EE_S|PROCESS_EE_T):
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// SysPrintf("Hello2 :)\n");
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if (regd == EEREC_S) recComOpXMM_to_XMM[op](regd, EEREC_T);
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else if (regd == EEREC_T) recComOpXMM_to_XMM[op](regd, EEREC_S);
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if (regd == EEREC_T) {
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if ((CHECK_FPU_EXTRA_OVERFLOW) && (op < 2)) { fpuFloat(regd); fpuFloat(EEREC_S); }
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recComOpXMM_to_XMM[op](regd, EEREC_S);
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}
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else {
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SSE_MOVSS_XMM_to_XMM(regd, EEREC_S);
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if (regd != EEREC_S) SSE_MOVSS_XMM_to_XMM(regd, EEREC_S);
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if ((CHECK_FPU_EXTRA_OVERFLOW) && (op < 2)) { fpuFloat(regd); fpuFloat(EEREC_T); }
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recComOpXMM_to_XMM[op](regd, EEREC_T);
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}
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break;
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default:
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SysPrintf("But we dont have regs2 :(\n");
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/*if (regd == EEREC_S) {
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recComOpXMM_to_XMM[op](regd, EEREC_T);
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}
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else if (regd == EEREC_T) {
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recComOpXMM_to_XMM[op](regd, EEREC_S);
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}
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else {
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SSE_MOVSS_XMM_to_XMM(regd, EEREC_S);
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recComOpXMM_to_XMM[op](regd, EEREC_T);
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}*/
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SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.fpr[_Fs_]);
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recComOpM32_to_XMM[op](regd, (uptr)&fpuRegs.fpr[_Ft_]);
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
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if ((CHECK_FPU_EXTRA_OVERFLOW) && (op < 2)) { fpuFloat(regd); fpuFloat(t0reg); }
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recComOpXMM_to_XMM[op](regd, t0reg);
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break;
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}
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_freeXMMreg(t0reg);
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return regd;
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}
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@ -947,10 +956,61 @@ void recADD_S_xmm(int info)
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FPURECOMPILE_CONSTCODE(ADD_S, XMMINFO_WRITED|XMMINFO_READS|XMMINFO_READT);
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////////////////////////////////////////////////////
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void recSUBhelper(int regd, int regt)
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{
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(regt); }
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SSE_SUBSS_XMM_to_XMM(regd, regt);
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}
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void recSUB_S_xmm(int info)
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{
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int t0reg = _allocTempXMMreg(XMMT_FPS, -1);
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if (t0reg == -1) {SysPrintf("FPU: SUB Allocation Error!\n");}
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//AND32ItoM((uptr)&fpuRegs.fprc[31], ~(FPUflagO|FPUflagU)); // Clear O and U flags
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ClampValues(recNonCommutativeOp(info, EEREC_D, 0));
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switch(info & (PROCESS_EE_S|PROCESS_EE_T) ) {
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case PROCESS_EE_S:
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//SysPrintf("FPU: SUB case 1\n");
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if (EEREC_D != EEREC_S) SSE_MOVSS_XMM_to_XMM(EEREC_D, EEREC_S);
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
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recSUBhelper(EEREC_D, t0reg);
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break;
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case PROCESS_EE_T:
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//SysPrintf("FPU: SUB case 2\n");
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if (EEREC_D == EEREC_T) {
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SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_T);
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SSE_MOVSS_M32_to_XMM(EEREC_D, (uptr)&fpuRegs.fpr[_Fs_]);
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recSUBhelper(EEREC_D, t0reg);
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}
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else {
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SSE_MOVSS_M32_to_XMM(EEREC_D, (uptr)&fpuRegs.fpr[_Fs_]);
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recSUBhelper(EEREC_D, EEREC_T);
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}
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break;
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case (PROCESS_EE_S|PROCESS_EE_T):
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//SysPrintf("FPU: SUB case 3\n");
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if (EEREC_D == EEREC_T) {
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SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_T);
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SSE_MOVSS_XMM_to_XMM(EEREC_D, EEREC_S);
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recSUBhelper(EEREC_D, t0reg);
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}
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else {
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if (EEREC_D != EEREC_S) SSE_MOVSS_XMM_to_XMM(EEREC_D, EEREC_S);
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recSUBhelper(EEREC_D, EEREC_T);
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}
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break;
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default:
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//SysPrintf("FPU: SUB case 4\n");
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
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SSE_MOVSS_M32_to_XMM(EEREC_D, (uptr)&fpuRegs.fpr[_Fs_]);
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recSUBhelper(EEREC_D, t0reg);
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break;
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}
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_freeXMMreg(t0reg);
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ClampValues(EEREC_D);
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}
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FPURECOMPILE_CONSTCODE(SUB_S, XMMINFO_WRITED|XMMINFO_READS|XMMINFO_READT);
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@ -1007,7 +1067,7 @@ void recDIVhelper1(int regd, int regt)
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x86SetJ32(ajmp32);
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/*--- Normal Divide ---*/
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(regt); }
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if (CHECK_FPU_EXTRA_OVERFLOW && (!CHECK_FPUCLAMPHACK)) { fpuFloat(regd); fpuFloat(regt); }
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SSE_DIVSS_XMM_to_XMM(regd, regt);
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ClampValues2(regd);
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@ -1020,7 +1080,7 @@ void recDIVhelper1(int regd, int regt)
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// Doesn't sets flags
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void recDIVhelper2(int regd, int regt)
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{
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(regt); }
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if (CHECK_FPU_EXTRA_OVERFLOW && (!CHECK_FPUCLAMPHACK)) { fpuFloat(regd); fpuFloat(regt); }
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SSE_DIVSS_XMM_to_XMM(regd, regt);
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ClampValues2(regd);
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}
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@ -1081,12 +1141,10 @@ FPURECOMPILE_CONSTCODE(DIV_S, XMMINFO_WRITED|XMMINFO_READS|XMMINFO_READT);
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void recSQRT_S_xmm(int info)
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{
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int tempReg;
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u8* pjmp;
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SysPrintf("FPU: SQRT\n");
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tempReg = _allocX86reg(-1, X86TYPE_TEMP, 0, 0);
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int tempReg = _allocX86reg(-1, X86TYPE_TEMP, 0, 0);
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if (tempReg == -1) {SysPrintf("FPU: SQRT Allocation Error!\n"); tempReg = EAX;}
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//SysPrintf("FPU: SQRT\n");
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if( info & PROCESS_EE_T ) {
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if ( EEREC_D != EEREC_T ) SSE_MOVSS_XMM_to_XMM(EEREC_D, EEREC_T);
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@ -1137,9 +1195,7 @@ void recMOV_S_xmm(int info)
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if( info & PROCESS_EE_S ) {
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if( EEREC_D != EEREC_S ) SSE_MOVSS_XMM_to_XMM(EEREC_D, EEREC_S);
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}
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else {
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SSE_MOVSS_M32_to_XMM(EEREC_D, (uptr)&fpuRegs.fpr[_Fs_]);
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}
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else SSE_MOVSS_M32_to_XMM(EEREC_D, (uptr)&fpuRegs.fpr[_Fs_]);
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}
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FPURECOMPILE_CONSTCODE(MOV_S, XMMINFO_WRITED|XMMINFO_READS);
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@ -1148,9 +1204,7 @@ void recNEG_S_xmm(int info) {
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if( info & PROCESS_EE_S ) {
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if( EEREC_D != EEREC_S ) SSE_MOVSS_XMM_to_XMM(EEREC_D, EEREC_S);
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}
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else {
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SSE_MOVSS_M32_to_XMM(EEREC_D, (uptr)&fpuRegs.fpr[_Fs_]);
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}
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else SSE_MOVSS_M32_to_XMM(EEREC_D, (uptr)&fpuRegs.fpr[_Fs_]);
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//AND32ItoM((uptr)&fpuRegs.fprc[31], ~(FPUflagO|FPUflagU)); // Clear O and U flags
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SSE_XORPS_M128_to_XMM(EEREC_D, (uptr)&s_neg[0]);
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@ -1162,9 +1216,8 @@ FPURECOMPILE_CONSTCODE(NEG_S, XMMINFO_WRITED|XMMINFO_READS);
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// Preforms the RSQRT function when regd <- Fs and t0reg <- Ft (Sets correct flags)
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void recRSQRThelper1(int regd, int t0reg)
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{
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u8* pjmp1;
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u8* pjmp2;
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u32* pjmp32;
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u8 *pjmp1, *pjmp2;
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u32 *pjmp32;
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int t1reg = _allocTempXMMreg(XMMT_FPS, -1);
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int tempReg = _allocX86reg(-1, X86TYPE_TEMP, 0, 0);
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if (t1reg == -1) {SysPrintf("FPU: RSQRT Allocation Error!\n");}
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@ -1224,8 +1277,8 @@ void recRSQRThelper2(int regd, int t0reg)
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void recRSQRT_S_xmm(int info)
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{
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int t0reg = _allocTempXMMreg(XMMT_FPS, -1);
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SysPrintf("FPU: RSQRT\n");
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if (t0reg == -1) {SysPrintf("FPU: RSQRT Allocation Error!\n");}
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//SysPrintf("FPU: RSQRT\n");
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switch(info & (PROCESS_EE_S|PROCESS_EE_T) ) {
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case PROCESS_EE_S:
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