mirror of https://github.com/PCSX2/pcsx2.git
IPU: Always process command if busy on DMA run
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parent
906898c785
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37f640ece2
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@ -177,8 +177,11 @@ void WriteFIFO_IPUin(const mem128_t* value)
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//committing every 16 bytes
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//committing every 16 bytes
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if( ipu_fifo.in.write((u32*)value, 1) == 0 )
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if( ipu_fifo.in.write((u32*)value, 1) == 0 )
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{
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if (ipuRegs.ctrl.BUSY && !CommandExecuteQueued)
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{
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{
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CommandExecuteQueued = true;
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CommandExecuteQueued = true;
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CPU_INT(IPU_PROCESS, 1 * BIAS);
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CPU_INT(IPU_PROCESS, 1 * BIAS);
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}
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}
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}
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}
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}
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@ -140,9 +140,11 @@ void IPU1dma()
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}
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}
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}
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}
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if (ipuRegs.ctrl.BUSY && !CommandExecuteQueued)
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{
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CommandExecuteQueued = true;
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CommandExecuteQueued = true;
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CPU_INT(IPU_PROCESS, totalqwc * BIAS);
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CPU_INT(IPU_PROCESS, totalqwc * BIAS);
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}
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IPU_LOG("Completed Call IPU1 DMA QWC Remaining %x Finished %d In Progress %d tadr %x", ipu1ch.qwc, IPU1Status.DMAFinished, IPU1Status.InProgress, ipu1ch.tadr);
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IPU_LOG("Completed Call IPU1 DMA QWC Remaining %x Finished %d In Progress %d tadr %x", ipu1ch.qwc, IPU1Status.DMAFinished, IPU1Status.InProgress, ipu1ch.tadr);
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}
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}
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@ -188,7 +190,7 @@ void IPU0dma()
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IPU_INT_FROM( readsize * BIAS );
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IPU_INT_FROM( readsize * BIAS );
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if (ipu0ch.qwc > 0 && !CommandExecuteQueued)
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if (ipuRegs.ctrl.BUSY && !CommandExecuteQueued)
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{
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{
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CommandExecuteQueued = true;
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CommandExecuteQueued = true;
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CPU_INT(IPU_PROCESS, 4);
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CPU_INT(IPU_PROCESS, 4);
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