mirror of https://github.com/PCSX2/pcsx2.git
x86emitter: Add some AVX/AVX2 instructions and YMM registers
This commit is contained in:
Connor McLaughlin
refractionpcsx2
parent
ac10e00d7c
commit
375c0a02bb
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@ -32,6 +32,7 @@ target_sources(common PRIVATE
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Timer.cpp
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Timer.cpp
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ThreadPool.cpp
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ThreadPool.cpp
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WindowInfo.cpp
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WindowInfo.cpp
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emitter/avx.cpp
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emitter/bmi.cpp
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emitter/bmi.cpp
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emitter/cpudetect.cpp
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emitter/cpudetect.cpp
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emitter/fpu.cpp
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emitter/fpu.cpp
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@ -105,6 +105,7 @@
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<ClCompile Include="Windows\WinThreads.cpp" />
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<ClCompile Include="Windows\WinThreads.cpp" />
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<ClCompile Include="Misc.cpp" />
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<ClCompile Include="Misc.cpp" />
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<ClCompile Include="Semaphore.cpp" />
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<ClCompile Include="Semaphore.cpp" />
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<ClCompile Include="emitter\avx.cpp" />
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<ClCompile Include="emitter\bmi.cpp" />
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<ClCompile Include="emitter\bmi.cpp" />
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<ClCompile Include="emitter\cpudetect.cpp" />
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<ClCompile Include="emitter\cpudetect.cpp" />
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<ClCompile Include="emitter\fpu.cpp" />
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<ClCompile Include="emitter\fpu.cpp" />
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@ -188,6 +189,7 @@
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<ClInclude Include="Vulkan\Util.h" />
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<ClInclude Include="Vulkan\Util.h" />
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<ClInclude Include="WindowInfo.h" />
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<ClInclude Include="WindowInfo.h" />
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<ClInclude Include="Threading.h" />
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<ClInclude Include="Threading.h" />
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<ClInclude Include="emitter\implement\avx.h" />
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<ClInclude Include="emitter\implement\bmi.h" />
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<ClInclude Include="emitter\implement\bmi.h" />
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<ClInclude Include="emitter\cpudetect_internal.h" />
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<ClInclude Include="emitter\cpudetect_internal.h" />
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<ClInclude Include="emitter\instructions.h" />
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<ClInclude Include="emitter\instructions.h" />
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@ -34,6 +34,9 @@
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<ClCompile Include="emitter\LnxCpuDetect.cpp">
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<ClCompile Include="emitter\LnxCpuDetect.cpp">
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<Filter>Source Files</Filter>
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<Filter>Source Files</Filter>
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</ClCompile>
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</ClCompile>
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<ClCompile Include="emitter\avx.cpp">
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<Filter>Source Files</Filter>
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</ClCompile>
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<ClCompile Include="Linux\LnxHostSys.cpp">
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<ClCompile Include="Linux\LnxHostSys.cpp">
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<Filter>Source Files</Filter>
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<Filter>Source Files</Filter>
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</ClCompile>
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</ClCompile>
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@ -297,6 +300,9 @@
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<ClInclude Include="emitter\implement\movs.h">
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<ClInclude Include="emitter\implement\movs.h">
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<Filter>Header Files</Filter>
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<Filter>Header Files</Filter>
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</ClInclude>
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</ClInclude>
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<ClInclude Include="emitter\implement\avx.h">
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<Filter>Header Files</Filter>
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</ClInclude>
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<ClInclude Include="Threading.h">
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<ClInclude Include="Threading.h">
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<Filter>Header Files</Filter>
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<Filter>Header Files</Filter>
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</ClInclude>
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</ClInclude>
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@ -0,0 +1,174 @@
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/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2022 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "common/emitter/internal.h"
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#include "common/emitter/tools.h"
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namespace x86Emitter
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{
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const xImplAVX_Move xVMOVAPS = {0x00, 0x28, 0x29};
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const xImplAVX_Move xVMOVUPS = {0x00, 0x10, 0x11};
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const xImplAVX_ArithFloat xVADD = {
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{0x00, 0x58}, // VADDPS
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{0x66, 0x58}, // VADDPD
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{0xF3, 0x58}, // VADDSS
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{0xF2, 0x58}, // VADDSD
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};
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const xImplAVX_ArithFloat xVSUB = {
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{0x00, 0x5C}, // VSUBPS
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{0x66, 0x5C}, // VSUBPD
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{0xF3, 0x5C}, // VSUBSS
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{0xF2, 0x5C}, // VSUBSD
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};
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const xImplAVX_ArithFloat xVMUL = {
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{0x00, 0x59}, // VMULPS
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{0x66, 0x59}, // VMULPD
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{0xF3, 0x59}, // VMULSS
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{0xF2, 0x59}, // VMULSD
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};
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const xImplAVX_ArithFloat xVDIV = {
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{0x00, 0x5E}, // VDIVPS
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{0x66, 0x5E}, // VDIVPD
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{0xF3, 0x5E}, // VDIVSS
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{0xF2, 0x5E}, // VDIVSD
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};
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const xImplAVX_CmpFloat xVCMP = {
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{SSE2_Equal},
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{SSE2_Less},
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{SSE2_LessOrEqual},
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{SSE2_Unordered},
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{SSE2_NotEqual},
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{SSE2_NotLess},
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{SSE2_NotLessOrEqual},
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{SSE2_Ordered},
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};
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const xImplAVX_ThreeArgYMM xVPAND = {0x66, 0xDB};
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const xImplAVX_ThreeArgYMM xVPANDN = {0x66, 0xDF};
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const xImplAVX_ThreeArgYMM xVPOR = {0x66, 0xEB};
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const xImplAVX_ThreeArgYMM xVPXOR = {0x66, 0xEF};
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const xImplAVX_CmpInt xVPCMP = {
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{0x66, 0x74}, // VPCMPEQB
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{0x66, 0x75}, // VPCMPEQW
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{0x66, 0x76}, // VPCMPEQD
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{0x66, 0x64}, // VPCMPGTB
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{0x66, 0x65}, // VPCMPGTW
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{0x66, 0x66}, // VPCMPGTD
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};
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void xVMOVMSKPS(const xRegister32& to, const xRegisterSSE& from)
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{
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xOpWriteC5(0x00, 0x50, to, xRegister32(), from);
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}
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void xVMOVMSKPD(const xRegister32& to, const xRegisterSSE& from)
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{
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xOpWriteC5(0x66, 0x50, to, xRegister32(), from);
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}
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void xVZEROUPPER()
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{
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// rather than dealing with nonexistant operands..
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xWrite8(0xc5);
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xWrite8(0xf8);
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xWrite8(0x77);
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}
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void xImplAVX_Move::operator()(const xRegisterSSE& to, const xRegisterSSE& from) const
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{
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if (to != from)
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xOpWriteC5(Prefix, LoadOpcode, to, xRegisterSSE(), from);
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}
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void xImplAVX_Move::operator()(const xRegisterSSE& to, const xIndirectVoid& from) const
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{
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xOpWriteC5(Prefix, LoadOpcode, to, xRegisterSSE(), from);
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}
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void xImplAVX_Move::operator()(const xIndirectVoid& to, const xRegisterSSE& from) const
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{
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xOpWriteC5(Prefix, StoreOpcode, from, xRegisterSSE(), to);
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}
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void xImplAVX_ThreeArg::operator()(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const
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{
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pxAssert(!to.IsWideSIMD() && !from1.IsWideSIMD() && !from2.IsWideSIMD());
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xOpWriteC5(Prefix, Opcode, to, from1, from2);
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}
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void xImplAVX_ThreeArg::operator()(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const
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{
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pxAssert(!to.IsWideSIMD() && !from1.IsWideSIMD());
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xOpWriteC5(Prefix, Opcode, to, from1, from2);
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}
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void xImplAVX_ThreeArgYMM::operator()(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const
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{
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xOpWriteC5(Prefix, Opcode, to, from1, from2);
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}
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void xImplAVX_ThreeArgYMM::operator()(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const
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{
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xOpWriteC5(Prefix, Opcode, to, from1, from2);
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}
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void xImplAVX_CmpFloatHelper::PS(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const
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{
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xOpWriteC5(0x00, 0xC2, to, from1, from2);
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xWrite8(static_cast<u8>(CType));
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}
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void xImplAVX_CmpFloatHelper::PS(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const
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{
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xOpWriteC5(0x00, 0xC2, to, from1, from2);
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xWrite8(static_cast<u8>(CType));
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}
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void xImplAVX_CmpFloatHelper::PD(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const
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{
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xOpWriteC5(0x66, 0xC2, to, from1, from2);
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xWrite8(static_cast<u8>(CType));
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}
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void xImplAVX_CmpFloatHelper::PD(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const
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{
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xOpWriteC5(0x66, 0xC2, to, from1, from2);
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xWrite8(static_cast<u8>(CType));
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}
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void xImplAVX_CmpFloatHelper::SS(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const
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{
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xOpWriteC5(0xF3, 0xC2, to, from1, from2);
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xWrite8(static_cast<u8>(CType));
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}
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void xImplAVX_CmpFloatHelper::SS(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const
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{
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xOpWriteC5(0xF3, 0xC2, to, from1, from2);
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xWrite8(static_cast<u8>(CType));
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}
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void xImplAVX_CmpFloatHelper::SD(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const
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{
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xOpWriteC5(0xF2, 0xC2, to, from1, from2);
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xWrite8(static_cast<u8>(CType));
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}
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void xImplAVX_CmpFloatHelper::SD(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const
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{
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xOpWriteC5(0xF2, 0xC2, to, from1, from2);
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xWrite8(static_cast<u8>(CType));
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}
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} // namespace x86Emitter
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@ -0,0 +1,113 @@
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/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2022 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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namespace x86Emitter
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{
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struct xImplAVX_Move
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{
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u8 Prefix;
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u8 LoadOpcode;
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u8 StoreOpcode;
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void operator()(const xRegisterSSE& to, const xRegisterSSE& from) const;
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void operator()(const xRegisterSSE& to, const xIndirectVoid& from) const;
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void operator()(const xIndirectVoid& to, const xRegisterSSE& from) const;
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};
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struct xImplAVX_ThreeArg
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{
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u8 Prefix;
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u8 Opcode;
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void operator()(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const;
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void operator()(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const;
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};
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struct xImplAVX_ThreeArgYMM : xImplAVX_ThreeArg
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{
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void operator()(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const;
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void operator()(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const;
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};
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struct xImplAVX_ArithFloat
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{
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xImplAVX_ThreeArgYMM PS;
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xImplAVX_ThreeArgYMM PD;
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xImplAVX_ThreeArg SS;
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xImplAVX_ThreeArg SD;
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};
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struct xImplAVX_CmpFloatHelper
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{
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SSE2_ComparisonType CType;
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void PS(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const;
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void PS(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const;
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void PD(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const;
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void PD(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const;
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void SS(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const;
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void SS(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const;
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void SD(const xRegisterSSE& to, const xRegisterSSE& from1, const xRegisterSSE& from2) const;
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void SD(const xRegisterSSE& to, const xRegisterSSE& from1, const xIndirectVoid& from2) const;
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};
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struct xImplAVX_CmpFloat
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{
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xImplAVX_CmpFloatHelper EQ;
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xImplAVX_CmpFloatHelper LT;
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xImplAVX_CmpFloatHelper LE;
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xImplAVX_CmpFloatHelper UO;
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xImplAVX_CmpFloatHelper NE;
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xImplAVX_CmpFloatHelper GE;
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xImplAVX_CmpFloatHelper GT;
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xImplAVX_CmpFloatHelper OR;
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};
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struct xImplAVX_CmpInt
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{
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// Compare packed bytes for equality.
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// If a data element in dest is equal to the corresponding date element src, the
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// corresponding data element in dest is set to all 1s; otherwise, it is set to all 0s.
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const xImplAVX_ThreeArgYMM EQB;
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// Compare packed words for equality.
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// If a data element in dest is equal to the corresponding date element src, the
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// corresponding data element in dest is set to all 1s; otherwise, it is set to all 0s.
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const xImplAVX_ThreeArgYMM EQW;
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// Compare packed doublewords [32-bits] for equality.
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// If a data element in dest is equal to the corresponding date element src, the
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// corresponding data element in dest is set to all 1s; otherwise, it is set to all 0s.
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const xImplAVX_ThreeArgYMM EQD;
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// Compare packed signed bytes for greater than.
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// If a data element in dest is greater than the corresponding date element src, the
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// corresponding data element in dest is set to all 1s; otherwise, it is set to all 0s.
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|
const xImplAVX_ThreeArgYMM GTB;
|
||||||
|
|
||||||
|
// Compare packed signed words for greater than.
|
||||||
|
// If a data element in dest is greater than the corresponding date element src, the
|
||||||
|
// corresponding data element in dest is set to all 1s; otherwise, it is set to all 0s.
|
||||||
|
const xImplAVX_ThreeArgYMM GTW;
|
||||||
|
|
||||||
|
// Compare packed signed doublewords [32-bits] for greater than.
|
||||||
|
// If a data element in dest is greater than the corresponding date element src, the
|
||||||
|
// corresponding data element in dest is set to all 1s; otherwise, it is set to all 0s.
|
||||||
|
const xImplAVX_ThreeArgYMM GTD;
|
||||||
|
};
|
||||||
|
} // namespace x86Emitter
|
||||||
|
|
@ -622,4 +622,24 @@ namespace x86Emitter
|
||||||
extern const SimdImpl_Pack xPACK;
|
extern const SimdImpl_Pack xPACK;
|
||||||
extern const xImplSimd_PInsert xPINSR;
|
extern const xImplSimd_PInsert xPINSR;
|
||||||
extern const SimdImpl_PExtract xPEXTR;
|
extern const SimdImpl_PExtract xPEXTR;
|
||||||
|
|
||||||
|
// ------------------------------------------------------------------------
|
||||||
|
|
||||||
|
extern const xImplAVX_Move xVMOVAPS;
|
||||||
|
extern const xImplAVX_Move xVMOVUPS;
|
||||||
|
extern const xImplAVX_ArithFloat xVADD;
|
||||||
|
extern const xImplAVX_ArithFloat xVSUB;
|
||||||
|
extern const xImplAVX_ArithFloat xVMUL;
|
||||||
|
extern const xImplAVX_ArithFloat xVDIV;
|
||||||
|
extern const xImplAVX_CmpFloat xVCMP;
|
||||||
|
extern const xImplAVX_ThreeArgYMM xVPAND;
|
||||||
|
extern const xImplAVX_ThreeArgYMM xVPANDN;
|
||||||
|
extern const xImplAVX_ThreeArgYMM xVPOR;
|
||||||
|
extern const xImplAVX_ThreeArgYMM xVPXOR;
|
||||||
|
extern const xImplAVX_CmpInt xVPCMP;
|
||||||
|
|
||||||
|
extern void xVMOVMSKPS(const xRegister32& to, const xRegisterSSE& from);
|
||||||
|
extern void xVMOVMSKPD(const xRegister32& to, const xRegisterSSE& from);
|
||||||
|
extern void xVZEROUPPER();
|
||||||
|
|
||||||
} // namespace x86Emitter
|
} // namespace x86Emitter
|
||||||
|
|
|
||||||
|
|
@ -123,12 +123,18 @@ namespace x86Emitter
|
||||||
{
|
{
|
||||||
pxAssert(prefix == 0 || prefix == 0x66 || prefix == 0xF3 || prefix == 0xF2);
|
pxAssert(prefix == 0 || prefix == 0x66 || prefix == 0xF3 || prefix == 0xF2);
|
||||||
|
|
||||||
const xRegisterInt& reg = param1.IsReg() ? param1 : param2;
|
const xRegisterBase& reg = param1.IsReg() ? param1 : param2;
|
||||||
|
|
||||||
u8 nR = reg.IsExtended() ? 0x00 : 0x80;
|
u8 nR = reg.IsExtended() ? 0x00 : 0x80;
|
||||||
u8 L = reg.IsWideSIMD() ? 4 : 0;
|
u8 L;
|
||||||
|
|
||||||
u8 nv = (~param2.GetId() & 0xF) << 3;
|
// Needed for 256-bit movemask.
|
||||||
|
if constexpr (std::is_same_v<T3, xRegisterSSE>)
|
||||||
|
L = param3.IsWideSIMD() ? 4 : 0;
|
||||||
|
else
|
||||||
|
L = reg.IsWideSIMD() ? 4 : 0;
|
||||||
|
|
||||||
|
u8 nv = (param2.IsEmpty() ? 0xF : ((~param2.GetId() & 0xF))) << 3;
|
||||||
|
|
||||||
u8 p =
|
u8 p =
|
||||||
prefix == 0xF2 ? 3 :
|
prefix == 0xF2 ? 3 :
|
||||||
|
|
|
||||||
|
|
@ -120,6 +120,16 @@ const xRegisterSSE
|
||||||
xmm12(12), xmm13(13),
|
xmm12(12), xmm13(13),
|
||||||
xmm14(14), xmm15(15);
|
xmm14(14), xmm15(15);
|
||||||
|
|
||||||
|
const xRegisterSSE
|
||||||
|
ymm0(0, xRegisterYMMTag()), ymm1(1, xRegisterYMMTag()),
|
||||||
|
ymm2(2, xRegisterYMMTag()), ymm3(3, xRegisterYMMTag()),
|
||||||
|
ymm4(4, xRegisterYMMTag()), ymm5(5, xRegisterYMMTag()),
|
||||||
|
ymm6(6, xRegisterYMMTag()), ymm7(7, xRegisterYMMTag()),
|
||||||
|
ymm8(8, xRegisterYMMTag()), ymm9(9, xRegisterYMMTag()),
|
||||||
|
ymm10(10, xRegisterYMMTag()), ymm11(11, xRegisterYMMTag()),
|
||||||
|
ymm12(12, xRegisterYMMTag()), ymm13(13, xRegisterYMMTag()),
|
||||||
|
ymm14(14, xRegisterYMMTag()), ymm15(15, xRegisterYMMTag());
|
||||||
|
|
||||||
const xAddressReg
|
const xAddressReg
|
||||||
rax(0), rbx(3),
|
rax(0), rbx(3),
|
||||||
rcx(1), rdx(2),
|
rcx(1), rdx(2),
|
||||||
|
|
|
||||||
|
|
@ -420,6 +420,8 @@ namespace x86Emitter
|
||||||
// This register type is provided to allow legal syntax for instructions that accept
|
// This register type is provided to allow legal syntax for instructions that accept
|
||||||
// an XMM register as a parameter, but do not allow for a GPR.
|
// an XMM register as a parameter, but do not allow for a GPR.
|
||||||
|
|
||||||
|
struct xRegisterYMMTag {};
|
||||||
|
|
||||||
class xRegisterSSE : public xRegisterBase
|
class xRegisterSSE : public xRegisterBase
|
||||||
{
|
{
|
||||||
typedef xRegisterBase _parent;
|
typedef xRegisterBase _parent;
|
||||||
|
|
@ -430,11 +432,16 @@ namespace x86Emitter
|
||||||
: _parent(16, regId)
|
: _parent(16, regId)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
xRegisterSSE(int regId, xRegisterYMMTag)
|
||||||
|
: _parent(32, regId)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
bool operator==(const xRegisterSSE& src) const { return this->Id == src.Id; }
|
bool operator==(const xRegisterSSE& src) const { return this->Id == src.Id; }
|
||||||
bool operator!=(const xRegisterSSE& src) const { return this->Id != src.Id; }
|
bool operator!=(const xRegisterSSE& src) const { return this->Id != src.Id; }
|
||||||
|
|
||||||
static const inline xRegisterSSE& GetInstance(uint id);
|
static const inline xRegisterSSE& GetInstance(uint id);
|
||||||
|
static const inline xRegisterSSE& GetYMMInstance(uint id);
|
||||||
};
|
};
|
||||||
|
|
||||||
class xRegisterCL : public xRegister8
|
class xRegisterCL : public xRegister8
|
||||||
|
|
@ -570,13 +577,19 @@ namespace x86Emitter
|
||||||
extern const xRegisterEmpty xEmptyReg;
|
extern const xRegisterEmpty xEmptyReg;
|
||||||
|
|
||||||
// clang-format off
|
// clang-format off
|
||||||
|
extern const xRegisterSSE
|
||||||
extern const xRegisterSSE
|
|
||||||
xmm0, xmm1, xmm2, xmm3,
|
xmm0, xmm1, xmm2, xmm3,
|
||||||
xmm4, xmm5, xmm6, xmm7,
|
xmm4, xmm5, xmm6, xmm7,
|
||||||
xmm8, xmm9, xmm10, xmm11,
|
xmm8, xmm9, xmm10, xmm11,
|
||||||
xmm12, xmm13, xmm14, xmm15;
|
xmm12, xmm13, xmm14, xmm15;
|
||||||
|
|
||||||
|
// TODO: This needs to be _M_SSE >= 0x500'ed, but we can't do it atm because common doesn't have variants.
|
||||||
|
extern const xRegisterSSE
|
||||||
|
ymm0, ymm1, ymm2, ymm3,
|
||||||
|
ymm4, ymm5, ymm6, ymm7,
|
||||||
|
ymm8, ymm9, ymm10, ymm11,
|
||||||
|
ymm12, ymm13, ymm14, ymm15;
|
||||||
|
|
||||||
extern const xAddressReg
|
extern const xAddressReg
|
||||||
rax, rbx, rcx, rdx,
|
rax, rbx, rcx, rdx,
|
||||||
rsi, rdi, rbp, rsp,
|
rsi, rdi, rbp, rsp,
|
||||||
|
|
@ -627,6 +640,19 @@ extern const xRegister32
|
||||||
return *m_tbl_xmmRegs[id];
|
return *m_tbl_xmmRegs[id];
|
||||||
}
|
}
|
||||||
|
|
||||||
|
const xRegisterSSE& xRegisterSSE::GetYMMInstance(uint id)
|
||||||
|
{
|
||||||
|
static const xRegisterSSE* const m_tbl_ymmRegs[] =
|
||||||
|
{
|
||||||
|
&ymm0, &ymm1, &ymm2, &ymm3,
|
||||||
|
&ymm4, &ymm5, &ymm6, &ymm7,
|
||||||
|
&ymm8, &ymm9, &ymm10, &ymm11,
|
||||||
|
&ymm12, &ymm13, &ymm14, &ymm15};
|
||||||
|
|
||||||
|
pxAssert(id < iREGCNT_XMM);
|
||||||
|
return *m_tbl_ymmRegs[id];
|
||||||
|
}
|
||||||
|
|
||||||
// --------------------------------------------------------------------------------------
|
// --------------------------------------------------------------------------------------
|
||||||
// xAddressVoid
|
// xAddressVoid
|
||||||
// --------------------------------------------------------------------------------------
|
// --------------------------------------------------------------------------------------
|
||||||
|
|
@ -949,3 +975,4 @@ extern const xRegister32
|
||||||
#include "implement/jmpcall.h"
|
#include "implement/jmpcall.h"
|
||||||
|
|
||||||
#include "implement/bmi.h"
|
#include "implement/bmi.h"
|
||||||
|
#include "implement/avx.h"
|
||||||
|
|
@ -167,3 +167,94 @@ TEST(CodegenTests, SSETest)
|
||||||
CODEGEN_TEST_64(xBLEND.PD(xmm8, xmm9, 0xaa), "66 45 0f 3a 0d c1 aa");
|
CODEGEN_TEST_64(xBLEND.PD(xmm8, xmm9, 0xaa), "66 45 0f 3a 0d c1 aa");
|
||||||
CODEGEN_TEST_64(xEXTRACTPS(ptr32[base], xmm1, 2), "66 0f 3a 17 0d f6 ff ff ff 02");
|
CODEGEN_TEST_64(xEXTRACTPS(ptr32[base], xmm1, 2), "66 0f 3a 17 0d f6 ff ff ff 02");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
TEST(CodegenTests, AVXTest)
|
||||||
|
{
|
||||||
|
CODEGEN_TEST_64(xVMOVAPS(xmm0, xmm1), "c5 f8 28 c1");
|
||||||
|
CODEGEN_TEST_64(xVMOVAPS(xmm0, ptr32[rdi]), "c5 f8 28 07");
|
||||||
|
CODEGEN_TEST_64(xVMOVAPS(ptr32[rdi], xmm0), "c5 f8 29 07");
|
||||||
|
CODEGEN_TEST_64(xVMOVUPS(xmm0, ptr32[rdi]), "c5 f8 10 07");
|
||||||
|
CODEGEN_TEST_64(xVMOVUPS(ptr32[rdi], xmm0), "c5 f8 11 07");
|
||||||
|
|
||||||
|
CODEGEN_TEST_64(xVADD.PS(xmm0, xmm1, xmm2), "c5 f0 58 c2");
|
||||||
|
CODEGEN_TEST_64(xVADD.PD(xmm0, xmm1, xmm2), "c5 f1 58 c2");
|
||||||
|
CODEGEN_TEST_64(xVADD.SS(xmm0, xmm1, xmm2), "c5 f2 58 c2");
|
||||||
|
CODEGEN_TEST_64(xVADD.SD(xmm0, xmm1, xmm2), "c5 f3 58 c2");
|
||||||
|
CODEGEN_TEST_64(xVSUB.PS(xmm0, xmm1, xmm2), "c5 f0 5c c2");
|
||||||
|
CODEGEN_TEST_64(xVSUB.PD(xmm0, xmm1, xmm2), "c5 f1 5c c2");
|
||||||
|
CODEGEN_TEST_64(xVSUB.SS(xmm0, xmm1, xmm2), "c5 f2 5c c2");
|
||||||
|
CODEGEN_TEST_64(xVSUB.SD(xmm0, xmm1, xmm2), "c5 f3 5c c2");
|
||||||
|
CODEGEN_TEST_64(xVMUL.PS(xmm0, xmm1, xmm2), "c5 f0 59 c2");
|
||||||
|
CODEGEN_TEST_64(xVMUL.PD(xmm0, xmm1, xmm2), "c5 f1 59 c2");
|
||||||
|
CODEGEN_TEST_64(xVMUL.SS(xmm0, xmm1, xmm2), "c5 f2 59 c2");
|
||||||
|
CODEGEN_TEST_64(xVMUL.SD(xmm0, xmm1, xmm2), "c5 f3 59 c2");
|
||||||
|
CODEGEN_TEST_64(xVDIV.PS(xmm0, xmm1, xmm2), "c5 f0 5e c2");
|
||||||
|
CODEGEN_TEST_64(xVDIV.PD(xmm0, xmm1, xmm2), "c5 f1 5e c2");
|
||||||
|
CODEGEN_TEST_64(xVDIV.SS(xmm0, xmm1, xmm2), "c5 f2 5e c2");
|
||||||
|
CODEGEN_TEST_64(xVDIV.SD(xmm0, xmm1, xmm2), "c5 f3 5e c2");
|
||||||
|
|
||||||
|
// Don't need to test all variants, since they just change the condition immediate.
|
||||||
|
CODEGEN_TEST_64(xVCMP.EQ.PS(xmm0, xmm1, xmm2), "c5 f0 c2 c2 00");
|
||||||
|
CODEGEN_TEST_64(xVCMP.EQ.PD(xmm0, xmm1, xmm2), "c5 f1 c2 c2 00");
|
||||||
|
CODEGEN_TEST_64(xVCMP.EQ.SS(xmm0, xmm1, xmm2), "c5 f2 c2 c2 00");
|
||||||
|
CODEGEN_TEST_64(xVCMP.EQ.SD(xmm0, xmm1, xmm2), "c5 f3 c2 c2 00");
|
||||||
|
CODEGEN_TEST_64(xVCMP.LE.PS(xmm0, xmm1, xmm2), "c5 f0 c2 c2 02");
|
||||||
|
CODEGEN_TEST_64(xVCMP.LE.PD(xmm0, xmm1, xmm2), "c5 f1 c2 c2 02");
|
||||||
|
CODEGEN_TEST_64(xVCMP.LE.SS(xmm0, xmm1, xmm2), "c5 f2 c2 c2 02");
|
||||||
|
CODEGEN_TEST_64(xVCMP.LE.SD(xmm0, xmm1, xmm2), "c5 f3 c2 c2 02");
|
||||||
|
|
||||||
|
CODEGEN_TEST_64(xVPCMP.EQB(xmm0, xmm1, xmm2), "c5 f1 74 c2");
|
||||||
|
CODEGEN_TEST_64(xVPCMP.EQW(xmm0, xmm1, xmm2), "c5 f1 75 c2");
|
||||||
|
CODEGEN_TEST_64(xVPCMP.EQD(xmm0, xmm1, xmm2), "c5 f1 76 c2");
|
||||||
|
CODEGEN_TEST_64(xVPCMP.GTB(xmm0, xmm1, xmm2), "c5 f1 64 c2");
|
||||||
|
CODEGEN_TEST_64(xVPCMP.GTW(xmm0, xmm1, xmm2), "c5 f1 65 c2");
|
||||||
|
CODEGEN_TEST_64(xVPCMP.GTD(xmm0, xmm1, xmm2), "c5 f1 66 c2");
|
||||||
|
|
||||||
|
CODEGEN_TEST_64(xVPAND(xmm0, xmm1, xmm2), "c5 f1 db c2");
|
||||||
|
CODEGEN_TEST_64(xVPANDN(xmm0, xmm1, xmm2), "c5 f1 df c2");
|
||||||
|
CODEGEN_TEST_64(xVPOR(xmm0, xmm1, xmm2), "c5 f1 eb c2");
|
||||||
|
CODEGEN_TEST_64(xVPXOR(xmm0, xmm1, xmm2), "c5 f1 ef c2");
|
||||||
|
|
||||||
|
CODEGEN_TEST_64(xVMOVMSKPS(eax, xmm1), "c5 f8 50 c1");
|
||||||
|
CODEGEN_TEST_64(xVMOVMSKPD(eax, xmm1), "c5 f9 50 c1");
|
||||||
|
}
|
||||||
|
|
||||||
|
TEST(CodegenTests, AVX256Test)
|
||||||
|
{
|
||||||
|
CODEGEN_TEST_64(xVMOVAPS(ymm0, ymm1), "c5 fc 28 c1");
|
||||||
|
CODEGEN_TEST_64(xVMOVAPS(ymm0, ptr32[rdi]), "c5 fc 28 07");
|
||||||
|
CODEGEN_TEST_64(xVMOVAPS(ptr32[rdi], ymm0), "c5 fc 29 07");
|
||||||
|
CODEGEN_TEST_64(xVMOVUPS(ymm0, ptr32[rdi]), "c5 fc 10 07");
|
||||||
|
CODEGEN_TEST_64(xVMOVUPS(ptr32[rdi], ymm0), "c5 fc 11 07");
|
||||||
|
|
||||||
|
CODEGEN_TEST_64(xVZEROUPPER(), "c5 f8 77");
|
||||||
|
|
||||||
|
CODEGEN_TEST_64(xVADD.PS(ymm0, ymm1, ymm2), "c5 f4 58 c2");
|
||||||
|
CODEGEN_TEST_64(xVADD.PD(ymm0, ymm1, ymm2), "c5 f5 58 c2");
|
||||||
|
CODEGEN_TEST_64(xVSUB.PS(ymm0, ymm1, ymm2), "c5 f4 5c c2");
|
||||||
|
CODEGEN_TEST_64(xVSUB.PD(ymm0, ymm1, ymm2), "c5 f5 5c c2");
|
||||||
|
CODEGEN_TEST_64(xVMUL.PS(ymm0, ymm1, ymm2), "c5 f4 59 c2");
|
||||||
|
CODEGEN_TEST_64(xVMUL.PD(ymm0, ymm1, ymm2), "c5 f5 59 c2");
|
||||||
|
CODEGEN_TEST_64(xVDIV.PS(ymm0, ymm1, ymm2), "c5 f4 5e c2");
|
||||||
|
CODEGEN_TEST_64(xVDIV.PD(ymm0, ymm1, ymm2), "c5 f5 5e c2");
|
||||||
|
|
||||||
|
CODEGEN_TEST_64(xVCMP.EQ.PS(ymm0, ymm1, ymm2), "c5 f4 c2 c2 00");
|
||||||
|
CODEGEN_TEST_64(xVCMP.EQ.PD(ymm0, ymm1, ymm2), "c5 f5 c2 c2 00");
|
||||||
|
CODEGEN_TEST_64(xVCMP.LE.PS(ymm0, ymm1, ymm2), "c5 f4 c2 c2 02");
|
||||||
|
CODEGEN_TEST_64(xVCMP.LE.PD(ymm0, ymm1, ymm2), "c5 f5 c2 c2 02");
|
||||||
|
|
||||||
|
CODEGEN_TEST_64(xVPCMP.EQB(ymm0, ymm1, ymm2), "c5 f5 74 c2");
|
||||||
|
CODEGEN_TEST_64(xVPCMP.EQW(ymm0, ymm1, ymm2), "c5 f5 75 c2");
|
||||||
|
CODEGEN_TEST_64(xVPCMP.EQD(ymm0, ymm1, ymm2), "c5 f5 76 c2");
|
||||||
|
CODEGEN_TEST_64(xVPCMP.GTB(ymm0, ymm1, ymm2), "c5 f5 64 c2");
|
||||||
|
CODEGEN_TEST_64(xVPCMP.GTW(ymm0, ymm1, ymm2), "c5 f5 65 c2");
|
||||||
|
CODEGEN_TEST_64(xVPCMP.GTD(ymm0, ymm1, ymm2), "c5 f5 66 c2");
|
||||||
|
|
||||||
|
CODEGEN_TEST_64(xVPAND(ymm0, ymm1, ymm2), "c5 f5 db c2");
|
||||||
|
CODEGEN_TEST_64(xVPANDN(ymm0, ymm1, ymm2), "c5 f5 df c2");
|
||||||
|
CODEGEN_TEST_64(xVPOR(ymm0, ymm1, ymm2), "c5 f5 eb c2");
|
||||||
|
CODEGEN_TEST_64(xVPXOR(ymm0, ymm1, ymm2), "c5 f5 ef c2");
|
||||||
|
|
||||||
|
CODEGEN_TEST_64(xVMOVMSKPS(eax, ymm1), "c5 fc 50 c1");
|
||||||
|
CODEGEN_TEST_64(xVMOVMSKPD(eax, ymm1), "c5 fd 50 c1");
|
||||||
|
}
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue