mirror of https://github.com/PCSX2/pcsx2.git
Converted IOP to use a static/global hardware register allocation. (same as I did for the EE a few weeks ago).
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3826 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
parent
cfca4ccdd0
commit
36d1503581
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@ -27,7 +27,7 @@ void psxHwReset() {
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/* if (Config.Sio) psxHu32(0x1070) |= 0x80;
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/* if (Config.Sio) psxHu32(0x1070) |= 0x80;
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if (Config.SpuIrq) psxHu32(0x1070) |= 0x200;*/
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if (Config.SpuIrq) psxHu32(0x1070) |= 0x200;*/
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memzero_ptr<0x10000>(psxH);
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memzero_ptr<0x10000>(iopHw);
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// mdecInit(); //initialize mdec decoder
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// mdecInit(); //initialize mdec decoder
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cdrReset();
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cdrReset();
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@ -229,18 +229,19 @@ struct dma_mbct
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wxString desc() const { return wxsFormat(L"madr: 0x%x bcr: 0x%x chcr: 0x%x tadr: 0x%x", madr, bcr, chcr, tadr); }
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wxString desc() const { return wxsFormat(L"madr: 0x%x bcr: 0x%x chcr: 0x%x tadr: 0x%x", madr, bcr, chcr, tadr); }
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};
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};
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#define hw_dma0 (*(dma_mbc*) &psxH[0x1080])
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static dma_mbc& hw_dma0 = (dma_mbc&) iopHw[0x1080];
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#define hw_dma1 (*(dma_mbc*) &psxH[0x1090])
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static dma_mbc& hw_dma1 = (dma_mbc&) iopHw[0x1090];
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#define hw_dma2 (*(dma_mbct*)&psxH[0x10a0])
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static dma_mbct& hw_dma2 = (dma_mbct&)iopHw[0x10a0];
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#define hw_dma3 (*(dma_mbc*) &psxH[0x10b0])
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static dma_mbc& hw_dma3 = (dma_mbc&) iopHw[0x10b0];
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#define hw_dma4 (*(dma_mbct*)&psxH[0x10c0])
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static dma_mbct& hw_dma4 = (dma_mbct&)iopHw[0x10c0];
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#define hw_dma6 (*(dma_mbc*) &psxH[0x10e0])
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static dma_mbc& hw_dma6 = (dma_mbc&) iopHw[0x10e0];
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#define hw_dma7 (*(dma_mbc*) &psxH[0x1500])
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static dma_mbc& hw_dma7 = (dma_mbc&) iopHw[0x1500];
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#define hw_dma8 (*(dma_mbc*) &psxH[0x1510])
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static dma_mbc& hw_dma8 = (dma_mbc&) iopHw[0x1510];
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#define hw_dma9 (*(dma_mbct*)&psxH[0x1520])
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static dma_mbct& hw_dma9 = (dma_mbct&)iopHw[0x1520];
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#define hw_dma10 (*(dma_mbc*) &psxH[0x1530])
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static dma_mbc& hw_dma10 = (dma_mbc&) iopHw[0x1530];
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#define hw_dma11 (*(dma_mbc*) &psxH[0x1540])
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static dma_mbc& hw_dma11 = (dma_mbc&) iopHw[0x1540];
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#define hw_dma12 (*(dma_mbc*) &psxH[0x1550])
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static dma_mbc& hw_dma12 = (dma_mbc&) iopHw[0x1550];
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#define hw_dma(x) hw_dma##x
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#define hw_dma(x) hw_dma##x
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#define HW_DMA0_MADR (psxHu32(0x1080)) // MDEC in DMA
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#define HW_DMA0_MADR (psxHu32(0x1080)) // MDEC in DMA
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@ -17,34 +17,17 @@
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#include "PrecompiledHeader.h"
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#include "PrecompiledHeader.h"
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#include "IopCommon.h"
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#include "IopCommon.h"
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u8 *psxM = NULL;
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u8 *psxP = NULL;
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u8 *psxH = NULL; // standard hardware registers (0x000->0x3ff is the scratchpad)
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u8 *psxS = NULL; // 'undocumented' SIF communication registers
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uptr *psxMemWLUT = NULL;
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uptr *psxMemWLUT = NULL;
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const uptr *psxMemRLUT = NULL;
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const uptr *psxMemRLUT = NULL;
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static u8* m_psxAllMem = NULL;
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IopVM_MemoryAllocMess* iopMem = NULL;
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static const uint m_psxMemSize =
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Ps2MemSize::IopRam +
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__pagealigned u8 iopHw[Ps2MemSize::IopHardware];
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Ps2MemSize::IopHardware +
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0x00010000 + // psxP
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0x00000100 ; // psxS
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void psxMemAlloc()
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void psxMemAlloc()
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{
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{
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if( m_psxAllMem == NULL )
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if( iopMem == NULL )
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m_psxAllMem = vtlb_malloc( m_psxMemSize, 4096 );
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iopMem = (IopVM_MemoryAllocMess*)vtlb_malloc( sizeof(*iopMem), 4096 );
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if( m_psxAllMem == NULL)
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throw Exception::OutOfMemory( L"IOP system ram (and roms)" );
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u8* curpos = m_psxAllMem;
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psxM = curpos; curpos += Ps2MemSize::IopRam;
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psxP = curpos; curpos += 0x00010000;
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psxH = curpos; curpos += Ps2MemSize::IopHardware;
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psxS = curpos; //curpos += 0x00010000;
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psxMemWLUT = (uptr*)_aligned_malloc(0x2000 * sizeof(uptr) * 2, 16);
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psxMemWLUT = (uptr*)_aligned_malloc(0x2000 * sizeof(uptr) * 2, 16);
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psxMemRLUT = psxMemWLUT + 0x2000; //(uptr*)_aligned_malloc(0x10000 * sizeof(uptr),16);
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psxMemRLUT = psxMemWLUT + 0x2000; //(uptr*)_aligned_malloc(0x10000 * sizeof(uptr),16);
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@ -55,12 +38,12 @@ void psxMemAlloc()
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void psxMemReset()
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void psxMemReset()
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{
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{
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pxAssume( psxMemWLUT != NULL );
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pxAssume( psxMemWLUT != NULL );
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pxAssume( m_psxAllMem != NULL );
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pxAssume( iopMem != NULL );
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DbgCon.WriteLn( "IOP Resetting physical ram..." );
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DbgCon.WriteLn( "IOP Resetting physical ram..." );
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memzero_ptr<0x2000 * sizeof(uptr) * 2>( psxMemWLUT ); // clears both allocations, RLUT and WLUT
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memzero_ptr<0x2000 * sizeof(uptr) * 2>( psxMemWLUT ); // clears both allocations, RLUT and WLUT
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memzero_ptr<m_psxMemSize>( m_psxAllMem );
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memzero( *iopMem );
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// Trick! We're accessing RLUT here through WLUT, since it's the non-const pointer.
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// Trick! We're accessing RLUT here through WLUT, since it's the non-const pointer.
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// So the ones with a 0x2000 prefixed are RLUT tables.
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// So the ones with a 0x2000 prefixed are RLUT tables.
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@ -69,20 +52,20 @@ void psxMemReset()
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// at 0x0, 0x8000, and 0xa000:
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// at 0x0, 0x8000, and 0xa000:
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for (int i=0; i<0x0080; i++)
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for (int i=0; i<0x0080; i++)
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{
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{
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psxMemWLUT[i + 0x0000] = (uptr)&psxM[(i & 0x1f) << 16];
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psxMemWLUT[i + 0x0000] = (uptr)&iopMem->Main[(i & 0x1f) << 16];
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// RLUTs, accessed through WLUT.
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// RLUTs, accessed through WLUT.
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psxMemWLUT[i + 0x2000] = (uptr)&psxM[(i & 0x1f) << 16];
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psxMemWLUT[i + 0x2000] = (uptr)&iopMem->Main[(i & 0x1f) << 16];
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}
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}
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// A few single-page allocations for things we store in special locations.
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// A few single-page allocations for things we store in special locations.
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psxMemWLUT[0x2000 + 0x1f00] = (uptr)psxP;
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psxMemWLUT[0x2000 + 0x1f00] = (uptr)iopMem->P;
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psxMemWLUT[0x2000 + 0x1f80] = (uptr)psxH;
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psxMemWLUT[0x2000 + 0x1f80] = (uptr)iopHw;
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//psxMemWLUT[0x1bf80] = (uptr)psxH;
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//psxMemWLUT[0x1bf80] = (uptr)iopHw;
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psxMemWLUT[0x1f00] = (uptr)psxP;
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psxMemWLUT[0x1f00] = (uptr)iopMem->P;
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psxMemWLUT[0x1f80] = (uptr)psxH;
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psxMemWLUT[0x1f80] = (uptr)iopHw;
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//psxMemWLUT[0xbf80] = (uptr)psxH;
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//psxMemWLUT[0xbf80] = (uptr)iopHw;
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// Read-only memory areas, so don't map WLUT for these...
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// Read-only memory areas, so don't map WLUT for these...
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for (int i=0; i<0x0040; i++)
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for (int i=0; i<0x0040; i++)
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@ -96,8 +79,8 @@ void psxMemReset()
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}
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}
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// sif!! (which is read only? (air))
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// sif!! (which is read only? (air))
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psxMemWLUT[0x2000 + 0x1d00] = (uptr)psxS;
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psxMemWLUT[0x2000 + 0x1d00] = (uptr)iopMem->Sif;
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//psxMemWLUT[0x1bd00] = (uptr)psxS;
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//psxMemWLUT[0x1bd00] = (uptr)iopMem->Sif;
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// this one looks like an old hack for some special write-only memory area,
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// this one looks like an old hack for some special write-only memory area,
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// but leaving it in for reference (air)
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// but leaving it in for reference (air)
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@ -106,10 +89,8 @@ void psxMemReset()
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void psxMemShutdown()
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void psxMemShutdown()
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{
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{
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vtlb_free( m_psxAllMem, m_psxMemSize );
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vtlb_free( iopMem, sizeof(*iopMem) );
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m_psxAllMem = NULL;
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iopMem = NULL;
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psxM = psxP = psxH = psxS = NULL;
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safe_aligned_free(psxMemWLUT);
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safe_aligned_free(psxMemWLUT);
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psxMemRLUT = NULL;
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psxMemRLUT = NULL;
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@ -17,10 +17,6 @@
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#include "MemoryTypes.h"
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#include "MemoryTypes.h"
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extern u8 *psxM;
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extern u8 *psxP;
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extern u8 *psxH;
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extern u8 *psxS;
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extern uptr *psxMemWLUT;
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extern uptr *psxMemWLUT;
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extern const uptr *psxMemRLUT;
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extern const uptr *psxMemRLUT;
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@ -51,29 +47,29 @@ static __fi const T* iopVirtMemR( u32 mem )
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// Obtains a pointer to the IOP's physical mapping (bypasses the TLB)
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// Obtains a pointer to the IOP's physical mapping (bypasses the TLB)
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static __fi u8* iopPhysMem( u32 addr )
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static __fi u8* iopPhysMem( u32 addr )
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{
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{
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return &psxM[addr & 0x1fffff];
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return &iopMem->Main[addr & 0x1fffff];
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}
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}
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#define psxSs8(mem) psxS[(mem) & 0x00ff]
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#define psxSs8(mem) iopMem->Sif[(mem) & 0x00ff]
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#define psxSs16(mem) (*(s16*)&psxS[(mem) & 0x00ff])
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#define psxSs16(mem) (*(s16*)&iopMem->Sif[(mem) & 0x00ff])
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#define psxSs32(mem) (*(s32*)&psxS[(mem) & 0x00ff])
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#define psxSs32(mem) (*(s32*)&iopMem->Sif[(mem) & 0x00ff])
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#define psxSu8(mem) (*(u8*) &psxS[(mem) & 0x00ff])
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#define psxSu8(mem) (*(u8*) &iopMem->Sif[(mem) & 0x00ff])
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#define psxSu16(mem) (*(u16*)&psxS[(mem) & 0x00ff])
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#define psxSu16(mem) (*(u16*)&iopMem->Sif[(mem) & 0x00ff])
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#define psxSu32(mem) (*(u32*)&psxS[(mem) & 0x00ff])
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#define psxSu32(mem) (*(u32*)&iopMem->Sif[(mem) & 0x00ff])
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#define psxPs8(mem) psxP[(mem) & 0xffff]
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#define psxPs8(mem) iopMem->P[(mem) & 0xffff]
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#define psxPs16(mem) (*(s16*)&psxP[(mem) & 0xffff])
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#define psxPs16(mem) (*(s16*)&iopMem->P[(mem) & 0xffff])
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#define psxPs32(mem) (*(s32*)&psxP[(mem) & 0xffff])
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#define psxPs32(mem) (*(s32*)&iopMem->P[(mem) & 0xffff])
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#define psxPu8(mem) (*(u8*) &psxP[(mem) & 0xffff])
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#define psxPu8(mem) (*(u8*) &iopMem->P[(mem) & 0xffff])
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#define psxPu16(mem) (*(u16*)&psxP[(mem) & 0xffff])
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#define psxPu16(mem) (*(u16*)&iopMem->P[(mem) & 0xffff])
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#define psxPu32(mem) (*(u32*)&psxP[(mem) & 0xffff])
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#define psxPu32(mem) (*(u32*)&iopMem->P[(mem) & 0xffff])
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#define psxHs8(mem) psxH[(mem) & 0xffff]
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#define psxHs8(mem) iopHw[(mem) & 0xffff]
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#define psxHs16(mem) (*(s16*)&psxH[(mem) & 0xffff])
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#define psxHs16(mem) (*(s16*)&iopHw[(mem) & 0xffff])
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#define psxHs32(mem) (*(s32*)&psxH[(mem) & 0xffff])
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#define psxHs32(mem) (*(s32*)&iopHw[(mem) & 0xffff])
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#define psxHu8(mem) (*(u8*) &psxH[(mem) & 0xffff])
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#define psxHu8(mem) (*(u8*) &iopHw[(mem) & 0xffff])
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#define psxHu16(mem) (*(u16*)&psxH[(mem) & 0xffff])
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#define psxHu16(mem) (*(u16*)&iopHw[(mem) & 0xffff])
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#define psxHu32(mem) (*(u32*)&psxH[(mem) & 0xffff])
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#define psxHu32(mem) (*(u32*)&iopHw[(mem) & 0xffff])
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extern void psxMemAlloc();
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extern void psxMemAlloc();
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extern void psxMemReset();
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extern void psxMemReset();
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@ -150,7 +150,7 @@ void memMapPhy()
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// IOP memory
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// IOP memory
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// (used by the EE Bios Kernel during initial hardware initialization, Apps/Games
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// (used by the EE Bios Kernel during initial hardware initialization, Apps/Games
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// are "supposed" to use the thread-safe SIF instead.)
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// are "supposed" to use the thread-safe SIF instead.)
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vtlb_MapBlock(psxM,0x1c000000,0x00800000);
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vtlb_MapBlock(iopMem->Main,0x1c000000,0x00800000);
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// Generic Handlers; These fallback to mem* stuff...
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// Generic Handlers; These fallback to mem* stuff...
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vtlb_MapHandler(tlb_fallback_7,0x14000000,0x10000);
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vtlb_MapHandler(tlb_fallback_7,0x14000000,0x10000);
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@ -647,7 +647,9 @@ void memReset()
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// rest of the emu is not really set up to support a "soft" reset of that sort
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// rest of the emu is not really set up to support a "soft" reset of that sort
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// we opt for the hard/safe version.
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// we opt for the hard/safe version.
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pxAssume( eeMem != NULL );
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memzero( *eeMem );
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memzero( *eeMem );
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#ifdef ENABLECACHE
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#ifdef ENABLECACHE
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memset(pCache,0,sizeof(_cacheS)*64);
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memset(pCache,0,sizeof(_cacheS)*64);
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#endif
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#endif
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@ -98,11 +98,21 @@ struct EEVM_MemoryAllocMess
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#endif
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#endif
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// EE Hardware registers.
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struct IopVM_MemoryAllocMess
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// DevNote: These are done as a static array instead of a pointer in order to allow for simpler
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{
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// macros and reference handles to be defined (we can safely use compile-time references to
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u8 Main[Ps2MemSize::IopRam]; // Main memory (hard-wired to 2MB)
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// registers instead of having to use instance variables).
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u8 P[0x00010000]; // I really have no idea what this is... --air
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u8 Sif[0x100]; // a few special SIF/SBUS registers (likely not needed)
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};
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// DevNote: EE and IOP hardware registers are done as a static array instead of a pointer in
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// order to allow for simpler macros and reference handles to be defined (we can safely use
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// compile-time references to registers instead of having to use instance variables).
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extern __pagealigned u8 eeHw[Ps2MemSize::Hardware];
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extern __pagealigned u8 eeHw[Ps2MemSize::Hardware];
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extern __pagealigned u8 iopHw[Ps2MemSize::IopHardware];
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extern EEVM_MemoryAllocMess* eeMem;
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extern EEVM_MemoryAllocMess* eeMem;
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extern IopVM_MemoryAllocMess* iopMem;
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@ -1048,7 +1048,7 @@ bool SysCorePlugins::OpenPlugin_SPU2()
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SPU2irqCallback( spu2Irq );
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SPU2irqCallback( spu2Irq );
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#else
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#else
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SPU2irqCallback( spu2Irq, spu2DMA4Irq, spu2DMA7Irq );
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SPU2irqCallback( spu2Irq, spu2DMA4Irq, spu2DMA7Irq );
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if( SPU2setDMABaseAddr != NULL ) SPU2setDMABaseAddr((uptr)psxM);
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if( SPU2setDMABaseAddr != NULL ) SPU2setDMABaseAddr((uptr)iopMem->Main);
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#endif
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#endif
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if( SPU2setClockPtr != NULL ) SPU2setClockPtr(&psxRegs.cycle);
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if( SPU2setClockPtr != NULL ) SPU2setClockPtr(&psxRegs.cycle);
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return true;
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return true;
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@ -1072,7 +1072,7 @@ bool SysCorePlugins::OpenPlugin_USB()
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USBirqCallback( usbIrq );
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USBirqCallback( usbIrq );
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usbHandler = USBirqHandler();
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usbHandler = USBirqHandler();
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if( USBsetRAM != NULL )
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if( USBsetRAM != NULL )
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USBsetRAM(psxM);
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USBsetRAM(iopMem->Main);
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return true;
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return true;
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}
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}
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@ -156,9 +156,9 @@ void SaveStateBase::FreezeMainMemory()
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FreezeMem(eeMem->Scratch, Ps2MemSize::Scratch); // scratch pad
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FreezeMem(eeMem->Scratch, Ps2MemSize::Scratch); // scratch pad
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FreezeMem(eeHw, Ps2MemSize::Hardware); // hardware memory
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FreezeMem(eeHw, Ps2MemSize::Hardware); // hardware memory
|
||||||
|
|
||||||
FreezeMem(psxM, Ps2MemSize::IopRam); // 2 MB main memory
|
FreezeMem(iopMem->Main, Ps2MemSize::IopRam); // 2 MB main memory
|
||||||
FreezeMem(psxH, Ps2MemSize::IopHardware); // hardware memory
|
FreezeMem(iopHw, Ps2MemSize::IopHardware); // hardware memory
|
||||||
FreezeMem(psxS, 0x000100); // iop's sif memory
|
FreezeMem(iopMem->Sif, 0x000100); // iop's sif memory
|
||||||
}
|
}
|
||||||
|
|
||||||
void SaveStateBase::FreezeRegisters()
|
void SaveStateBase::FreezeRegisters()
|
||||||
|
|
|
@ -24,7 +24,7 @@ namespace IopMemory {
|
||||||
using namespace Internal;
|
using namespace Internal;
|
||||||
|
|
||||||
// Template-compatible version of the psxHu macro. Used for writing.
|
// Template-compatible version of the psxHu macro. Used for writing.
|
||||||
#define psxHu(mem) (*(u32*)&psxH[(mem) & 0xffff])
|
#define psxHu(mem) (*(u32*)&iopHw[(mem) & 0xffff])
|
||||||
|
|
||||||
|
|
||||||
//////////////////////////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
|
@ -432,7 +432,7 @@ BOOL CALLBACK FinderProc(HWND hWnd,UINT uMsg,WPARAM wParam,LPARAM lParam)
|
||||||
|
|
||||||
case WM_INITDIALOG:
|
case WM_INITDIALOG:
|
||||||
mptr[0]=eeMem->Main;
|
mptr[0]=eeMem->Main;
|
||||||
mptr[1]=psxM;
|
mptr[1]=iopMem->Main;
|
||||||
|
|
||||||
hWndFinder=hWnd;
|
hWndFinder=hWnd;
|
||||||
|
|
||||||
|
|
|
@ -688,7 +688,7 @@ static void rpsxLW()
|
||||||
|
|
||||||
// read from psM directly
|
// read from psM directly
|
||||||
AND32ItoR(ECX, 0x1fffff);
|
AND32ItoR(ECX, 0x1fffff);
|
||||||
ADD32ItoR(ECX, (uptr)psxM);
|
ADD32ItoR(ECX, (uptr)iopMem->Main);
|
||||||
|
|
||||||
MOV32RmtoR( ECX, ECX );
|
MOV32RmtoR( ECX, ECX );
|
||||||
MOV32RtoM( (uptr)&psxRegs.GPR.r[_Rt_], ECX);
|
MOV32RtoM( (uptr)&psxRegs.GPR.r[_Rt_], ECX);
|
||||||
|
|
Loading…
Reference in New Issue