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Fixed trap instructions by using the old implementation for now. 

Added INT and INTO to the emitter.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2716 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
sudonim1 2010-03-15 14:15:40 +00:00
parent 7f6f27b9d9
commit 3657bebe9e
3 changed files with 38 additions and 31 deletions
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3
common/include/x86emitter/instructions.h
View File

@ -168,6 +168,9 @@ namespace x86Emitter
// NOP 1-byte
extern void xNOP();
extern void xINT( u8 imm );
extern void xINTO();
//////////////////////////////////////////////////////////////////////////////////////////
// JMP / Jcc Instructions!

13
common/src/x86emitter/x86emitter.cpp
View File

@ -861,6 +861,19 @@ __forceinline void xCLC() { xWrite8( 0xF8 ); }
// NOP 1-byte
__forceinline void xNOP() { xWrite8(0x90); }
__forceinline void xINT( u8 imm )
{
if (imm == 3)
xWrite8(0xcc);
else
{
xWrite8(0xcd);
xWrite8(imm);
}
}
__forceinline void xINTO() { xWrite8(0xce); }
__emitinline void xBSWAP( const xRegister32& to )
{
xWrite8( 0x0F );

53
pcsx2/R5900OpcodeImpl.cpp
View File

@ -901,46 +901,37 @@ void PREF( void )
{
}
// Fixme: The game "Mademan" triggers a trap here, and crashes when we actually handle it.
static void trap(u16 code=0)
{
// unimplemented?
// throw R5900Exception::Trap(code);
cpuRegs.pc -= 4;
Console.Warning("Trap exception at 0x%08x", cpuRegs.pc);
cpuException(0x34, cpuRegs.branch);
}
/*********************************************************
* Register trap *
* Format: OP rs, rt *
*********************************************************/
#ifdef PCSX2_DEVBUILD
void TGE() { Console.Warning("TGE Trap"); if (cpuRegs.GPR.r[_Rs_].SD[0] >= cpuRegs.GPR.r[_Rt_].SD[0]) throw R5900Exception::Trap(_TrapCode_); }
void TGEU() { Console.Warning("TGEU Trap"); if (cpuRegs.GPR.r[_Rs_].UD[0] >= cpuRegs.GPR.r[_Rt_].UD[0]) throw R5900Exception::Trap(_TrapCode_); }
void TLT() { Console.Warning("TLT Trap"); if (cpuRegs.GPR.r[_Rs_].SD[0] < cpuRegs.GPR.r[_Rt_].SD[0]) throw R5900Exception::Trap(_TrapCode_); }
void TLTU() { Console.Warning("TLTU Trap"); if (cpuRegs.GPR.r[_Rs_].UD[0] < cpuRegs.GPR.r[_Rt_].UD[0]) throw R5900Exception::Trap(_TrapCode_); }
void TEQ() { Console.Warning("TEQ Trap"); if (cpuRegs.GPR.r[_Rs_].SD[0] == cpuRegs.GPR.r[_Rt_].SD[0]) throw R5900Exception::Trap(_TrapCode_); }
void TNE() { Console.Warning("TNE Trap"); if (cpuRegs.GPR.r[_Rs_].SD[0] != cpuRegs.GPR.r[_Rt_].SD[0]) throw R5900Exception::Trap(_TrapCode_); }
#else
void TGE() { }
void TGEU() { }
void TLT() { }
void TLTU() { }
void TEQ() { }
void TNE() { }
#endif
void TGE() { if (cpuRegs.GPR.r[_Rs_].SD[0] >= cpuRegs.GPR.r[_Rt_].SD[0]) trap(_TrapCode_); }
void TGEU() { if (cpuRegs.GPR.r[_Rs_].UD[0] >= cpuRegs.GPR.r[_Rt_].UD[0]) trap(_TrapCode_); }
void TLT() { if (cpuRegs.GPR.r[_Rs_].SD[0] < cpuRegs.GPR.r[_Rt_].SD[0]) trap(_TrapCode_); }
void TLTU() { if (cpuRegs.GPR.r[_Rs_].UD[0] < cpuRegs.GPR.r[_Rt_].UD[0]) trap(_TrapCode_); }
void TEQ() { if (cpuRegs.GPR.r[_Rs_].SD[0] == cpuRegs.GPR.r[_Rt_].SD[0]) trap(_TrapCode_); }
void TNE() { if (cpuRegs.GPR.r[_Rs_].SD[0] != cpuRegs.GPR.r[_Rt_].SD[0]) trap(_TrapCode_); }
/*********************************************************
* Trap with immediate operand *
* Format: OP rs, rt *
*********************************************************/
#ifdef PCSX2_DEVBUILD
void TGEI() { Console.Warning("TGEI Trap"); if (cpuRegs.GPR.r[_Rs_].SD[0] >= _Imm_) throw R5900Exception::Trap(); }
void TLTI() { Console.Warning("TLTI Trap"); if (cpuRegs.GPR.r[_Rs_].SD[0] < _Imm_) throw R5900Exception::Trap(); }
void TEQI() { Console.Warning("TEQI Trap"); if (cpuRegs.GPR.r[_Rs_].SD[0] == _Imm_) throw R5900Exception::Trap(); }
void TNEI() { Console.Warning("TNEI Trap"); if (cpuRegs.GPR.r[_Rs_].SD[0] != _Imm_) throw R5900Exception::Trap(); }
void TGEIU() { Console.Warning("TGEIU Trap"); if (cpuRegs.GPR.r[_Rs_].UD[0] >= (u64)_Imm_) throw R5900Exception::Trap(); }
void TLTIU() { Console.Warning("TLTIU Trap"); if (cpuRegs.GPR.r[_Rs_].UD[0] < (u64)_Imm_) throw R5900Exception::Trap(); }
#else
void TGEI() { }
void TLTI() { }
void TEQI() { }
void TNEI() { }
void TGEIU() { }
void TLTIU() { }
#endif
void TGEI() { if (cpuRegs.GPR.r[_Rs_].SD[0] >= _Imm_) trap(); }
void TLTI() { if (cpuRegs.GPR.r[_Rs_].SD[0] < _Imm_) trap(); }
void TEQI() { if (cpuRegs.GPR.r[_Rs_].SD[0] == _Imm_) trap(); }
void TNEI() { if (cpuRegs.GPR.r[_Rs_].SD[0] != _Imm_) trap(); }
void TGEIU() { if (cpuRegs.GPR.r[_Rs_].UD[0] >= (u64)_Imm_) trap(); }
void TLTIU() { if (cpuRegs.GPR.r[_Rs_].UD[0] < (u64)_Imm_) trap(); }
/*********************************************************
* Sa intructions *