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core: inline LogicalOp* functions

This commit is contained in:
Gregory Hainaut 2015-11-26 21:48:54 +01:00
parent 9b7b9bc407
commit 3570467838
4 changed files with 32 additions and 93 deletions
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21
pcsx2/x86/iCore.h
View File

@ -363,25 +363,4 @@ extern u16 x86FpuState;
// used when regs aren't going to be changed be callee
#define FLUSH_NOCONST (FLUSH_FREE_XMM|FLUSH_FREE_MMX|FLUSH_FREE_TEMPX86)
//////////////////////////////////////////////////////////////////////////
// Utility Functions -- that should probably be part of the Emitter.
// op = 0, and
// op = 1, or
// op = 2, xor
// op = 3, nor (the 32bit versoins only do OR)
extern void LogicalOpRtoR(x86MMXRegType to, x86MMXRegType from, int op);
extern void LogicalOpMtoR(x86MMXRegType to, u32 from, int op);
extern void LogicalOp32RtoM(uptr to, x86IntRegType from, int op);
extern void LogicalOp32MtoR(x86IntRegType to, uptr from, int op);
extern void LogicalOp32ItoR(x86IntRegType to, u32 from, int op);
extern void LogicalOp32ItoM(uptr to, u32 from, int op);
#ifdef ARITHMETICIMM_RECOMPILE
extern void LogicalOpRtoR(x86MMXRegType to, x86MMXRegType from, int op);
extern void LogicalOpMtoR(x86MMXRegType to, u32 from, int op);
#endif
#endif

20
pcsx2/x86/iR3000Atables.cpp
View File

@ -287,13 +287,29 @@ void rpsxLogicalOp(int info, int op)
if( _Rd_ == _Rs_ || _Rd_ == _Rt_ ) {
int vreg = _Rd_ == _Rs_ ? _Rt_ : _Rs_;
xMOV(ecx, ptr[&psxRegs.GPR.r[vreg]]);
LogicalOp32RtoM((uptr)&psxRegs.GPR.r[_Rd_], ECX, op);
switch(op) {
case 0: xAND(ptr[&psxRegs.GPR.r[_Rd_]], ecx); break;
case 1: xOR(ptr[&psxRegs.GPR.r[_Rd_]], ecx); break;
case 2: xXOR(ptr[&psxRegs.GPR.r[_Rd_]], ecx); break;
case 3: xOR(ptr[&psxRegs.GPR.r[_Rd_]], ecx); break;
default: pxAssert(0);
}
if( op == 3 )
xNOT(ptr32[&psxRegs.GPR.r[_Rd_]]);
}
else {
xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
LogicalOp32MtoR(ECX, (uptr)&psxRegs.GPR.r[_Rt_], op);
switch(op) {
case 0: xAND(ecx, ptr[&psxRegs.GPR.r[_Rt_]]); break;
case 1: xOR(ecx, ptr[&psxRegs.GPR.r[_Rt_]]); break;
case 2: xXOR(ecx, ptr[&psxRegs.GPR.r[_Rt_]]); break;
case 3: xOR(ecx, ptr[&psxRegs.GPR.r[_Rt_]]); break;
default: pxAssert(0);
}
if( op == 3 )
xNOT(ecx);
xMOV(ptr[&psxRegs.GPR.r[_Rd_]], ecx);

68
pcsx2/x86/ix86-32/iCore-32.cpp
View File

@ -934,71 +934,3 @@ int _allocCheckGPRtoMMX(EEINST* pinst, int reg, int mode)
{
return _checkMMXreg(MMX_GPR+reg, mode);
}
static const __aligned16 u32 s_ones[2] = {0xffffffff, 0xffffffff};
void LogicalOpRtoR(x86MMXRegType to, x86MMXRegType from, int op)
{
switch(op) {
case 0: xPAND(xRegisterMMX(to), xRegisterMMX(from)); break;
case 1: xPOR(xRegisterMMX(to), xRegisterMMX(from)); break;
case 2: xPXOR(xRegisterMMX(to), xRegisterMMX(from)); break;
case 3:
xPOR(xRegisterMMX(to), xRegisterMMX(from));
xPXOR(xRegisterMMX(to), ptr[&s_ones[0]]);
break;
}
}
void LogicalOpMtoR(x86MMXRegType to, uptr from, int op)
{
switch(op) {
case 0: xPAND(xRegisterMMX(to), ptr[(void*)(from)]); break;
case 1: xPOR(xRegisterMMX(to), ptr[(void*)(from)]); break;
case 2: xPXOR(xRegisterMMX(to), ptr[(void*)(from)]); break;
case 3:
xPOR(xRegisterMMX(to), xRegisterMMX(from));
xPXOR(xRegisterMMX(to), ptr[&s_ones[0]]);
break;
}
}
void LogicalOp32RtoM(uptr to, x86IntRegType from, int op)
{
switch(op) {
case 0: xAND(ptr[(void*)(to)], xRegister32(from)); break;
case 1: xOR(ptr[(void*)(to)], xRegister32(from)); break;
case 2: xXOR(ptr[(void*)(to)], xRegister32(from)); break;
case 3: xOR(ptr[(void*)(to)], xRegister32(from)); break;
}
}
void LogicalOp32MtoR(x86IntRegType to, uptr from, int op)
{
switch(op) {
case 0: xAND(xRegister32(to), ptr[(void*)(from)]); break;
case 1: xOR(xRegister32(to), ptr[(void*)(from)]); break;
case 2: xXOR(xRegister32(to), ptr[(void*)(from)]); break;
case 3: xOR(xRegister32(to), ptr[(void*)(from)]); break;
}
}
void LogicalOp32ItoR(x86IntRegType to, u32 from, int op)
{
switch(op) {
case 0: xAND(xRegister32(to), from); break;
case 1: xOR(xRegister32(to), from); break;
case 2: xXOR(xRegister32(to), from); break;
case 3: xOR(xRegister32(to), from); break;
}
}
void LogicalOp32ItoM(uptr to, u32 from, int op)
{
switch(op) {
case 0: xAND(ptr32[(u32*)(to)], from); break;
case 1: xOR(ptr32[(u32*)(to)], from); break;
case 2: xXOR(ptr32[(u32*)(to)], from); break;
case 3: xOR(ptr32[(u32*)(to)], from); break;
}
}

16
pcsx2/x86/ix86-32/iR5900AritImm.cpp
View File

@ -195,13 +195,25 @@ void recLogicalOpI(int info, int op)
if ( _ImmU_ != 0 )
{
if( _Rt_ == _Rs_ ) {
LogicalOp32ItoM((uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _ImmU_, op);
switch(op) {
case 0: xAND(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]], _ImmU_); break;
case 1: xOR(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]], _ImmU_); break;
case 2: xXOR(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]], _ImmU_); break;
default: pxAssert(0);
}
}
else {
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
if( op != 0 )
xMOV(edx, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] ]);
LogicalOp32ItoR( EAX, _ImmU_, op);
switch(op) {
case 0: xAND(eax, _ImmU_); break;
case 1: xOR(eax, _ImmU_); break;
case 2: xXOR(eax, _ImmU_); break;
default: pxAssert(0);
}
if( op != 0 )
xMOV(ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]], edx);
xMOV(ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]], eax);