mirror of https://github.com/PCSX2/pcsx2.git
3rdparty: Update CPUInfo to commit 5e3d2445e6a84d9599bee2bf78edbb4d80865e1d
This commit is contained in:
JordanTheToaster
Ty
parent
0f09b8df77
commit
356ab30e89
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@ -522,6 +522,8 @@ enum cpuinfo_uarch {
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cpuinfo_uarch_falkor = 0x00400103,
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/** Qualcomm Saphira. */
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cpuinfo_uarch_saphira = 0x00400104,
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/** Qualcomm Oryon. */
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cpuinfo_uarch_oryon = 0x00400105,
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/** Nvidia Denver. */
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cpuinfo_uarch_denver = 0x00500100,
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@ -821,6 +823,7 @@ struct cpuinfo_x86_isa {
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bool avx512_4vnniw;
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bool avx512_4fmaps;
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bool avx10_1;
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bool avx10_2;
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bool amx_bf16;
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bool amx_tile;
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bool amx_int8;
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@ -1444,6 +1447,14 @@ static inline bool cpuinfo_has_x86_avx10_1(void) {
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#endif
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}
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static inline bool cpuinfo_has_x86_avx10_2(void) {
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#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
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return cpuinfo_isa.avx10_2;
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#else
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return false;
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#endif
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}
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static inline bool cpuinfo_has_x86_hle(void) {
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#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
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return cpuinfo_isa.hle;
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@ -1,5 +1,11 @@
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#pragma once
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#ifdef _MSC_VER
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#define RESTRICT_STATIC /* nothing for MSVC */
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#else
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#define RESTRICT_STATIC restrict static
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#endif
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#include <stdbool.h>
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#include <stdint.h>
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@ -82,11 +88,11 @@ struct cpuinfo_arm_chipset {
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#ifndef __cplusplus
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CPUINFO_INTERNAL void cpuinfo_arm_chipset_to_string(
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const struct cpuinfo_arm_chipset chipset[restrict static 1],
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char name[restrict static CPUINFO_ARM_CHIPSET_NAME_MAX]);
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const struct cpuinfo_arm_chipset chipset[RESTRICT_STATIC 1],
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char name[RESTRICT_STATIC CPUINFO_ARM_CHIPSET_NAME_MAX]);
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CPUINFO_INTERNAL void cpuinfo_arm_fixup_chipset(
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struct cpuinfo_arm_chipset chipset[restrict static 1],
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struct cpuinfo_arm_chipset chipset[RESTRICT_STATIC 1],
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uint32_t cores,
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uint32_t max_cpu_freq_max);
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@ -95,23 +101,23 @@ CPUINFO_INTERNAL void cpuinfo_arm_decode_vendor_uarch(
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#if CPUINFO_ARCH_ARM
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bool has_vfpv4,
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#endif
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enum cpuinfo_vendor vendor[restrict static 1],
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enum cpuinfo_uarch uarch[restrict static 1]);
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enum cpuinfo_vendor vendor[RESTRICT_STATIC 1],
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enum cpuinfo_uarch uarch[RESTRICT_STATIC 1]);
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CPUINFO_INTERNAL void cpuinfo_arm_decode_cache(
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enum cpuinfo_uarch uarch,
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uint32_t cluster_cores,
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uint32_t midr,
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const struct cpuinfo_arm_chipset chipset[restrict static 1],
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const struct cpuinfo_arm_chipset chipset[RESTRICT_STATIC 1],
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uint32_t cluster_id,
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uint32_t arch_version,
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struct cpuinfo_cache l1i[restrict static 1],
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struct cpuinfo_cache l1d[restrict static 1],
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struct cpuinfo_cache l2[restrict static 1],
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struct cpuinfo_cache l3[restrict static 1]);
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struct cpuinfo_cache l1i[RESTRICT_STATIC 1],
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struct cpuinfo_cache l1d[RESTRICT_STATIC 1],
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struct cpuinfo_cache l2[RESTRICT_STATIC 1],
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struct cpuinfo_cache l3[RESTRICT_STATIC 1]);
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CPUINFO_INTERNAL uint32_t
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cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor processor[restrict static 1]);
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cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor processor[RESTRICT_STATIC 1]);
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#else /* defined(__cplusplus) */
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CPUINFO_INTERNAL void cpuinfo_arm_decode_cache(
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enum cpuinfo_uarch uarch,
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@ -101,7 +101,6 @@ static enum cpuinfo_uarch decode_uarch(uint32_t cpu_family, uint32_t core_index,
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return cpuinfo_uarch_unknown;
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}
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/* Small bodge until cpuinfo merges PR #246 */
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static int read_package_name_from_brand_string(char* package_name) {
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size_t size;
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if (sysctlbyname("machdep.cpu.brand_string", NULL, &size, NULL, 0) != 0) {
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@ -9,8 +9,8 @@ void cpuinfo_arm_decode_vendor_uarch(
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#if CPUINFO_ARCH_ARM
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bool has_vfpv4,
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#endif /* CPUINFO_ARCH_ARM */
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enum cpuinfo_vendor vendor[restrict static 1],
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enum cpuinfo_uarch uarch[restrict static 1]) {
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enum cpuinfo_vendor vendor[RESTRICT_STATIC 1],
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enum cpuinfo_uarch uarch[RESTRICT_STATIC 1]) {
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switch (midr_get_implementer(midr)) {
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case 'A':
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*vendor = cpuinfo_vendor_arm;
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@ -332,6 +332,9 @@ void cpuinfo_arm_decode_vendor_uarch(
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*uarch = cpuinfo_uarch_cortex_a55;
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break;
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#if CPUINFO_ARCH_ARM64
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case 0x001:
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*uarch = cpuinfo_uarch_oryon;
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break;
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case 0xC00:
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*uarch = cpuinfo_uarch_falkor;
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break;
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@ -750,11 +750,14 @@ void store_core_info_per_processor(
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if (cores) {
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processors[processor_global_index].core = cores + core_id;
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cores[core_id].core_id = core_id;
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get_core_uarch_for_efficiency(
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chip_info->chip_name,
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core_info->Processor.EfficiencyClass,
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&(cores[core_id].uarch),
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&(cores[core_id].frequency));
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if (chip_info->uarchs == NULL) {
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cpuinfo_log_error("uarch is NULL for core %d", core_id);
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return;
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}
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cores[core_id].uarch = chip_info->uarchs[0].uarch;
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cores[core_id].frequency = chip_info->uarchs[0].frequency;
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/* We don't have cluster information, so we handle it as
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* fixed 1 to (cluster / cores).
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@ -7,6 +7,9 @@
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#include <cpuinfo/internal-api.h>
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#include <cpuinfo/log.h>
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#include <arm/api.h>
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#include <arm/midr.h>
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#include "windows-arm-init.h"
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struct cpuinfo_arm_isa cpuinfo_isa;
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@ -14,62 +17,7 @@ struct cpuinfo_arm_isa cpuinfo_isa;
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static void set_cpuinfo_isa_fields(void);
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static struct woa_chip_info* get_system_info_from_registry(void);
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static struct woa_chip_info woa_chip_unknown = {
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L"Unknown",
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woa_chip_name_unknown,
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{{cpuinfo_vendor_unknown, cpuinfo_uarch_unknown, 0}}};
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/* Please add new SoC/chip info here! */
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static struct woa_chip_info woa_chips[woa_chip_name_last] = {
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/* Microsoft SQ1 Kryo 495 4 + 4 cores (3 GHz + 1.80 GHz) */
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[woa_chip_name_microsoft_sq_1] =
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{L"Microsoft SQ1",
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woa_chip_name_microsoft_sq_1,
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{{
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cpuinfo_vendor_arm,
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cpuinfo_uarch_cortex_a55,
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1800000000,
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},
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{
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cpuinfo_vendor_arm,
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cpuinfo_uarch_cortex_a76,
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3000000000,
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}}},
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/* Microsoft SQ2 Kryo 495 4 + 4 cores (3.15 GHz + 2.42 GHz) */
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[woa_chip_name_microsoft_sq_2] =
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{L"Microsoft SQ2",
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woa_chip_name_microsoft_sq_2,
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{{
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cpuinfo_vendor_arm,
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cpuinfo_uarch_cortex_a55,
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2420000000,
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},
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{cpuinfo_vendor_arm, cpuinfo_uarch_cortex_a76, 3150000000}}},
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/* Snapdragon (TM) 8cx Gen 3 @ 3.0 GHz */
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[woa_chip_name_microsoft_sq_3] =
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{L"Snapdragon (TM) 8cx Gen 3",
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woa_chip_name_microsoft_sq_3,
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{{
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cpuinfo_vendor_arm,
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cpuinfo_uarch_cortex_a78,
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2420000000,
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},
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{cpuinfo_vendor_arm, cpuinfo_uarch_cortex_x1, 3000000000}}},
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/* Microsoft Windows Dev Kit 2023 */
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[woa_chip_name_microsoft_sq_3_devkit] =
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{L"Snapdragon Compute Platform",
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woa_chip_name_microsoft_sq_3_devkit,
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{{
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cpuinfo_vendor_arm,
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cpuinfo_uarch_cortex_a78,
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2420000000,
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},
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{cpuinfo_vendor_arm, cpuinfo_uarch_cortex_x1, 3000000000}}},
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/* Ampere Altra */
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[woa_chip_name_ampere_altra] = {
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L"Ampere(R) Altra(R) Processor",
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woa_chip_name_ampere_altra,
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{{cpuinfo_vendor_arm, cpuinfo_uarch_neoverse_n1, 3000000000}}}};
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static struct woa_chip_info woa_chip_unknown = {L"Unknown", {{cpuinfo_vendor_unknown, cpuinfo_uarch_unknown, 0}}};
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BOOL CALLBACK cpuinfo_arm_windows_init(PINIT_ONCE init_once, PVOID parameter, PVOID* context) {
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struct woa_chip_info* chip_info = NULL;
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@ -87,23 +35,6 @@ BOOL CALLBACK cpuinfo_arm_windows_init(PINIT_ONCE init_once, PVOID parameter, PV
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return true;
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}
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bool get_core_uarch_for_efficiency(
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enum woa_chip_name chip,
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BYTE EfficiencyClass,
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enum cpuinfo_uarch* uarch,
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uint64_t* frequency) {
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/* For currently supported WoA chips, the Efficiency class selects
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* the pre-defined little and big core.
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* Any further supported SoC's logic should be implemented here.
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*/
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if (uarch && frequency && chip < woa_chip_name_last && EfficiencyClass < MAX_WOA_VALID_EFFICIENCY_CLASSES) {
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*uarch = woa_chips[chip].uarchs[EfficiencyClass].uarch;
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*frequency = woa_chips[chip].uarchs[EfficiencyClass].frequency;
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return true;
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}
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return false;
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}
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/* Static helper functions */
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static wchar_t* read_registry(LPCWSTR subkey, LPCWSTR value) {
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@ -149,40 +80,112 @@ static wchar_t* read_registry(LPCWSTR subkey, LPCWSTR value) {
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return text_buffer;
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}
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static uint64_t read_registry_qword(LPCWSTR subkey, LPCWSTR value) {
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DWORD key_type = 0;
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DWORD data_size = sizeof(uint64_t);
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const DWORD flags = RRF_RT_REG_QWORD; /* Only read QWORD (REG_QWORD) values */
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uint64_t qword_value = 0;
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LSTATUS result = RegGetValueW(HKEY_LOCAL_MACHINE, subkey, value, flags, &key_type, &qword_value, &data_size);
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if (result != ERROR_SUCCESS || data_size != sizeof(uint64_t)) {
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cpuinfo_log_error("Registry QWORD read error");
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return 0;
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}
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return qword_value;
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}
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static uint64_t read_registry_dword(LPCWSTR subkey, LPCWSTR value) {
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DWORD key_type = 0;
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DWORD data_size = sizeof(DWORD);
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DWORD dword_value = 0;
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LSTATUS result =
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RegGetValueW(HKEY_LOCAL_MACHINE, subkey, value, RRF_RT_REG_DWORD, &key_type, &dword_value, &data_size);
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if (result != ERROR_SUCCESS || data_size != sizeof(DWORD)) {
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cpuinfo_log_error("Registry DWORD read error");
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return 0;
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}
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return (uint64_t)dword_value;
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}
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static wchar_t* wcsndup(const wchar_t* src, size_t n) {
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size_t len = wcsnlen(src, n);
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wchar_t* dup = HeapAlloc(GetProcessHeap(), HEAP_ZERO_MEMORY, (len + 1) * sizeof(wchar_t));
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if (dup) {
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wcsncpy_s(dup, len + 1, src, len);
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dup[len] = L'\0';
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}
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return dup;
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}
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static struct core_info_by_chip_name get_core_info_from_midr(uint32_t midr, uint64_t frequency) {
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struct core_info_by_chip_name info;
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enum cpuinfo_vendor vendor;
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enum cpuinfo_uarch uarch;
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#if CPUINFO_ARCH_ARM
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bool has_vfpv4 = false;
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cpuinfo_arm_decode_vendor_uarch(midr, has_vfpv4, &vendor, &uarch);
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#else
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cpuinfo_arm_decode_vendor_uarch(midr, &vendor, &uarch);
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#endif
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info.vendor = vendor;
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info.uarch = uarch;
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info.frequency = frequency;
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return info;
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}
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static struct woa_chip_info* get_system_info_from_registry(void) {
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wchar_t* text_buffer = NULL;
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LPCWSTR cpu0_subkey = L"HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0";
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LPCWSTR chip_name_value = L"ProcessorNameString";
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LPCWSTR chip_midr_value = L"CP 4000";
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LPCWSTR chip_mhz_value = L"~MHz";
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struct woa_chip_info* chip_info = NULL;
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HANDLE heap = GetProcessHeap();
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/* Read processor model name from registry and find in the hard-coded
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* list. */
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text_buffer = read_registry(cpu0_subkey, chip_name_value);
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if (text_buffer == NULL) {
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cpuinfo_log_error("Registry read error");
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cpuinfo_log_error("Registry read error for processor name");
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return NULL;
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}
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for (uint32_t i = 0; i < (uint32_t)woa_chip_name_last; i++) {
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size_t compare_length = wcsnlen(woa_chips[i].chip_name_string, CPUINFO_PACKAGE_NAME_MAX);
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int compare_result = wcsncmp(text_buffer, woa_chips[i].chip_name_string, compare_length);
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if (compare_result == 0) {
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chip_info = woa_chips + i;
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break;
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}
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/*
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* https://developer.arm.com/documentation/100442/0100/register-descriptions/aarch32-system-registers/midr--main-id-register
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* Regedit for MIDR :
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*HKEY_LOCAL_MACHINE\HARDWARE\DESCRIPTION\System\CentralProcessor\0\CP 4000
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*/
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uint64_t midr_qword = (uint32_t)read_registry_qword(cpu0_subkey, chip_midr_value);
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if (midr_qword == 0) {
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cpuinfo_log_error("Registry read error for MIDR value");
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return NULL;
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}
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// MIDR is only 32 bits, so we need to cast it to uint32_t
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uint32_t midr_value = (uint32_t)midr_qword;
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/* Read the frequency from the registry
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* The value is in MHz, so we need to convert it to Hz */
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uint64_t frequency_mhz = read_registry_dword(cpu0_subkey, chip_mhz_value);
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if (frequency_mhz == 0) {
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cpuinfo_log_error("Registry read error for frequency value");
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return NULL;
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}
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// Convert MHz to Hz
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uint64_t frequency_hz = frequency_mhz * 1000000;
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// Allocate chip_info before using it.
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chip_info = HeapAlloc(GetProcessHeap(), HEAP_ZERO_MEMORY, sizeof(struct woa_chip_info));
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if (chip_info == NULL) {
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/* No match was found, so print a warning and assign the unknown
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* case. */
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cpuinfo_log_error(
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"Unknown chip model name '%ls'.\nPlease add new Windows on Arm SoC/chip support to arm/windows/init.c!",
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text_buffer);
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} else {
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cpuinfo_log_debug("detected chip model name: %s", chip_info->chip_name_string);
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cpuinfo_log_error("Heap allocation error for chip_info");
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return NULL;
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}
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HeapFree(heap, 0, text_buffer);
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// set chip_info fields
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chip_info->chip_name_string = wcsndup(text_buffer, CPUINFO_PACKAGE_NAME_MAX - 1);
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chip_info->uarchs[0] = get_core_info_from_midr(midr_value, frequency_hz);
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cpuinfo_log_debug("detected chip model name: %ls", chip_info->chip_name_string);
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return chip_info;
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}
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@ -216,4 +219,4 @@ static void set_cpuinfo_isa_fields(void) {
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cpuinfo_isa.pmull = crypto;
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cpuinfo_isa.crc32 = IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE) != 0;
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}
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}
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@ -3,17 +3,6 @@
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/* Efficiency class = 0 means little core, while 1 means big core for now. */
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#define MAX_WOA_VALID_EFFICIENCY_CLASSES 2
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/* List of known and supported Windows on Arm SoCs/chips. */
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enum woa_chip_name {
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woa_chip_name_microsoft_sq_1 = 0,
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woa_chip_name_microsoft_sq_2 = 1,
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woa_chip_name_microsoft_sq_3 = 2,
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woa_chip_name_microsoft_sq_3_devkit = 3,
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woa_chip_name_ampere_altra = 4,
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woa_chip_name_unknown = 5,
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woa_chip_name_last = woa_chip_name_unknown
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};
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/* Topology information hard-coded by SoC/chip name */
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struct core_info_by_chip_name {
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enum cpuinfo_vendor vendor;
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@ -26,14 +15,7 @@ struct core_info_by_chip_name {
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*/
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struct woa_chip_info {
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wchar_t* chip_name_string;
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enum woa_chip_name chip_name;
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||||
struct core_info_by_chip_name uarchs[MAX_WOA_VALID_EFFICIENCY_CLASSES];
|
||||
};
|
||||
|
||||
bool get_core_uarch_for_efficiency(
|
||||
enum woa_chip_name chip,
|
||||
BYTE EfficiencyClass,
|
||||
enum cpuinfo_uarch* uarch,
|
||||
uint64_t* frequency);
|
||||
|
||||
bool cpu_info_init_by_logical_sys_info(const struct woa_chip_info* chip_info, enum cpuinfo_vendor vendor);
|
||||
|
|
|
|||
|
|
@ -46,6 +46,8 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa(
|
|||
(max_base_index >= 7) ? cpuidex(7, 0) : (struct cpuid_regs){0, 0, 0, 0};
|
||||
const struct cpuid_regs structured_feature_info1 =
|
||||
(max_base_index >= 7) ? cpuidex(7, 1) : (struct cpuid_regs){0, 0, 0, 0};
|
||||
const struct cpuid_regs structured_feature_info2 =
|
||||
(max_base_index >= 7) ? cpuidex(0x24, 0) : (struct cpuid_regs){0, 0, 0, 0};
|
||||
|
||||
const uint32_t processor_capacity_info_index = UINT32_C(0x80000008);
|
||||
const struct cpuid_regs processor_capacity_info = (max_extended_index >= processor_capacity_info_index)
|
||||
|
|
@ -430,10 +432,17 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa(
|
|||
isa.avx512f = avx512_regs && !!(structured_feature_info0.ebx & UINT32_C(0x00010000));
|
||||
|
||||
/*
|
||||
* AVX 10.1 instructions:
|
||||
* AVX 10.1 instructions: avx 10 isa supported.
|
||||
* - Intel: edx[bit 19] in structured feature info (ecx = 1).
|
||||
*/
|
||||
isa.avx10_1 = avx512_regs && !!(structured_feature_info1.edx & UINT32_C(0x00080000));
|
||||
|
||||
/*
|
||||
* AVX 10.2 instructions: avx 10 version information.
|
||||
* - Intel: ebx[bits 0-7] in structured features info (eax = 24 ecx = 0).
|
||||
*/
|
||||
isa.avx10_2 = ((structured_feature_info2.ebx & UINT32_C(0x000000FF)) >= 2) && isa.avx10_1;
|
||||
|
||||
/*
|
||||
* AVX512PF instructions:
|
||||
* - Intel: ebx[bit 26] in structured feature info (ecx = 0).
|
||||
|
|
|
|||
|
|
@ -83,8 +83,9 @@ struct proc_cpuinfo_parser_state {
|
|||
static bool parse_line(
|
||||
const char* line_start,
|
||||
const char* line_end,
|
||||
struct proc_cpuinfo_parser_state state[restrict static 1],
|
||||
void* context,
|
||||
uint64_t line_number) {
|
||||
struct proc_cpuinfo_parser_state* restrict state = context;
|
||||
/* Empty line. Skip. */
|
||||
if (line_start == line_end) {
|
||||
return true;
|
||||
|
|
@ -215,5 +216,5 @@ bool cpuinfo_x86_linux_parse_proc_cpuinfo(
|
|||
.processors = processors,
|
||||
};
|
||||
return cpuinfo_linux_parse_multiline_file(
|
||||
"/proc/cpuinfo", BUFFER_SIZE, (cpuinfo_line_callback)parse_line, &state);
|
||||
"/proc/cpuinfo", BUFFER_SIZE, parse_line, &state);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue