PS1 mode: Adjustments to processor clock speed and CD read speed. (#2447)

switch IOP clock, CD read speed and EE/IOP cycle ratio for PSX mode

pcsx2/CDVD/CDVD.cpp

@@ -21,6 +21,7 @@
 #include <ctype.h>
 #include <wx/datetime.h>
 
+#include "CdRom.h"
 #include "CDVD.h"
 #include "CDVD_internal.h"
 #include "CDVDisoReader.h"
@@ -38,6 +39,9 @@ wxString DiscSerial;
 
 static cdvdStruct cdvd;
 
+s64 PSXCLK = 36864000;
+
+
 static __fi void SetResultSize(u8 size)
 {
 	cdvd.ResultC = size;
@@ -1416,6 +1420,9 @@ static __fi void cdvdWrite0F(u8 rt) { // TYPE
 static __fi void cdvdWrite14(u8 rt) { // PS1 MODE?? // This should be done in the SBUS_F240 bit 19 write in HwWrite.cpp
 	u32 cycle = psxRegs.cycle;
 
+	PSXCLK =  33868800;
+	setPsxSpeed();
+
 	if (rt == 0xFE)
 		Console.Warning("*PCSX2*: go PS1 mode DISC SPEED = FAST");
 	else

pcsx2/CDVD/CdRom.cpp

@@ -85,7 +85,6 @@ u8 Test23[] = { 0x43, 0x58, 0x44, 0x32, 0x39 ,0x34, 0x30, 0x51 };
 // 1x = 75 sectors per second
 // PSXCLK = 1 sec in the ps
 // so (PSXCLK / 75) / BIAS = cdr read time (linuzappz)
-//#define cdReadTime ((PSXCLK / 75) / BIAS)
 u32 cdReadTime;// = ((PSXCLK / 75) / BIAS);
 
 #define CDR_INT(eCycle)    PSX_INT(IopEvt_Cdrom, eCycle)
@@ -604,6 +603,11 @@ void cdrWrite0(u8 rt) {
 	}
 }
 
+void setPsxSpeed()
+{
+	 cdReadTime = ((PSXCLK / 75) / BIAS);
+}
+
 u8 cdrRead1(void) {
 	if (cdr.ResultReady && cdr.Ctrl & 0x1) {
 		psxHu8(0x1801) = cdr.Result[cdr.ResultP++];

pcsx2/CDVD/CdRom.h

@@ -93,6 +93,7 @@ u8   cdrRead0(void);
 u8   cdrRead1(void);
 u8   cdrRead2(void);
 u8   cdrRead3(void);
+void setPsxSpeed();
 void cdrWrite0(u8 rt);
 void cdrWrite1(u8 rt);
 void cdrWrite2(u8 rt);

pcsx2/Common.h

@@ -19,6 +19,8 @@
 
 static const u32 BIAS = 2;				// Bus is half of the actual ps2 speed
 static const u32 PS2CLK = 294912000;	//hz	/* 294.912 mhz */
+extern s64 PSXCLK;	/* 36.864 Mhz */
+
 
 #include "System.h"
 #include "Memory.h"

pcsx2/IopCommon.h

@@ -28,7 +28,6 @@
 #include "IopCounters.h"
 #include "IopSio2.h"
 #include "IopGte.h"
-static const s64 PSXCLK = 36864000;	/* 36.864 Mhz */
 //#define PSXCLK	 9216000	/* 36.864 Mhz */
 //#define PSXCLK	186864000	/* 36.864 Mhz */
 

pcsx2/R3000A.cpp

@@ -63,7 +63,7 @@ void psxReset()
 	g_iopNextEventCycle = psxRegs.cycle + 4;
 
 	psxHwReset();
-
+	PSXCLK = 36864000;
 	ioman::reset();
 	psxBiosReset();
 }

pcsx2/R3000AInterpreter.cpp

@@ -142,8 +142,16 @@ static __fi void execI()
 
 	psxRegs.pc+= 4;
 	psxRegs.cycle++;
-	iopCycleEE-=8;
-
+	
+	if ((psxHu32(HW_ICFG) & (1 << 3)))
+	{
+		//One of the Iop to EE delta clocks to be set in PS1 mode.
+		iopCycleEE-=9;
+	}
+	else
+	{   //default ps2 mode value
+		iopCycleEE-=8;
+	}
 	psxBSC[psxRegs.code >> 26]();
 }