Lets use the Gif stat enums, too. And set some of the dmac irqs to have more accurate names, and misc other things.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1672 96395faa-99c1-11dd-bbfe-3dabce05a288

pcsx2/Gif.cpp

@@ -99,7 +99,7 @@ __forceinline void gsInterrupt()
 	
 	psHu32(GIF_STAT)&= ~(GIF_STAT_APATH3 | GIF_STAT_OPH); // OPH=0 | APATH=0
 	psHu32(GIF_STAT) &= ~GIF_STAT_P3Q;
-	psHu32(GIF_STAT) &= ~0x1F000000; // QFC=0
+	psHu32(GIF_STAT) &= ~GIF_STAT_FQC; // FQC=0
 	
 	clearFIFOstuff(false);
 	hwDmacIrq(DMAC_GIF);
@@ -237,18 +237,17 @@ void GIFdma()
 	psHu32(GIF_STAT) |= 0x10000000; // FQC=31, hack ;) [ used to be 0xE00; // OPH=1 | APATH=3]
 	
 	//Path2 gets priority in intermittent mode
-	if (((psHu32(GIF_STAT) & 0x100) || (vif1.cmd & 0x7f) == 0x50) && (psHu32(GIF_MODE) & 0x4) && (Path3progress == IMAGE_MODE)) 
+	if (((psHu32(GIF_STAT) & GIF_STAT_P1Q) || (vif1.cmd & 0x7f) == 0x50) && (psHu32(GIF_MODE) & GIF_MODE_IMT) && (Path3progress == IMAGE_MODE)) 
 	{
 		GIF_LOG("Waiting VU %x, PATH2 %x, GIFMODE %x Progress %x", psHu32(GIF_STAT) & 0x100, (vif1.cmd & 0x7f), psHu32(GIF_MODE), Path3progress);
 		CPU_INT(2, 16);
 		return;
 	}
 
-	if (vif1Regs->mskpath3 || (psHu32(GIF_MODE) & 0x1)) 
+	if (vif1Regs->mskpath3 || (psHu32(GIF_MODE) & GIF_MODE_M3R)) 
 	{
 		if (gif->qwc == 0) 
 		{
-			//if ((gif->chcr & 0x10c) == 0x104) 
 			if ((CHCR::MOD(gif) == CHAIN_MODE) && CHCR::STR(gif))
 			{
 				if (!ReadTag(ptag, id)) return;
@@ -300,7 +299,7 @@ void GIFdma()
 				Console::WriteLn("GS Stall Control Source = %x, Drain = %x\n MADR = %x, STADR = %x", params (psHu32(0xe000) >> 4) & 0x3, (psHu32(0xe000) >> 6) & 0x3,gif->madr, psHu32(DMAC_STADR));
 				prevcycles = gscycles;
 				gif->tadr -= 16;
-				hwDmacIrq(DMAC_13);
+				hwDmacIrq(DMAC_STALL_SIS);
 				CPU_INT(2, gscycles);
 				gscycles = 0;
 				return;
@@ -465,7 +464,7 @@ void mfifoGIFtransfer(int qwc)
 		if (gif->tadr == spr0->madr) 
 		{
 			//if( gifqwc > 1 ) DevCon::WriteLn("gif mfifo tadr==madr but qwc = %d", params gifqwc);
-			hwDmacIrq(DMAC_14);
+			hwDmacIrq(DMAC_MFIFO_EMPTY);
 			gifstate |= GIF_STATE_EMPTY;			
 			return;
 		}
@@ -557,7 +556,7 @@ void gifMFIFOInterrupt()
 		return; 
 	}
 
-	if (((psHu32(GIF_STAT) & 0x100) || (vif1.cmd & 0x7f) == 0x50) && (psHu32(GIF_MODE) & 0x4) && Path3progress == IMAGE_MODE) //Path2 gets priority in intermittent mode
+	if (((psHu32(GIF_STAT) & GIF_STAT_P1Q) || (vif1.cmd & 0x7f) == 0x50) && (psHu32(GIF_MODE) & GIF_MODE_IMT) && Path3progress == IMAGE_MODE) //Path2 gets priority in intermittent mode
 	{
 		//GIF_LOG("Waiting VU %x, PATH2 %x, GIFMODE %x Progress %x", psHu32(GIF_STAT) & 0x100, (vif1.cmd & 0x7f), psHu32(GIF_MODE), Path3progress);
 		CPU_INT(11,mfifocycles);
@@ -570,8 +569,8 @@ void gifMFIFOInterrupt()
 		{
 			//Console::WriteLn("Empty");
 			gifstate |= GIF_STATE_EMPTY;
-			psHu32(GIF_STAT)&= ~0xE00; // OPH=0 | APATH=0
+			psHu32(GIF_STAT)&= ~GIF_STAT_IMT; // OPH=0 | APATH=0
-			hwDmacIrq(DMAC_14);
+			hwDmacIrq(DMAC_MFIFO_EMPTY);
 			return;
 		}
 		mfifoGIFtransfer(0);
@@ -591,9 +590,7 @@ void gifMFIFOInterrupt()
 	gspath3done = 0;
 	gscycles = 0;
 	
-	psHu32(GIF_STAT) &= ~(GIF_STAT_APATH3 | GIF_STAT_OPH); // OPH=0 | APATH=0
+	psHu32(GIF_STAT) &= ~(GIF_STAT_APATH3 | GIF_STAT_OPH | GIF_STAT_P3Q | GIF_STAT_FQC); // OPH, APATH, P3Q,  FQC = 0
-	psHu32(GIF_STAT) &= ~GIF_STAT_P3Q;
-	psHu32(GIF_STAT)&= ~0x1F000000; // QFC=0
 	
 	vif1Regs->stat &= ~VIF1_STAT_VGW;
 	CHCR::clearSTR(gif);

pcsx2/Hw.h

@@ -287,12 +287,15 @@ enum INTCIrqs
 	INTC_TIM2,
 	INTC_TIM3,
 };
-	
+
-#define DMAC_STAT_SIS (1<<13) // stall condition
+enum dmac_conditions
-#define DMAC_STAT_MEIS (1<<14) // mfifo empty
+{
-#define DMAC_STAT_BEIS (1<<15) // bus error
+	DMAC_STAT_SIS	= (1<<13),	 // stall condition
-#define DMAC_STAT_SIM (1<<29) // stall mask
+	DMAC_STAT_MEIS	= (1<<14),	 // mfifo empty
-#define DMAC_STAT_MEIM (1<<30) // mfifo mask
+	DMAC_STAT_BEIS	= (1<<15),	 // bus error
+	DMAC_STAT_SIM	= (1<<29),	 // stall mask
+	DMAC_STAT_MEIM	= (1<<30)	 // mfifo mask
+};
 
 enum DMACIrqs
 {
@@ -306,9 +309,11 @@ enum DMACIrqs
 	DMAC_SIF2,
 	DMAC_FROM_SPR,
 	DMAC_TO_SPR,
-	DMAC_13		= 13, // Stall?
+	
-	DMAC_14		= 14, // Transfer?
+	// We're setting error conditions through hwDmacIrq, so these correspond to the conditions above.
-	DMAC_ERROR	= 15,
+	DMAC_STALL_SIS		= 13,
+	DMAC_MFIFO_EMPTY		= 14, // Transfer?
+	DMAC_BUS_ERROR	= 15
 };
 
 enum vif0_stat_flags
@@ -327,7 +332,6 @@ enum vif0_stat_flags
 	VIF0_STAT_ER0		= (1<<12),
 	VIF0_STAT_ER1		= (1<<13),
 	VIF0_STAT_FQC		= (15<<24)
-	
 };
 
 enum vif1_stat_flags
@@ -350,23 +354,49 @@ enum vif1_stat_flags
 	VIF1_STAT_FQC		= (31<<24)
 };
 
+// These are the stat flags that are the same for vif0 & vif1,
+// for occassions where we don't neccessarily know which we are using.
+enum vif_stat_flags 
+{
+	VIF_STAT_VPS_W 	= (1),
+	VIF_STAT_VPS_D 	= (2),
+	VIF_STAT_VPS_T		= (3),
+	VIF_STAT_VPS 		= (3),
+	VIF_STAT_VEW		= (1<<2),
+	VIF_STAT_MRK		= (1<<6),
+	VIF_STAT_DBF		= (1<<7),
+	VIF_STAT_VSS		= (1<<8),
+	VIF_STAT_VFS		= (1<<9),
+	VIF_STAT_VIS		= (1<<10),
+	VIF_STAT_INT		= (1<<11),
+	VIF_STAT_ER0		= (1<<12),
+	VIF_STAT_ER1		= (1<<13)
+};
+
 //GIF_STAT 
+enum gif_stat_flags
+{
+	GIF_STAT_M3R		= (1),		// GIF_MODE Mask
+	GIF_STAT_M3P		= (1<<1),	// VIF PATH3 Mask
+	GIF_STAT_IMT		= (1<<2),	// Intermittent Transfer Mode
+	GIF_STAT_PSE		= (1<<3),	// Temporary Transfer Stop
+	GIF_STAT_IP3		= (1<<5),	// Interrupted PATH3
+	GIF_STAT_P3Q		= (1<<6),	// PATH3 request Queued
+	GIF_STAT_P2Q		= (1<<7),	// PATH2 request Queued
+	GIF_STAT_P1Q		= (1<<8),	// PATH1 request Queued
+	GIF_STAT_OPH		= (1<<9),	// Output Path (Outputting Data)
+	GIF_STAT_APATH1	= (1<<10),	// Data Transfer Path 1 (In progress)
+	GIF_STAT_APATH2	= (2<<10),	// Data Transfer Path 2 (In progress)
+	GIF_STAT_APATH3	= (3<<10),	// Data Transfer Path 3 (In progress) (Mask too)
+	GIF_STAT_DIR		= (1<<12),	// Transfer Direction
+	GIF_STAT_FQC		= (31<<24)	// QWC in GIF-FIFO
+};
 
-#define GIF_STAT_M3R    (1)  //GIF_MODE Mask
+enum gif_mode_flags
-#define GIF_STAT_M3P    (1<<1) //VIF PATH3 Mask
+{
-#define GIF_STAT_IMT    (1<<2) //Intermittent Transfer Mode
+	GIF_MODE_M3R	= (1),
-#define GIF_STAT_PSE    (1<<3) //Temporary Transfer Stop
+	GIF_MODE_IMT		= (1<<2)
-#define GIF_STAT_IP3    (1<<5) //Interrupted PATH3
+};
-#define GIF_STAT_P3Q    (1<<6) //PATH3 request Queued
-#define GIF_STAT_P2Q    (1<<7) //PATH2 request Queued
-#define GIF_STAT_P1Q    (1<<8) //PATH1 request Queued
-#define GIF_STAT_OPH    (1<<9) //Output Path (Outputting Data)
-#define GIF_STAT_APATH1 (1<<10) //Data Transfer Path 1 (In progress)
-#define GIF_STAT_APATH2 (2<<10) //Data Transfer Path 2 (In progress)
-#define GIF_STAT_APATH3 (3<<10) //Data Transfer Path 3 (In progress) (Mask too)
-#define GIF_STAT_DIR	(1<<12) //Transfer Direction
-#define GIF_STAT_FQC    (31<<24) //QWC in GIF-FIFO
-
 //DMA interrupts & masks
 enum DMAInter
 {	

pcsx2/HwWrite.cpp

@@ -726,10 +726,10 @@ void __fastcall hwWrite32_page_03( u32 mem, u32 value )
 		
 			if (value & 0x1)
 				gsGIFReset();
-			else if( value & 8 )
+			else if ( value & 8 )
-				psHu32(GIF_STAT) |= 8;
+				psHu32(GIF_STAT) |= GIF_STAT_PSE;
 			else
-				psHu32(GIF_STAT) &= ~8;
+				psHu32(GIF_STAT) &= ~GIF_STAT_PSE;
 		break;
 
 		case GIF_MODE:
@@ -738,7 +738,7 @@ void __fastcall hwWrite32_page_03( u32 mem, u32 value )
 			psHu32(GIF_MODE) = value;
 
 			// set/clear bits 0 and 2 as per the GIF_MODE value.
-			const u32 bitmask = 0x1 | 0x4;
+			const u32 bitmask = GIF_MODE_M3R | GIF_MODE_IMT;
 			psHu32(GIF_STAT) &= ~bitmask;
 			psHu32(GIF_STAT) |= (u32)value & bitmask;
 		}
@@ -1076,16 +1076,16 @@ void __fastcall hwWrite64_page_03( u32 mem, const mem64_t* srcval )
 			else
 			{
 				if( value & 8 )
-					psHu32(GIF_STAT) |= 8;
+					psHu32(GIF_STAT) |= GIF_STAT_PSE;
 				else
-					psHu32(GIF_STAT) &= ~8;
+					psHu32(GIF_STAT) &= ~GIF_STAT_PSE;
 			}
 			break;
 
 		case GIF_MODE:
 		{
 			// set/clear bits 0 and 2 as per the GIF_MODE value.
-			const u32 bitmask = 0x1 | 0x4;
+			const u32 bitmask = GIF_MODE_M3R | GIF_MODE_IMT;
 			
 			Console::Status("GIFMODE64 %x", params value);
 

pcsx2/Tags.h

@@ -305,7 +305,7 @@ namespace D_CTRL
 	{ 
 		return (std_type)((psHu32(DMAC_CTRL) & CTRL_STD) >> 6);
 	}
-	static __forceinline int RCLC() 
+	static __forceinline int RCYC() 
 	{ 
 		return ((((psHu32(DMAC_CTRL) & CTRL_RCYC) >> 3) + 1) * 8);
 	}

pcsx2/VUmicroMem.cpp

@@ -32,7 +32,7 @@ VUmicroCpu CpuVU1;		// contains a working copy of the VU1 cpu functions/API
 static void DummyExecuteVU1Block(void)
 {
 	VU0.VI[ REG_VPU_STAT ].UL &= ~0x100;
-	VU1.vifRegs->stat &= ~4; // also reset the bit (grandia 3 works)
+	VU1.vifRegs->stat &= ~VIF1_STAT_VEW; // also reset the bit (grandia 3 works)
 }
 
 void vuMicroCpuReset()

pcsx2/Vif.cpp

@@ -558,7 +558,7 @@ void vifMFIFOInterrupt()
 		--vif1.irq;
 		if (vif1Regs->stat & (VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
 		{
-			vif1Regs->stat &= ~0x1F000000; // FQC=0
+			vif1Regs->stat &= ~VIF1_STAT_FQC; // FQC=0
 			CHCR::clearSTR(vif1ch);
 			return;
 		}
@@ -577,7 +577,7 @@ void vifMFIFOInterrupt()
 					vifqwc = 0;
 					vif1.inprogress |= 0x10;
 					vif1Regs->stat &= ~VIF1_STAT_FQC; // FQC=0
-					hwDmacIrq(DMAC_14);
+					hwDmacIrq(DMAC_MFIFO_EMPTY);
 					return;
 				}
 
@@ -601,7 +601,7 @@ void vifMFIFOInterrupt()
 		//Console::WriteLn("Empty 2");
 		//vif1.inprogress |= 0x10;
 		vif1Regs->stat &= ~VIF1_STAT_FQC; // FQC=0
-		hwDmacIrq(DMAC_14);
+		hwDmacIrq(DMAC_MFIFO_EMPTY);
 	}*/
 
 	vif1.done = 1;

pcsx2/VifDma.cpp

@@ -890,17 +890,17 @@ static void vuExecMicro(u32 addr, const u32 VIFdmanum)
 		VU->vifRegs->top = VU->vifRegs->tops & 0x3ff;
 
 		/* is DBF flag set in VIF_STAT? */
-		if (VU->vifRegs->stat & 0x80)
+		if (VU->vifRegs->stat & VIF_STAT_DBF)
 		{
 			/* it is, so set tops with base, and set the stat DBF flag */ 
 			VU->vifRegs->tops = VU->vifRegs->base;
-			VU->vifRegs->stat &= ~0x80;
+			VU->vifRegs->stat &= ~VIF_STAT_DBF;
 		}
 		else
 		{
 			/* it is not, so set tops with base + ofst,  and clear stat DBF flag */
 			VU->vifRegs->tops = VU->vifRegs->base + VU->vifRegs->ofst;
-			VU->vifRegs->stat |= 0x80;
+			VU->vifRegs->stat |= VIF_STAT_DBF;
 		}
 	}
 
@@ -2060,7 +2060,7 @@ void Vif1MskPath3()  // MSKPATH3
 	{
 		//Let the Gif know it can transfer again (making sure any vif stall isnt unset prematurely)
 		Path3progress = TRANSFER_MODE; 
-		psHu32(GIF_STAT) &= ~0x2;
+		psHu32(GIF_STAT) &= ~GIF_STAT_IMT;
 		CPU_INT(2, 4);		
 	}
 	
@@ -2467,7 +2467,7 @@ __forceinline void vif1SetupTransfer()
 				if ((vif1ch->madr + vif1ch->qwc * 16) >= psHu32(DMAC_STADR))
 				{
 					// stalled
-					hwDmacIrq(DMAC_13);
+					hwDmacIrq(DMAC_STALL_SIS);
 					return;
 				}
 			}
@@ -2671,7 +2671,7 @@ void vif1Write32(u32 mem, u32 value)
 				if(vif1Regs->mskpath3)
 				{
 					vif1Regs->mskpath3 = 0;
-					psHu32(GIF_STAT) &= ~0x2;
+					psHu32(GIF_STAT) &= ~GIF_STAT_IMT;
 					if (CHCR::STR(gif)) CPU_INT(2, 4);	
 				}