Lots of work from tmkk. This update adds recompiling for several MMI opcodes, fixes bugs and adds SSSE3 detection.

Thanks again, tmkk! :)

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@522 96395faa-99c1-11dd-bbfe-3dabce05a288

pcsx2/MMI.cpp

@@ -1058,10 +1058,10 @@ void PSLLVW() {
 void PSRLVW() {
 	if (!_Rd_) return;
 
-	cpuRegs.GPR.r[_Rd_].UD[0] = (cpuRegs.GPR.r[_Rt_].UL[0] >>
+	cpuRegs.GPR.r[_Rd_].UD[0] = (s32)(cpuRegs.GPR.r[_Rt_].UL[0] >>
-								(cpuRegs.GPR.r[_Rs_].UL[0] & 0x1F));
+									 (cpuRegs.GPR.r[_Rs_].UL[0] & 0x1F));
-	cpuRegs.GPR.r[_Rd_].UD[1] = (cpuRegs.GPR.r[_Rt_].UL[2] >>
+	cpuRegs.GPR.r[_Rd_].UD[1] = (s32)(cpuRegs.GPR.r[_Rt_].UL[2] >>
-								(cpuRegs.GPR.r[_Rs_].UL[2] & 0x1F));
+									 (cpuRegs.GPR.r[_Rs_].UL[2] & 0x1F));
 }
 
 __forceinline void  _PMSUBW(int dd, int ss) 

pcsx2/System.cpp

@@ -134,11 +134,13 @@ void SysDetect()
 		"\t%sDetected SSE\n"
 		"\t%sDetected SSE2\n"
 		"\t%sDetected SSE3\n"
+		"\t%sDetected SSSE3\n"
 		"\t%sDetected SSE4.1\n", params
 			cpucaps.hasMultimediaExtensions     ? "" : "Not ",
 			cpucaps.hasStreamingSIMDExtensions  ? "" : "Not ",
 			cpucaps.hasStreamingSIMD2Extensions ? "" : "Not ",
 			cpucaps.hasStreamingSIMD3Extensions ? "" : "Not ",
+			cpucaps.hasSupplementalStreamingSIMD3Extensions ? "" : "Not ",
 			cpucaps.hasStreamingSIMD4Extensions ? "" : "Not "
 	);
 

pcsx2/x86/ix86/ix86.h

@@ -126,6 +126,7 @@ struct CAPABILITIES {
    u32 hasThermalMonitor;
    u32 hasIntel64BitArchitecture;
    u32 hasStreamingSIMD3Extensions;
+   u32 hasSupplementalStreamingSIMD3Extensions;
    u32 hasStreamingSIMD4Extensions;
 
    // AMD-specific CPU Features
@@ -1413,6 +1414,9 @@ extern void SSE2_PSHUFLW_M128_to_XMM( x86SSERegType to, uptr from, u8 imm8 );
 extern void SSE2_PSHUFHW_XMM_to_XMM( x86SSERegType to, x86SSERegType from, u8 imm8 );
 extern void SSE2_PSHUFHW_M128_to_XMM( x86SSERegType to, uptr from, u8 imm8 );
 
+extern void SSE2_SHUFPD_XMM_to_XMM( x86SSERegType to, x86SSERegType from, u8 imm8 );
+extern void SSE2_SHUFPD_M128_to_XMM( x86SSERegType to, uptr from, u8 imm8 );
+
 extern void SSE_STMXCSR( uptr from );
 extern void SSE_LDMXCSR( uptr from );
 
@@ -1610,6 +1614,13 @@ extern void SSE3_MOVSLDUP_M128_to_XMM(x86SSERegType to, uptr from);
 extern void SSE3_MOVSHDUP_XMM_to_XMM(x86SSERegType to, x86SSERegType from);
 extern void SSE3_MOVSHDUP_M128_to_XMM(x86SSERegType to, uptr from);
 
+// SSSE3
+
+extern void SSSE3_PABSB_XMM_to_XMM(x86SSERegType to, x86SSERegType from);
+extern void SSSE3_PABSW_XMM_to_XMM(x86SSERegType to, x86SSERegType from);
+extern void SSSE3_PABSD_XMM_to_XMM(x86SSERegType to, x86SSERegType from);
+extern void SSSE3_PALIGNR_XMM_to_XMM(x86SSERegType to, x86SSERegType from, u8 imm8);
+
 // SSE4.1
 
 #ifndef _MM_MK_INSERTPS_NDX
@@ -1633,6 +1644,7 @@ extern void SSE4_PMAXSD_M128_to_XMM(x86SSERegType to, uptr from);
 extern void SSE4_PMINSD_M128_to_XMM(x86SSERegType to, uptr from);
 extern void SSE4_PMAXUD_M128_to_XMM(x86SSERegType to, uptr from);
 extern void SSE4_PMINUD_M128_to_XMM(x86SSERegType to, uptr from);
+extern void SSE4_PMULDQ_XMM_to_XMM(x86SSERegType to, x86SSERegType from);
 
 //*********************
 // SSE-X - uses both SSE,SSE2 code and tries to keep consistensies between the data

pcsx2/x86/ix86/ix86_cpudetect.cpp

@@ -376,6 +376,10 @@ void cpudetectInit()
 
 	cpucaps.hasStreamingSIMD4Extensions = ( cpuinfo.x86Flags2 >> 19 ) & 1; //sse4.1   
 
+	// --> SSSE3 detection <--
+
+	cpucaps.hasSupplementalStreamingSIMD3Extensions = ( cpuinfo.x86Flags2 >> 9 ) & 1; //ssse3  
+
 	// --> SSE3 detection <--
 	// These instructions may not be recognized by some compilers, or may not have
 	// intrinsic equivalents available.  So we use our own ix86 emitter to generate

pcsx2/x86/ix86/ix86_sse.cpp

@@ -661,6 +661,13 @@ __forceinline void SSE_SHUFPS_RmOffset_to_XMM( x86SSERegType to, x86IntRegType f
 	write8(imm8);
 }
 
+//////////////////////////////////////////////////////////////////////////////////////
+//**********************************************************************************/
+//SHUFPD: Shuffle Packed Double-Precision FP Values                                *
+//**********************************************************************************
+__forceinline void SSE2_SHUFPD_XMM_to_XMM( x86SSERegType to, x86SSERegType from, u8 imm8 )	{ SSERtoR66( 0xC60F ); write8( imm8 ); }
+__forceinline void SSE2_SHUFPD_M128_to_XMM( x86SSERegType to, uptr from, u8 imm8 )		{ SSEMtoR66( 0xC60F ); write8( imm8 ); }
+
 ////////////////////////////////////////////////////////////////////////////////////
 //**********************************************************************************/
 //PSHUFD: Shuffle Packed DoubleWords                                               *
@@ -1076,6 +1083,41 @@ __forceinline void SSE3_MOVSLDUP_M128_to_XMM(x86SSERegType to, uptr from) { writ
 __forceinline void SSE3_MOVSHDUP_XMM_to_XMM(x86SSERegType to, x86SSERegType from) { write8(0xf3); SSERtoR(0x160f); }
 __forceinline void SSE3_MOVSHDUP_M128_to_XMM(x86SSERegType to, uptr from) { write8(0xf3); SSEMtoR(0x160f, 0); }
 
+// SSSE3
+
+__forceinline void SSSE3_PABSB_XMM_to_XMM(x86SSERegType to, x86SSERegType from)
+{
+	write8(0x66);
+	RexRB(0, to, from);
+	write24(0x1C380F);
+	ModRM(3, to, from);
+}
+
+__forceinline void SSSE3_PABSW_XMM_to_XMM(x86SSERegType to, x86SSERegType from)
+{
+	write8(0x66);
+	RexRB(0, to, from);
+	write24(0x1D380F);
+	ModRM(3, to, from);
+}
+
+__forceinline void SSSE3_PABSD_XMM_to_XMM(x86SSERegType to, x86SSERegType from)
+{
+	write8(0x66);
+	RexRB(0, to, from);
+	write24(0x1E380F);
+	ModRM(3, to, from);
+}
+
+__forceinline void SSSE3_PALIGNR_XMM_to_XMM(x86SSERegType to, x86SSERegType from, u8 imm8)
+{
+	write8(0x66);
+	RexRB(0, to, from);
+	write24(0x0F3A0F);
+	ModRM(3, to, from);
+	write8(imm8);
+}
+
 // SSE4.1
 
 __forceinline void SSE4_DPPS_XMM_to_XMM(x86SSERegType to, x86SSERegType from, u8 imm8) 
@@ -1224,6 +1266,14 @@ __forceinline void SSE4_PMINUD_M128_to_XMM(x86SSERegType to, uptr from)
 	write32(MEMADDR(from, 4));
 }
 
+__forceinline void SSE4_PMULDQ_XMM_to_XMM(x86SSERegType to, x86SSERegType from)
+{
+	write8(0x66);
+	RexRB(0, to, from);
+	write24(0x28380F);
+	ModRM(3, to, from);
+}
+
 // SSE-X
 __forceinline void SSEX_MOVDQA_M128_to_XMM( x86SSERegType to, uptr from )
 {