mirror of https://github.com/PCSX2/pcsx2.git
parent
fc882c9efc
commit
328e358b21
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@ -114,7 +114,7 @@ int IPU1dma()
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//We need to make sure GIF has flushed before sending IPU data, it seems to REALLY screw FFX videos
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//We need to make sure GIF has flushed before sending IPU data, it seems to REALLY screw FFX videos
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if(!ipu1ch.chcr.STR || IPU1Status.DMAMode == 2)
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if(!ipu1ch.chcr.STR || IPU1Status.DMAMode == DMA_MODE_INTERLEAVE)
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{
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{
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//We MUST stop the IPU from trying to fill the FIFO with more data if the DMA has been suspended
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//We MUST stop the IPU from trying to fill the FIFO with more data if the DMA has been suspended
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//if we don't, we risk causing the data to go out of sync with the fifo and we end up losing some!
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//if we don't, we risk causing the data to go out of sync with the fifo and we end up losing some!
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@ -409,6 +409,6 @@ IPU_FORCEINLINE void ipu1Interrupt()
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DMA_LOG("IPU1 DMA End");
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DMA_LOG("IPU1 DMA End");
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ipu1ch.chcr.STR = false;
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ipu1ch.chcr.STR = false;
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IPU1Status.DMAMode = 2;
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IPU1Status.DMAMode = DMA_MODE_INTERLEAVE;
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hwDmacIrq(DMAC_TO_IPU);
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hwDmacIrq(DMAC_TO_IPU);
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}
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}
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@ -33,6 +33,7 @@ struct IPUStatus {
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#define DMA_MODE_NORMAL 0
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#define DMA_MODE_NORMAL 0
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#define DMA_MODE_CHAIN 1
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#define DMA_MODE_CHAIN 1
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#define DMA_MODE_INTERLEAVE 2
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#define IPU1_TAG_FOLLOW 0
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#define IPU1_TAG_FOLLOW 0
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#define IPU1_TAG_QWC 1
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#define IPU1_TAG_QWC 1
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