mirror of https://github.com/PCSX2/pcsx2.git
tekken 5 works again with the gamefix. that game is really picky :/
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@111 a6443dda-0b58-4228-96e9-037be469359c
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@ -69,7 +69,7 @@
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//------------ SPECIAL GAME FIXES!!! ---------------
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//#define CHECK_FPUCLAMPHACK (Config.GameFixes & 0x1) // Special Fix for GT4, different clamping for FPU (Note: sets negative infinity to positive fMax when clamping, which the real ps2 doesn't do)
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#define CHECK_FPUCLAMPHACK (Config.GameFixes & 0x4) // Special Fix for Tekken 5, different clamping for FPU (sets infinities to zero)
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#define CHECK_FPUCLAMPHACK (Config.GameFixes & 0x4) // Special Fix for Tekken 5, different clamping for FPU (sets NaN to zero; doesn't clamp infinities)
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#define CHECK_VUCLIPHACK (Config.GameFixes & 0x2) // Special Fix for GoW, updates the clipflag differently in recVUMI_CLIP() (note: turning this hack on, breaks Rockstar games)
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#define CHECK_FRAMELIMIT (Config.Options&PCSX2_FRAMELIMIT_MASK)
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@ -772,8 +772,8 @@ static u32 s_signbit = 0x80000000;
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extern int g_VuNanHandling;
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void fpuFloat(regd) {
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if (CHECK_FPU_OVERFLOW) { // MIN() must be before MAX()!
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SSE_MINSS_M32_to_XMM(regd, (uptr)&g_maxvals[0]);
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if (CHECK_FPU_OVERFLOW && !CHECK_FPUCLAMPHACK) { // Tekken 5 doesn't like clamping infinities.
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SSE_MINSS_M32_to_XMM(regd, (uptr)&g_maxvals[0]); // MIN() must be before MAX()! So that NaN's become +Maximum
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SSE_MAXSS_M32_to_XMM(regd, (uptr)&g_minvals[0]);
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}
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}
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@ -784,7 +784,7 @@ void ClampValues(regd) {
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void ClampValues2(regd) {
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if (CHECK_FPUCLAMPHACK) {
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if (CHECK_FPUCLAMPHACK) { // Fixes Tekken 5
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int t5reg = _allocTempXMMreg(XMMT_FPS, -1);
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SSE_XORPS_XMM_to_XMM(t5reg, t5reg);
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@ -792,10 +792,10 @@ void ClampValues2(regd) {
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SSE_ANDPS_XMM_to_XMM(regd, t5reg);
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SSE_MINSS_M32_to_XMM(regd, (uptr)&g_maxvals[0]);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)&g_minvals[0]);
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/* --- Its odd but tekken dosn't like Infinities to be clamped. --- */
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//SSE_MINSS_M32_to_XMM(regd, (uptr)&g_maxvals[0]);
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//SSE_MAXSS_M32_to_XMM(regd, (uptr)&g_minvals[0]);
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_freeXMMreg(t5reg);
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}
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else fpuFloat(regd);
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@ -817,7 +817,7 @@ int recCommutativeOp(int info, int regd, int op)
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case PROCESS_EE_S:
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if (regd == EEREC_S) {
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
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if (CHECK_FPU_EXTRA_OVERFLOW && !CHECK_FPUCLAMPHACK && (op < 2)) { fpuFloat(regd); fpuFloat(t0reg); }
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if (CHECK_FPU_EXTRA_OVERFLOW && /*!CHECK_FPUCLAMPHACK &&*/ (op < 2)) { fpuFloat(regd); fpuFloat(t0reg); }
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recComOpXMM_to_XMM[op](regd, t0reg);
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}
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else {
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@ -875,7 +875,7 @@ FPURECOMPILE_CONSTCODE(ADD_S, XMMINFO_WRITED|XMMINFO_READS|XMMINFO_READT);
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void recSUBhelper(int regd, int regt)
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{
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if (CHECK_FPU_EXTRA_OVERFLOW && !CHECK_FPUCLAMPHACK) { fpuFloat(regd); fpuFloat(regt); }
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if (CHECK_FPU_EXTRA_OVERFLOW /*&& !CHECK_FPUCLAMPHACK*/) { fpuFloat(regd); fpuFloat(regt); }
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SSE_SUBSS_XMM_to_XMM(regd, regt);
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}
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