mirror of https://github.com/PCSX2/pcsx2.git
DEV9: Improved SPEED emulation, also hookup ATA emulation
This commit is contained in:
TheLastRar
refractionpcsx2
parent
afc9412191
commit
31a3ee3cbc
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@ -157,6 +157,7 @@ s32 DEV9init()
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DEV9_LOG("DEV9init\n");
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memset(&dev9, 0, sizeof(dev9));
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dev9.ata = new ATA();
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DEV9_LOG("DEV9init2\n");
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DEV9_LOG("DEV9init3\n");
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@ -235,7 +236,7 @@ s32 DEV9init()
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void DEV9shutdown()
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{
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DEV9_LOG("DEV9shutdown\n");
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delete dev9.ata;
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if (logFile)
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DEV9Log.Close();
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}
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@ -259,6 +260,9 @@ s32 DEV9open(void* pDsp)
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ghc::filesystem::path hddPath(config.Hdd);
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#endif
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if (hddPath.empty())
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config.hddEnable = false;
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if (hddPath.is_relative())
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{
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//GHC uses UTF8 on all platforms
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@ -266,33 +270,35 @@ s32 DEV9open(void* pDsp)
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hddPath = path / hddPath;
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}
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#ifdef ENABLE_ATA
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ata_init();
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#endif
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if (config.hddEnable)
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{
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if (dev9.ata->Open(hddPath) != 0)
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config.hddEnable = false;
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}
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return _DEV9open();
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}
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void DEV9close()
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{
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DEV9_LOG("DEV9close\n");
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#ifdef ENABLE_ATA
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ata_term();
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#endif
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dev9.ata->Close();
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_DEV9close();
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}
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int DEV9irqHandler(void)
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{
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//dev9Ru16(SPD_R_INTR_STAT)|= dev9.irqcause;
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DEV9_LOG("_DEV9irqHandler %x, %x\n", dev9.irqcause, dev9Ru16(SPD_R_INTR_MASK));
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if (dev9.irqcause & dev9Ru16(SPD_R_INTR_MASK))
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DEV9_LOG("_DEV9irqHandler %x, %x\n", dev9.irqcause, dev9.irqmask);
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if (dev9.irqcause & dev9.irqmask)
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return 1;
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return 0;
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}
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void _DEV9irq(int cause, int cycles)
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{
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DEV9_LOG("_DEV9irq %x, %x\n", cause, dev9Ru16(SPD_R_INTR_MASK));
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DEV9_LOG("_DEV9irq %x, %x\n", cause, dev9.irqmask);
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dev9.irqcause |= cause;
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@ -302,6 +308,66 @@ void _DEV9irq(int cause, int cycles)
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dev9Irq(cycles);
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}
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//Fakes SPEED FIFO
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void HDDWriteFIFO()
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{
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if (dev9.ata->dmaReady && (dev9.if_ctrl & SPD_IF_ATA_DMAEN))
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{
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const int unread = (dev9.fifo_bytes_write - dev9.fifo_bytes_read);
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const int spaceSectors = (SPD_DBUF_AVAIL_MAX * 512 - unread) / 512;
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if (spaceSectors < 0)
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{
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DEV9_LOG_ERROR("No Space on SPEED FIFO");
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pxAssert(false);
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abort();
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}
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const int readSectors = dev9.ata->nsectorLeft < spaceSectors ? dev9.ata->nsectorLeft : spaceSectors;
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dev9.fifo_bytes_write += readSectors * 512;
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dev9.ata->nsectorLeft -= readSectors;
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}
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//FIFOIntr();
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}
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void HDDReadFIFO()
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{
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if (dev9.ata->dmaReady && (dev9.if_ctrl & SPD_IF_ATA_DMAEN))
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{
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const int writeSectors = (dev9.fifo_bytes_write - dev9.fifo_bytes_read) / 512;
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dev9.fifo_bytes_read += writeSectors * 512;
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dev9.ata->nsectorLeft -= writeSectors;
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}
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//FIFOIntr();
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}
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void IOPReadFIFO(int bytes)
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{
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dev9.fifo_bytes_read += bytes;
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if (dev9.fifo_bytes_read > dev9.fifo_bytes_write)
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DEV9_LOG_ERROR("UNDERFLOW BY IOP\n");
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//FIFOIntr();
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}
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void IOPWriteFIFO(int bytes)
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{
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dev9.fifo_bytes_write += bytes;
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if (dev9.fifo_bytes_write - SPD_DBUF_AVAIL_MAX * 512 > dev9.fifo_bytes_read)
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DEV9_LOG_ERROR("OVERFLOW BY IOP\n");
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//FIFOIntr();
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}
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void FIFOIntr()
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{
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//FIFO Buffer Full/Empty
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const int unread = (dev9.fifo_bytes_write - dev9.fifo_bytes_read);
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if (unread == 0)
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{
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if ((dev9.irqcause & SPD_INTR_ATA_FIFO_EMPTY) == 0)
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_DEV9irq(SPD_INTR_ATA_FIFO_EMPTY, 1);
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}
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if (unread == SPD_DBUF_AVAIL_MAX * 512)
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{
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//Log_Error("FIFO Full");
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//INTR Full?
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}
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}
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u8 DEV9read8(u32 addr)
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{
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@ -311,17 +377,18 @@ u8 DEV9read8(u32 addr)
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u8 hard;
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if (addr >= ATA_DEV9_HDD_BASE && addr < ATA_DEV9_HDD_END)
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{
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#ifdef ENABLE_ATA
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return ata_read<1>(addr);
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#else
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DEV9_LOG_ERROR("ATA does not support 8bit reads %lx\n", addr);
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return 0;
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#endif
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}
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if (addr >= SMAP_REGBASE && addr < FLASH_REGBASE)
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{
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//smap
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return smap_read8(addr);
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}
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if ((addr >= FLASH_REGBASE) && (addr < (FLASH_REGBASE + FLASH_REGSIZE)))
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{
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return (u8)FLASHread32(addr, 1);
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}
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switch (addr)
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{
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@ -353,25 +420,19 @@ u8 DEV9read8(u32 addr)
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}
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else
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hard = 0;
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DEV9_LOG_VERB("SPD_R_PIO_DATA 8bit read %x\n", hard);
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return hard;
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case DEV9_R_REV:
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hard = 0x32; // expansion bay
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break;
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DEV9_LOG_VERB("DEV9_R_REV 8bit read %x\n", hard);
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return hard;
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default:
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if ((addr >= FLASH_REGBASE) && (addr < (FLASH_REGBASE + FLASH_REGSIZE)))
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{
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return (u8)FLASHread32(addr, 1);
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}
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hard = dev9Ru8(addr);
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DEV9_LOG("*Unknown 8bit read at address %lx value %x\n", addr, hard);
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DEV9_LOG_ERROR("*Unknown 8bit read at address %lx value %x\n", addr, hard);
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return hard;
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}
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DEV9_LOG("*Known 8bit read at address %lx value %x\n", addr, hard);
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return hard;
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}
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u16 DEV9read16(u32 addr)
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@ -382,23 +443,28 @@ u16 DEV9read16(u32 addr)
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u16 hard;
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if (addr >= ATA_DEV9_HDD_BASE && addr < ATA_DEV9_HDD_END)
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{
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#ifdef ENABLE_ATA
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return ata_read<2>(addr);
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#else
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return 0;
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#endif
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return dev9.ata->Read16(addr);
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}
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if (addr >= SMAP_REGBASE && addr < FLASH_REGBASE)
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{
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//smap
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return smap_read16(addr);
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}
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if ((addr >= FLASH_REGBASE) && (addr < (FLASH_REGBASE + FLASH_REGSIZE)))
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{
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return (u16)FLASHread32(addr, 2);
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}
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switch (addr)
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{
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case SPD_R_INTR_STAT:
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DEV9_LOG_VERB("SPD_R_INTR_STAT 16bit read %x\n", dev9.irqcause);
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return dev9.irqcause;
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case SPD_R_INTR_MASK:
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DEV9_LOG("SPD_R_INTR_MASK 16bit read %x\n", dev9.irqmask);
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return dev9.irqmask;
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case SPD_R_PIO_DATA:
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/*if(dev9.eeprom_dir!=1)
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@ -427,48 +493,86 @@ u16 DEV9read16(u32 addr)
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}
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else
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hard = 0;
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DEV9_LOG_VERB("SPD_R_PIO_DATA 16bit read %x\n", hard);
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return hard;
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case DEV9_R_REV:
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hard = 0x0030; // expansion bay
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break;
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//hard = 0x0030; // expansion bay
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DEV9_LOG_VERB("DEV9_R_REV 16bit read %x\n", dev9.irqmask);
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hard = 0x0032;
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return hard;
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case SPD_R_REV_1:
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DEV9_LOG_VERB("SPD_R_REV_1 16bit read %x\n", 0);
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return 0;
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case SPD_R_REV_2:
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hard = 0x0011;
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DEV9_LOG("STD_R_REV_1 16bit read %x\n", hard);
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DEV9_LOG_VERB("STD_R_REV_1 16bit read %x\n", hard);
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return hard;
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case SPD_R_REV_3:
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// bit 0: smap
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// bit 1: hdd
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// bit 5: flash
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hard = 0;
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/*if (config.hddEnable) {
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hard|= 0x2;
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}*/
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if (config.hddEnable)
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hard |= SPD_CAPS_ATA;
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if (config.ethEnable)
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{
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hard |= 0x1;
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}
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hard |= 0x20; //flash
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break;
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hard |= SPD_CAPS_SMAP;
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hard |= SPD_CAPS_FLASH;
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DEV9_LOG_VERB("SPD_R_REV_3 16bit read %x\n", hard);
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return hard;
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case SPD_R_0e:
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hard = 0x0002;
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break;
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default:
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if ((addr >= FLASH_REGBASE) && (addr < (FLASH_REGBASE + FLASH_REGSIZE)))
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hard = 0x0002; //Have HDD inserted
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DEV9_LOG_VERB("SPD_R_0e 16bit read %x\n", hard);
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return hard;
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case SPD_R_XFR_CTRL:
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DEV9_LOG_VERB("SPD_R_XFR_CTRL 16bit read %x\n", dev9.xfr_ctrl);
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return dev9.xfr_ctrl;
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case SPD_R_DBUF_STAT:
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{
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return (u16)FLASHread32(addr, 2);
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hard = 0;
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if (dev9.if_ctrl & SPD_IF_READ) //Semi async
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{
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HDDWriteFIFO(); //Yes this is not a typo
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}
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else
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{
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HDDReadFIFO();
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}
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FIFOIntr();
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const u8 count = (u8)((dev9.fifo_bytes_write - dev9.fifo_bytes_read) / 512);
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if (dev9.xfr_ctrl & SPD_XFR_WRITE) //or ifRead?
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{
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hard = (u8)(SPD_DBUF_AVAIL_MAX - count);
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hard |= (count == 0) ? SPD_DBUF_STAT_1 : (u16)0;
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hard |= (count > 0) ? SPD_DBUF_STAT_2 : (u16)0;
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}
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else
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{
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hard = count;
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hard |= (count < SPD_DBUF_AVAIL_MAX) ? SPD_DBUF_STAT_1 : (u16)0;
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hard |= (count == 0) ? SPD_DBUF_STAT_2 : (u16)0;
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//If overflow (HDD->SPEED), set both SPD_DBUF_STAT_2 & SPD_DBUF_STAT_FULL
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//and overflow INTR set
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}
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if (count == SPD_DBUF_AVAIL_MAX)
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{
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hard |= SPD_DBUF_STAT_FULL;
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}
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DEV9_LOG_VERB("SPD_R_DBUF_STAT 16bit read %x\n", hard);
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return hard;
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}
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case SPD_R_IF_CTRL:
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DEV9_LOG_VERB("SPD_R_IF_CTRL 16bit read %x\n", dev9.if_ctrl);
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return dev9.if_ctrl;
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default:
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hard = dev9Ru16(addr);
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DEV9_LOG("*Unknown 16bit read at address %lx value %x\n", addr, hard);
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DEV9_LOG_ERROR("*Unknown 16bit read at address %lx value %x\n", addr, hard);
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return hard;
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}
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DEV9_LOG("*Known 16bit read at address %lx value %x\n", addr, hard);
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return hard;
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}
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u32 DEV9read32(u32 addr)
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@ -479,32 +583,22 @@ u32 DEV9read32(u32 addr)
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u32 hard;
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if (addr >= ATA_DEV9_HDD_BASE && addr < ATA_DEV9_HDD_END)
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{
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#ifdef ENABLE_ATA
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return ata_read<4>(addr);
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#else
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DEV9_LOG_ERROR("ATA does not support 32bit reads %lx\n", addr);
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return 0;
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#endif
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}
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if (addr >= SMAP_REGBASE && addr < FLASH_REGBASE)
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{
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//smap
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return smap_read32(addr);
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}
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// switch (addr) {
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// default:
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if ((addr >= FLASH_REGBASE) && (addr < (FLASH_REGBASE + FLASH_REGSIZE)))
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{
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return (u32)FLASHread32(addr, 4);
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}
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hard = dev9Ru32(addr);
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DEV9_LOG("*Unknown 32bit read at address %lx value %x\n", addr, hard);
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DEV9_LOG_ERROR("*Unknown 32bit read at address %lx value %x\n", addr, hard);
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return hard;
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// }
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// DEV9_LOG("*Known 32bit read at address %lx: %lx\n", addr, hard);
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// return hard;
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}
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void DEV9write8(u32 addr, u8 value)
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@ -525,21 +619,28 @@ void DEV9write8(u32 addr, u8 value)
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smap_write8(addr, value);
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return;
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}
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if ((addr >= FLASH_REGBASE) && (addr < (FLASH_REGBASE + FLASH_REGSIZE)))
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{
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FLASHwrite32(addr, (u32)value, 1);
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return;
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}
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switch (addr)
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{
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case 0x10000020:
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DEV9_LOG_ERROR("SPD_R_INTR_CAUSE, WTFH ?\n");
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dev9.irqcause = 0xff;
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break;
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case SPD_R_INTR_STAT:
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emu_printf("SPD_R_INTR_STAT , WTFH ?\n");
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DEV9_LOG_ERROR("SPD_R_INTR_STAT, WTFH ?\n");
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dev9.irqcause = value;
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return;
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case SPD_R_INTR_MASK:
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emu_printf("SPD_R_INTR_MASK8 , WTFH ?\n");
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DEV9_LOG_ERROR("SPD_R_INTR_MASK8, WTFH ?\n");
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break;
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case SPD_R_PIO_DIR:
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//DEV9_LOG("SPD_R_PIO_DIR 8bit write %x\n", value);
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DEV9_LOG_VERB("SPD_R_PIO_DIR 8bit write %x\n", value);
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if ((value & 0xc0) != 0xc0)
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return;
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@ -553,7 +654,7 @@ void DEV9write8(u32 addr, u8 value)
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return;
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case SPD_R_PIO_DATA:
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//DEV9_LOG("SPD_R_PIO_DATA 8bit write %x\n", value);
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DEV9_LOG_VERB("SPD_R_PIO_DATA 8bit write %x\n", value);
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if ((value & 0xc0) != 0xc0)
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return;
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@ -600,23 +701,16 @@ void DEV9write8(u32 addr, u8 value)
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}
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}
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break;
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}
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return;
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default:
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if ((addr >= FLASH_REGBASE) && (addr < (FLASH_REGBASE + FLASH_REGSIZE)))
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{
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FLASHwrite32(addr, (u32)value, 1);
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DEV9_LOG_ERROR("Unkown EEPROM COMMAND\n");
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break;
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}
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return;
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default:
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dev9Ru8(addr) = value;
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DEV9_LOG_ERROR("*Unknown 8bit write at address %lx value %x\n", addr, value);
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return;
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}
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dev9Ru8(addr) = value;
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DEV9_LOG("*Unknown 8bit write at address %lx value %x\n", addr, value);
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return;
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}
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dev9Ru8(addr) = value;
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DEV9_LOG("*Known 8bit write at address %lx value %x\n", addr, value);
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}
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void DEV9write16(u32 addr, u16 value)
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@ -626,9 +720,7 @@ void DEV9write16(u32 addr, u16 value)
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if (addr >= ATA_DEV9_HDD_BASE && addr < ATA_DEV9_HDD_END)
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{
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#ifdef ENABLE_ATA
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ata_write<2>(addr, value);
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#endif
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dev9.ata->Write16(addr, value);
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return;
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}
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if (addr >= SMAP_REGBASE && addr < FLASH_REGBASE)
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@ -637,18 +729,26 @@ void DEV9write16(u32 addr, u16 value)
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smap_write16(addr, value);
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return;
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||||
}
|
||||
if ((addr >= FLASH_REGBASE) && (addr < (FLASH_REGBASE + FLASH_REGSIZE)))
|
||||
{
|
||||
FLASHwrite32(addr, (u32)value, 2);
|
||||
return;
|
||||
}
|
||||
|
||||
switch (addr)
|
||||
{
|
||||
case SPD_R_INTR_MASK:
|
||||
if ((dev9Ru16(SPD_R_INTR_MASK) != value) && ((dev9Ru16(SPD_R_INTR_MASK) | value) & dev9.irqcause))
|
||||
DEV9_LOG_VERB("SPD_R_INTR_MASK 16bit write %x , checking for masked/unmasked interrupts\n", value);
|
||||
if ((dev9.irqmask != value) && ((dev9.irqmask | value) & dev9.irqcause))
|
||||
{
|
||||
DEV9_LOG("SPD_R_INTR_MASK16=0x%X , checking for masked/unmasked interrupts\n", value);
|
||||
DEV9_LOG_VERB("SPD_R_INTR_MASK16 firing unmasked interrupts\n");
|
||||
dev9Irq(1);
|
||||
}
|
||||
dev9.irqmask = value;
|
||||
break;
|
||||
|
||||
case SPD_R_PIO_DIR:
|
||||
//DEV9_LOG("SPD_R_PIO_DIR 16bit write %x\n", value);
|
||||
DEV9_LOG_VERB("SPD_R_PIO_DIR 16bit write %x\n", value);
|
||||
|
||||
if ((value & 0xc0) != 0xc0)
|
||||
return;
|
||||
|
|
@ -662,7 +762,7 @@ void DEV9write16(u32 addr, u16 value)
|
|||
return;
|
||||
|
||||
case SPD_R_PIO_DATA:
|
||||
//DEV9_LOG("SPD_R_PIO_DATA 16bit write %x\n", value);
|
||||
DEV9_LOG_VERB("SPD_R_PIO_DATA 16bit write %x\n", value);
|
||||
|
||||
if ((value & 0xc0) != 0xc0)
|
||||
return;
|
||||
|
|
@ -709,24 +809,220 @@ void DEV9write16(u32 addr, u16 value)
|
|||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
DEV9_LOG_ERROR("Unkown EEPROM COMMAND\n");
|
||||
break;
|
||||
}
|
||||
return;
|
||||
|
||||
case SPD_R_DMA_CTRL:
|
||||
DEV9_LOG_VERB("SPD_R_IF_CTRL 16bit write %x\n", value);
|
||||
dev9.dma_ctrl = value;
|
||||
|
||||
if (value & SPD_DMA_TO_SMAP)
|
||||
DEV9_LOG_VERB("SPD_R_DMA_CTRL DMA For SMAP\n");
|
||||
else
|
||||
DEV9_LOG_VERB("SPD_R_DMA_CTRL DMA For ATA\n");
|
||||
|
||||
if ((value & SPD_DMA_FASTEST) != 0)
|
||||
DEV9_LOG_VERB("SPD_R_DMA_CTRL Fastest DMA Mode\n");
|
||||
else
|
||||
DEV9_LOG_VERB("SPD_R_DMA_CTRL Slower DMA Mode\n");
|
||||
|
||||
if ((value & SPD_DMA_WIDE) != 0)
|
||||
DEV9_LOG_VERB("SPD_R_DMA_CTRL Wide(32bit) DMA Mode Set\n");
|
||||
else
|
||||
DEV9_LOG_VERB("SPD_R_DMA_CTRL 16bit DMA Mode\n");
|
||||
|
||||
if ((value & SPD_DMA_PAUSE) != 0)
|
||||
DEV9_LOG_ERROR("SPD_R_DMA_CTRL Pause DMA\n");
|
||||
|
||||
if ((value & 0b1111111111101000) != 0)
|
||||
DEV9_LOG_ERROR("SPD_R_DMA_CTRL Unkown value written %x\n", value);
|
||||
|
||||
break;
|
||||
case SPD_R_XFR_CTRL:
|
||||
DEV9_LOG_VERB("SPD_R_IF_CTRL 16bit write %x\n", value);
|
||||
dev9.xfr_ctrl = value;
|
||||
|
||||
if (value & SPD_XFR_WRITE)
|
||||
DEV9_LOG_VERB("SPD_R_XFR_CTRL Set Write\n");
|
||||
else
|
||||
DEV9_LOG_VERB("SPD_R_XFR_CTRL Set Read\n");
|
||||
|
||||
if ((value & (1 << 1)) != 0)
|
||||
DEV9_LOG_VERB("SPD_R_XFR_CTRL Unkown Bit 1\n");
|
||||
|
||||
if ((value & (1 << 2)) != 0)
|
||||
DEV9_LOG_VERB("SPD_R_XFR_CTRL Unkown Bit 2\n");
|
||||
|
||||
if (value & SPD_XFR_DMAEN)
|
||||
DEV9_LOG_VERB("SPD_R_XFR_CTRL For DMA Enabled\n");
|
||||
else
|
||||
DEV9_LOG_VERB("SPD_R_XFR_CTRL For DMA Disabled\n");
|
||||
|
||||
if ((value & 0b1111111101111000) != 0)
|
||||
{
|
||||
DEV9_LOG_ERROR("SPD_R_XFR_CTRL Unkown value written %x\n", value);
|
||||
}
|
||||
|
||||
return;
|
||||
break;
|
||||
case SPD_R_DBUF_STAT:
|
||||
DEV9_LOG_VERB("SPD_R_DBUF_STAT 16bit write %x\n", value);
|
||||
|
||||
if ((value & SPD_DBUF_RESET_FIFO) != 0)
|
||||
{
|
||||
DEV9_LOG_VERB("SPD_R_XFR_CTRL Reset FIFO\n");
|
||||
dev9.fifo_bytes_write = 0;
|
||||
dev9.fifo_bytes_read = 0;
|
||||
dev9.xfr_ctrl &= ~SPD_XFR_WRITE; //?
|
||||
dev9.if_ctrl |= SPD_IF_READ; //?
|
||||
|
||||
FIFOIntr();
|
||||
}
|
||||
|
||||
if (value != 3)
|
||||
DEV9_LOG_ERROR("SPD_R_38 16bit write %x Which != 3!!!", value);
|
||||
break;
|
||||
|
||||
case SPD_R_IF_CTRL:
|
||||
DEV9_LOG_VERB("SPD_R_IF_CTRL 16bit write %x\n", value);
|
||||
dev9.if_ctrl = value;
|
||||
|
||||
if (value & SPD_IF_UDMA)
|
||||
DEV9_LOG_VERB("IF_CTRL UDMA Enabled\n");
|
||||
else
|
||||
DEV9_LOG_VERB("IF_CTRL UDMA Disabled\n");
|
||||
if (value & SPD_IF_READ)
|
||||
DEV9_LOG_VERB("IF_CTRL DMA Is ATA Read\n");
|
||||
else
|
||||
DEV9_LOG_VERB("IF_CTRL DMA Is ATA Write\n");
|
||||
|
||||
if (value & SPD_IF_ATA_DMAEN)
|
||||
{
|
||||
DEV9_LOG_VERB("IF_CTRL ATA DMA Enabled\n");
|
||||
if (value & SPD_IF_READ) //Semi async
|
||||
{
|
||||
HDDWriteFIFO(); //Yes this is not a typo
|
||||
}
|
||||
else
|
||||
{
|
||||
HDDReadFIFO();
|
||||
}
|
||||
FIFOIntr();
|
||||
}
|
||||
else
|
||||
DEV9_LOG_VERB("IF_CTRL ATA DMA Disabled\n");
|
||||
|
||||
if (value & (1 << 3))
|
||||
DEV9_LOG_VERB("IF_CTRL Unkown Bit 3 Set\n");
|
||||
|
||||
if (value & (1 << 4))
|
||||
DEV9_LOG_ERROR("IF_CTRL Unkown Bit 4 Set\n");
|
||||
if (value & (1 << 5))
|
||||
DEV9_LOG_ERROR("IF_CTRL Unkown Bit 5 Set\n");
|
||||
|
||||
if ((value & SPD_IF_HDD_RESET) == 0) //Maybe?
|
||||
{
|
||||
DEV9_LOG_INFO("IF_CTRL HDD Hard Reset\n");
|
||||
dev9.ata->ATA_HardReset();
|
||||
}
|
||||
if ((value & SPD_IF_ATA_RESET) != 0)
|
||||
{
|
||||
DEV9_LOG_INFO("IF_CTRL ATA Reset\n");
|
||||
//0x62 0x0020
|
||||
dev9.if_ctrl = 0x001A;
|
||||
//0x66 0x0001
|
||||
dev9.pio_mode = 0x24;
|
||||
dev9.mdma_mode = 0x45;
|
||||
dev9.udma_mode = 0x83;
|
||||
//0x76 0x4ABA (And consequently 0x78 = 0x4ABA.)
|
||||
}
|
||||
|
||||
if ((value & 0xFF00) > 0)
|
||||
DEV9_LOG_ERROR("IF_CTRL Unkown Bit(s) %x\n", (value & 0xFF00));
|
||||
|
||||
break;
|
||||
case SPD_R_PIO_MODE: //ATA only? or includes EEPROM?
|
||||
DEV9_LOG_VERB("SPD_R_PIO_MODE 16bit write %x\n", value);
|
||||
dev9.pio_mode = value;
|
||||
|
||||
switch (value)
|
||||
{
|
||||
case 0x92:
|
||||
DEV9_LOG_INFO("SPD_R_PIO_MODE 0\n");
|
||||
break;
|
||||
case 0x72:
|
||||
DEV9_LOG_INFO("SPD_R_PIO_MODE 1\n");
|
||||
break;
|
||||
case 0x32:
|
||||
DEV9_LOG_INFO("SPD_R_PIO_MODE 2\v");
|
||||
break;
|
||||
case 0x24:
|
||||
DEV9_LOG_INFO("SPD_R_PIO_MODE 3\n");
|
||||
break;
|
||||
case 0x23:
|
||||
DEV9_LOG_INFO("SPD_R_PIO_MODE 4\n");
|
||||
break;
|
||||
|
||||
default:
|
||||
DEV9_LOG_ERROR("SPD_R_PIO_MODE UNKOWN MODE %x\n", value);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case SPD_R_MDMA_MODE: //ATA only? or includes EEPROM?
|
||||
DEV9_LOG_VERB("SPD_R_MDMA_MODE 16bit write %x\n", value);
|
||||
dev9.mdma_mode = value;
|
||||
|
||||
if ((addr >= FLASH_REGBASE) && (addr < (FLASH_REGBASE + FLASH_REGSIZE)))
|
||||
switch (value)
|
||||
{
|
||||
FLASHwrite32(addr, (u32)value, 2);
|
||||
return;
|
||||
case 0xFF:
|
||||
DEV9_LOG_INFO("SPD_R_MDMA_MODE 0\n");
|
||||
break;
|
||||
case 0x45:
|
||||
DEV9_LOG_INFO("SPD_R_MDMA_MODE 1\n");
|
||||
break;
|
||||
case 0x24:
|
||||
DEV9_LOG_INFO("SPD_R_MDMA_MODE 2\n");
|
||||
break;
|
||||
default:
|
||||
DEV9_LOG_ERROR("SPD_R_MDMA_MODE UNKOWN MODE %x\n", value);
|
||||
break;
|
||||
}
|
||||
|
||||
break;
|
||||
case SPD_R_UDMA_MODE: //ATA only?
|
||||
DEV9_LOG_VERB("SPD_R_UDMA_MODE 16bit write %x\n", value);
|
||||
dev9.udma_mode = value;
|
||||
|
||||
switch (value)
|
||||
{
|
||||
case 0xa7:
|
||||
DEV9_LOG_VERB("SPD_R_UDMA_MODE 0\n");
|
||||
break;
|
||||
case 0x85:
|
||||
DEV9_LOG_VERB("SPD_R_UDMA_MODE 1\n");
|
||||
break;
|
||||
case 0x63:
|
||||
DEV9_LOG_VERB("SPD_R_UDMA_MODE 2\n");
|
||||
break;
|
||||
case 0x62:
|
||||
DEV9_LOG_VERB("SPD_R_UDMA_MODE 3\n");
|
||||
break;
|
||||
case 0x61:
|
||||
DEV9_LOG_VERB("SPD_R_UDMA_MODE 4\n");
|
||||
break;
|
||||
default:
|
||||
DEV9_LOG_ERROR("SPD_R_UDMA_MODE UNKOWN MODE %x\n", value);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
dev9Ru16(addr) = value;
|
||||
DEV9_LOG("*Unknown 16bit write at address %lx value %x\n", addr, value);
|
||||
DEV9_LOG_ERROR("*Unknown 16bit write at address %lx value %x\n", addr, value);
|
||||
return;
|
||||
}
|
||||
dev9Ru16(addr) = value;
|
||||
DEV9_LOG("*Known 16bit write at address %lx value %x\n", addr, value);
|
||||
}
|
||||
|
||||
void DEV9write32(u32 addr, u32 value)
|
||||
|
|
@ -747,24 +1043,22 @@ void DEV9write32(u32 addr, u32 value)
|
|||
smap_write32(addr, value);
|
||||
return;
|
||||
}
|
||||
switch (addr)
|
||||
{
|
||||
case SPD_R_INTR_MASK:
|
||||
emu_printf("SPD_R_INTR_MASK , WTFH ?\n");
|
||||
break;
|
||||
default:
|
||||
if ((addr >= FLASH_REGBASE) && (addr < (FLASH_REGBASE + FLASH_REGSIZE)))
|
||||
{
|
||||
FLASHwrite32(addr, (u32)value, 4);
|
||||
return;
|
||||
}
|
||||
|
||||
switch (addr)
|
||||
{
|
||||
case SPD_R_INTR_MASK:
|
||||
DEV9_LOG_ERROR("SPD_R_INTR_MASK , WTFH ?\n");
|
||||
break;
|
||||
default:
|
||||
dev9Ru32(addr) = value;
|
||||
DEV9_LOG("*Unknown 32bit write at address %lx write %x\n", addr, value);
|
||||
DEV9_LOG_ERROR("*Unknown 32bit write at address %lx write %x\n", addr, value);
|
||||
return;
|
||||
}
|
||||
dev9Ru32(addr) = value;
|
||||
DEV9_LOG("*Known 32bit write at address %lx value %lx\n", addr, value);
|
||||
}
|
||||
|
||||
void DEV9readDMA8Mem(u32* pMem, int size)
|
||||
|
|
@ -772,14 +1066,26 @@ void DEV9readDMA8Mem(u32* pMem, int size)
|
|||
if (!config.ethEnable & !config.hddEnable)
|
||||
return;
|
||||
|
||||
DEV9_LOG("*DEV9readDMA8Mem: size %x\n", size);
|
||||
emu_printf("rDMA\n");
|
||||
size >>= 1;
|
||||
|
||||
DEV9_LOG_VERB("*DEV9readDMA8Mem: size %x\n", size);
|
||||
DEV9_LOG_INFO("rDMA\n");
|
||||
|
||||
if (dev9.dma_ctrl & SPD_DMA_TO_SMAP)
|
||||
smap_readDMA8Mem(pMem, size);
|
||||
#ifdef ENABLE_ATA
|
||||
ata_readDMA8Mem(pMem, size);
|
||||
#endif
|
||||
else
|
||||
{
|
||||
if (dev9.xfr_ctrl & SPD_XFR_DMAEN &&
|
||||
!(dev9.xfr_ctrl & SPD_XFR_WRITE))
|
||||
{
|
||||
HDDWriteFIFO();
|
||||
IOPReadFIFO(size);
|
||||
dev9.ata->ATAreadDMA8Mem((u8*)pMem, size);
|
||||
FIFOIntr();
|
||||
}
|
||||
}
|
||||
|
||||
//TODO, track if read was successful
|
||||
}
|
||||
|
||||
void DEV9writeDMA8Mem(u32* pMem, int size)
|
||||
|
|
@ -787,20 +1093,32 @@ void DEV9writeDMA8Mem(u32* pMem, int size)
|
|||
if (!config.ethEnable & !config.hddEnable)
|
||||
return;
|
||||
|
||||
DEV9_LOG("*DEV9writeDMA8Mem: size %x\n", size);
|
||||
emu_printf("wDMA\n");
|
||||
size >>= 1;
|
||||
|
||||
smap_writeDMA8Mem(pMem, size);
|
||||
#ifdef ENABLE_ATA
|
||||
ata_writeDMA8Mem(pMem, size);
|
||||
#endif
|
||||
}
|
||||
DEV9_LOG_VERB("*DEV9writeDMA8Mem: size %x\n", size);
|
||||
DEV9_LOG_INFO("wDMA\n");
|
||||
|
||||
if (dev9.dma_ctrl & SPD_DMA_TO_SMAP)
|
||||
smap_writeDMA8Mem(pMem, size);
|
||||
else
|
||||
{
|
||||
if (dev9.xfr_ctrl & SPD_XFR_DMAEN &&
|
||||
dev9.xfr_ctrl & SPD_XFR_WRITE)
|
||||
{
|
||||
IOPWriteFIFO(size);
|
||||
HDDReadFIFO();
|
||||
dev9.ata->ATAwriteDMA8Mem((u8*)pMem, size);
|
||||
FIFOIntr();
|
||||
}
|
||||
}
|
||||
|
||||
//TODO, track if write was successful
|
||||
}
|
||||
|
||||
void DEV9async(u32 cycles)
|
||||
{
|
||||
smap_async(cycles);
|
||||
dev9.ata->Async(cycles);
|
||||
}
|
||||
|
||||
// extended funcs
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
#include "PS2Edefs.h"
|
||||
#include "PS2Eext.h"
|
||||
#include "net.h"
|
||||
#include "ATA/ATA.h"
|
||||
|
||||
#ifdef _WIN32
|
||||
|
||||
|
|
@ -82,6 +83,8 @@ EXTERN Config config;
|
|||
|
||||
typedef struct
|
||||
{
|
||||
ATA* ata;
|
||||
|
||||
s8 dev9R[0x10000];
|
||||
u8 eeprom_state;
|
||||
u8 eeprom_command;
|
||||
|
|
@ -99,14 +102,21 @@ typedef struct
|
|||
u16 txfifo_rd_ptr;
|
||||
|
||||
u8 bd_swap;
|
||||
u16 atabuf[1024];
|
||||
u32 atacount;
|
||||
u32 atasize;
|
||||
u16 phyregs[32];
|
||||
int irqcause;
|
||||
u8 atacmd;
|
||||
u32 atasector;
|
||||
u32 atansector;
|
||||
|
||||
u16 irqcause;
|
||||
u16 irqmask;
|
||||
u16 dma_ctrl;
|
||||
u16 xfr_ctrl;
|
||||
u16 if_ctrl;
|
||||
|
||||
u16 pio_mode;
|
||||
u16 mdma_mode;
|
||||
u16 udma_mode;
|
||||
|
||||
//Non-Regs
|
||||
int fifo_bytes_read;
|
||||
int fifo_bytes_write;
|
||||
} dev9Struct;
|
||||
|
||||
//EEPROM states
|
||||
|
|
|
|||
Loading…
Reference in New Issue