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work in progress stuff... 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@797 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes 2009-03-16 08:19:46 +00:00
parent 80abd88a67
commit 2fa30cabf4
8 changed files with 145 additions and 55 deletions
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6
pcsx2/x86/microVU.cpp
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@ -86,7 +86,7 @@ microVUt(void) mVUreset() {
// Create Block Managers
for (int i; i <= mVU->prog.max; i++) {
for (u32 j; j < mVU->progSize; j++) {
for (u32 j; j < (mVU->progSize / 2); j++) {
mVU->prog.prog[i].block[j] = new microBlockManager();
}
}
@ -112,7 +112,7 @@ microVUt(void) mVUclose() {
// Delete Block Managers
for (int i; i <= mVU->prog.max; i++) {
for (u32 j; j < mVU->progSize; j++) {
for (u32 j; j < (mVU->progSize / 2); j++) {
if (mVU->prog.prog[i].block[j]) delete mVU->prog.prog[i].block[j];
}
}
@ -163,7 +163,7 @@ void* __fastcall mVUexecuteVU1(u32 startPC, u32 cycles) {
// Clears program data (Sets used to 1 because calling this function implies the program will be used at least once)
__forceinline void mVUclearProg(microVU* mVU, int progIndex) {
mVU->prog.prog[progIndex].used = 1;
for (u32 i = 0; i < mVU->progSize; i++) {
for (u32 i = 0; i < (mVU->progSize / 2); i++) {
mVU->prog.prog[progIndex].block[i]->reset();
}
}

7
pcsx2/x86/microVU.h
View File

@ -82,9 +82,9 @@ public:
template<u32 progSize>
struct microProgram {
u8 data[progSize];
u32 data[progSize];
u32 used; // Number of times its been used
microBlockManager* block[progSize];
microBlockManager* block[progSize / 2];
microAllocInfo<progSize> allocInfo;
};
@ -107,7 +107,7 @@ struct microVU {
u32 cacheAddr; // VU Cache Start Address
static const u32 cacheSize = 0x500000; // VU Cache Size
microProgManager<0x800> prog; // Micro Program Data
microProgManager<0x1000> prog; // Micro Program Data
VURegs* regs; // VU Regs Struct
u8* cache; // Dynarec Cache Start (where we will start writing the recompiled code to)
@ -149,3 +149,4 @@ microVUt(void) mVUclose();
#include "microVU_Misc.h"
#include "microVU_Alloc.inl"
#include "microVU_Tables.inl"
#include "microVU_Compile.inl"

21
pcsx2/x86/microVU_Alloc.h
View File

@ -28,8 +28,7 @@ union regInfo {
};
};
template<u32 pSize>
struct microAllocInfo {
struct microRegInfo {
regInfo VF[32];
regInfo Acc;
u8 VI[32];
@ -37,11 +36,19 @@ struct microAllocInfo {
u8 q;
u8 p;
u8 r;
};
template<u32 pSize>
struct microAllocInfo {
microRegInfo regs;
u8 branch; // 0 = No Branch, 1 = Branch, 2 = Conditional Branch, 3 = Jump (JALR/JR)
u32 curPC; // Current PC
u32 cycles; // Cycles for current block
u32 info[pSize];// bit 00 = Lower Instruction is NOP
// bit 01 = Used with bit 2 to make a 2-bit key for ACC write instance
// bit 02 = (00 = instance #0, 01 = instance #1, 10 = instance #2, 11 = instance #3)
// bit 03 = Used with bit 4 to make a 2-bit key for ACC read instance
// bit 04 = (00 = instance #0, 01 = instance #1, 10 = instance #2, 11 = instance #3)
// bit 01
// bit 02
// bit 03
// bit 04
// bit 05 = Write to Q1 or Q2?
// bit 06 = Read Q1 or Q2?
// bit 07 = Read/Write to P1 or P2?
@ -59,6 +66,4 @@ struct microAllocInfo {
// bit 19
// bit 20 = Read VI(Fs) from backup memory?
// bit 21 = Read VI(Ft) from backup memory?
u32 curPC;
};

34
pcsx2/x86/microVU_Compile.inl
View File

@ -19,4 +19,36 @@
#pragma once
#ifdef PCSX2_MICROVU
#endif //PCSX2_MICROVU
#define mVUbranch mVUallocInfo.branch
#define iPC mVUcurProg.curPC
#define curI mVUcurProg.data[iPC]
#define setCode() { mVU->code = curI; }
#define incPC() { iPC = ((iPC + 1) & (mVU->progSize-1)); setCode();}
microVUx(void) mVUcompile(u32 startPC, u32 pipelineState, u8* x86ptrStart) {
microVU* mVU = mVUx;
int x;
iPC = startPC;
setCode();
for (x = 0; ; x++) {
if (curI & _Ibit_) { SysPrintf("microVU: I-bit set!\n"); }
if (curI & _Ebit_) { SysPrintf("microVU: E-bit set!\n"); }
if (curI & _Mbit_) { SysPrintf("microVU: M-bit set!\n"); }
if (curI & _Dbit_) { SysPrintf("microVU: D-bit set!\n"); mVUbranch = 4; }
if (curI & _Tbit_) { SysPrintf("microVU: T-bit set!\n"); mVUbranch = 4; }
mVUopU<vuIndex, 0>();
incPC();
mVUopL<vuIndex, 0>();
if (mVUbranch == 4) { mVUbranch = 0; break; }
else if (mVUbranch) { mVUbranch = 4; }
}
iPC = startPC;
setCode();
for (int i = 0; i < x; i++) {
mVUopU<vuIndex, 1>();
incPC();
if (!isNop) mVUopL<vuIndex, 1>();
}
}
#endif //PCSX2_MICROVU

67
pcsx2/x86/microVU_Lower.inl
View File

@ -594,17 +594,6 @@ microVUf(void) mVU_ISUBIU() {
}
}
microVUf(void) mVU_B() {}
microVUf(void) mVU_BAL() {}
microVUf(void) mVU_IBEQ() {}
microVUf(void) mVU_IBGEZ() {}
microVUf(void) mVU_IBGTZ() {}
microVUf(void) mVU_IBLTZ() {}
microVUf(void) mVU_IBLEZ() {}
microVUf(void) mVU_IBNE() {}
microVUf(void) mVU_JR() {}
microVUf(void) mVU_JALR() {}
microVUf(void) mVU_MOVE() {
microVU* mVU = mVUx;
if (recPass == 0) { /*If (!_Ft_ || (_Ft_ == _Fs_)) nop();*/ }
@ -952,4 +941,60 @@ microVUf(void) mVU_XGKICK() {
else CALLFunc((uptr)mVU_XGKICK1);
}
}
//------------------------------------------------------------------
// Branches
//------------------------------------------------------------------
microVUf(void) mVU_B() {
microVU* mVU = mVUx;
if (recPass == 0) { mVUallocInfo.branch = 1; }
else {}
}
microVUf(void) mVU_BAL() {
microVU* mVU = mVUx;
if (recPass == 0) { mVUallocInfo.branch = 1; }
else {}
}
microVUf(void) mVU_IBEQ() {
microVU* mVU = mVUx;
if (recPass == 0) { mVUallocInfo.branch = 2; }
else {}
}
microVUf(void) mVU_IBGEZ() {
microVU* mVU = mVUx;
if (recPass == 0) { mVUallocInfo.branch = 2; }
else {}
}
microVUf(void) mVU_IBGTZ() {
microVU* mVU = mVUx;
if (recPass == 0) { mVUallocInfo.branch = 2; }
else {}
}
microVUf(void) mVU_IBLTZ() {
microVU* mVU = mVUx;
if (recPass == 0) { mVUallocInfo.branch = 2; }
else {}
}
microVUf(void) mVU_IBLEZ() {
microVU* mVU = mVUx;
if (recPass == 0) { mVUallocInfo.branch = 2; }
else {}
}
microVUf(void) mVU_IBNE() {
microVU* mVU = mVUx;
if (recPass == 0) { mVUallocInfo.branch = 2; }
else {}
}
microVUf(void) mVU_JR() {
microVU* mVU = mVUx;
if (recPass == 0) { mVUallocInfo.branch = 3; }
else {}
}
microVUf(void) mVU_JALR() {
microVU* mVU = mVUx;
if (recPass == 0) { mVUallocInfo.branch = 3; }
else {}
}
#endif //PCSX2_MICROVU

46
pcsx2/x86/microVU_Misc.h
View File

@ -59,15 +59,14 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]);
#define _Fs_ ((mVU->code >> 11) & 0x1F) // The rd part of the instruction register
#define _Fd_ ((mVU->code >> 6) & 0x1F) // The sa part of the instruction register
#define _X ((mVU->code>>24) & 0x1)
#define _Y ((mVU->code>>23) & 0x1)
#define _Z ((mVU->code>>22) & 0x1)
#define _W ((mVU->code>>21) & 0x1)
#define _X ((mVU->code>>24) & 0x1)
#define _Y ((mVU->code>>23) & 0x1)
#define _Z ((mVU->code>>22) & 0x1)
#define _W ((mVU->code>>21) & 0x1)
#define _XYZW_SS (_X+_Y+_Z+_W==1)
#define _X_Y_Z_W (((mVU->code >> 21 ) & 0xF ))
#define _xyzw_ACC ((_XYZW_SS && !_X) ? 15 : _X_Y_Z_W)
#define _XYZW_SS (_X+_Y+_Z+_W==1)
#define _X_Y_Z_W (((mVU->code >> 21 ) & 0xF ))
#define _xyzw_ACC ((_XYZW_SS && !_X) ? 15 : _X_Y_Z_W)
#define _bc_ (mVU->code & 0x03)
#define _bc_x ((mVU->code & 0x03) == 0)
@ -78,12 +77,17 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]);
#define _Fsf_ ((mVU->code >> 21) & 0x03)
#define _Ftf_ ((mVU->code >> 23) & 0x03)
#define _Imm11_ (s32)(mVU->code & 0x400 ? 0xfffffc00 | (mVU->code & 0x3ff) : mVU->code & 0x3ff)
#define _UImm11_ (s32)(mVU->code & 0x7ff)
#define _Imm12_ (((mVU->code >> 21 ) & 0x1) << 11) | (mVU->code & 0x7ff)
#define _Imm5_ (((mVU->code & 0x400) ? 0xfff0 : 0) | ((mVU->code >> 6) & 0xf))
#define _Imm15_ (((mVU->code >> 10) & 0x7800) | (mVU->code & 0x7ff))
#define _Imm24_ (u32)(mVU->code & 0xffffff)
#define _Imm5_ (((mVU->code & 0x400) ? 0xfff0 : 0) | ((mVU->code >> 6) & 0xf))
#define _Imm11_ (s32)(mVU->code & 0x400 ? 0xfffffc00 | (mVU->code & 0x3ff) : mVU->code & 0x3ff)
#define _Imm12_ (((mVU->code >> 21 ) & 0x1) << 11) | (mVU->code & 0x7ff)
#define _Imm15_ (((mVU->code >> 10) & 0x7800) | (mVU->code & 0x7ff))
#define _Imm24_ (u32)(mVU->code & 0xffffff)
#define _Ibit_ (1<<31)
#define _Ebit_ (1<<30)
#define _Mbit_ (1<<29)
#define _Dbit_ (1<<28)
#define _Tbit_ (1<<27)
#define getVUmem(x) (((vuIndex == 1) ? (x & 0x3ff) : ((x >= 0x400) ? (x & 0x43f) : (x & 0xff))) * 16)
#define offsetSS ((_X) ? (0) : ((_Y) ? (4) : ((_Z) ? 8: 12)))
@ -92,9 +96,9 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]);
#define xmmFs 1 // Holds the Value of Fs (writes back result Fd)
#define xmmFt 2 // Holds the Value of Ft
#define xmmACC 3 // Holds ACC
#define xmmT2 4 // Temp Reg?
#define xmmT3 5 // Temp Reg?
#define xmmT4 6 // Temp Reg?
#define xmmMax 4 // Holds mVU_maxvals
#define xmmMin 5 // Holds mVU_minvals
#define xmmT2 6 // Temp Reg?
#define xmmPQ 7 // Holds the Value and Backup Values of P and Q regs
#define mmxVI1 0 // Holds VI 1
@ -122,12 +126,13 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]);
#define microVUf(aType) template<int vuIndex, int recPass> aType
#define microVUq(aType) template<int vuIndex, int recPass> __forceinline aType
#define mVUcurProg mVU->prog.prog[mVU->prog.cur]
#define mVUallocInfo mVU->prog.prog[mVU->prog.cur].allocInfo
#define isNOP (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<0))
#define writeACC ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<1)) >> 1)
#define prevACC (((u8)((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<1)) >> 1) - 1) & 0x3)
#define readACC ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<3)) >> 3)
//#define writeACC ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<1)) >> 1)
//#define prevACC (((u8)((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<1)) >> 1) - 1) & 0x3)
//#define readACC ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<3)) >> 3)
#define writeQ ((mVUallocInfo.info[mVUallocInfo.curPC] & (1<<5)) >> 5)
#define readQ ((mVUallocInfo.info[mVUallocInfo.curPC] & (1<<6)) >> 6)
#define writeP ((mVUallocInfo.info[mVUallocInfo.curPC] & (1<<7)) >> 7)
@ -143,7 +148,6 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]);
#define fvmInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<16)) >> 16)
#define fvsInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<18)) >> 18)
#define fvcInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<14)) >> 14)
//#define getFs (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<13))
//#define getFt (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<14))

16
pcsx2/x86/microVU_Misc.inl
View File

@ -27,12 +27,12 @@
microVUx(void) mVUclamp1(int reg, int regT1, int xyzw) {
switch (xyzw) {
case 1: case 2: case 4: case 8:
SSE_MINSS_M32_to_XMM(reg, (uptr)mVU_maxvals);
SSE_MAXSS_M32_to_XMM(reg, (uptr)mVU_minvals);
SSE_MINSS_XMM_to_XMM(reg, xmmMax);
SSE_MAXSS_XMM_to_XMM(reg, xmmMin);
break;
default:
SSE_MINPS_M128_to_XMM(reg, (uptr)mVU_maxvals);
SSE_MAXPS_M128_to_XMM(reg, (uptr)mVU_minvals);
SSE_MINPS_XMM_to_XMM(reg, xmmMax);
SSE_MAXPS_XMM_to_XMM(reg, xmmMin);
break;
}
}
@ -44,15 +44,15 @@ microVUx(void) mVUclamp2(int reg, int regT1, int xyzw) {
case 1: case 2: case 4: case 8:
SSE_MOVSS_XMM_to_XMM(regT1, reg);
SSE_ANDPS_M128_to_XMM(regT1, (uptr)mVU_signbit);
SSE_MINSS_M32_to_XMM(reg, (uptr)mVU_maxvals);
SSE_MAXSS_M32_to_XMM(reg, (uptr)mVU_minvals);
SSE_MINSS_XMM_to_XMM(reg, xmmMax);
SSE_MAXSS_XMM_to_XMM(reg, xmmMin);
SSE_ORPS_XMM_to_XMM(reg, regT1);
break;
default:
SSE_MOVAPS_XMM_to_XMM(regT1, reg);
SSE_ANDPS_M128_to_XMM(regT1, (uptr)mVU_signbit);
SSE_MINPS_M128_to_XMM(reg, (uptr)mVU_maxvals);
SSE_MAXPS_M128_to_XMM(reg, (uptr)mVU_minvals);
SSE_MINPS_XMM_to_XMM(reg, xmmMax);
SSE_MAXPS_XMM_to_XMM(reg, xmmMin);
SSE_ORPS_XMM_to_XMM(reg, regT1);
break;
}

3
pcsx2/x86/microVU_Tables.inl
View File

@ -750,4 +750,7 @@ microVUf(void) mVULowerOP_T3_01() { doTableStuff(mVULowerOP_T3_01_OPCODE, ((mVUg
microVUf(void) mVULowerOP_T3_10() { doTableStuff(mVULowerOP_T3_10_OPCODE, ((mVUgetCode >> 6) & 0x1f)); }
microVUf(void) mVULowerOP_T3_11() { doTableStuff(mVULowerOP_T3_11_OPCODE, ((mVUgetCode >> 6) & 0x1f)); }
microVUf(void) mVUunknown() { SysPrintf("mVUunknown<%d,%d> : Unknown Micro VU opcode called\n", vuIndex, recPass); }
microVUf(void) mVUopU() { doTableStuff(mVU_UPPER_OPCODE, (mVUgetCode & 0x3f)); } // Gets Upper Opcode
microVUf(void) mVUopL() { doTableStuff(mVULOWER_OPCODE, (mVUgetCode >> 25)); } // Gets Lower Opcode
#endif //PCSX2_MICROVU