mirror of https://github.com/PCSX2/pcsx2.git
Clean up some nasty #ifdefs in a few functions, which involved somewhat of a rewrite of those particular functions.
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@343 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
arcum42
Gregory Hainaut
parent
a56b32fe18
commit
2f08ff5e70
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@ -20,7 +20,7 @@
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# Uncomment if building by itself, rather then with all the plugins
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#Normal
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#export PCSX2OPTIONS="--enable-sse3 --prefix `pwd`"
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export PCSX2OPTIONS="--enable-sse3 --prefix `pwd`"
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#Debug version
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#export PCSX2OPTIONS="--enable-debug --enable-devbuild --enable-sse3 --prefix `pwd`"
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330
pcsx2/x86/iFPU.c
330
pcsx2/x86/iFPU.c
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@ -24,8 +24,10 @@
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#include "ix86/ix86.h"
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#include "iR5900.h"
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#include "iFPU.h"
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#include "stdio.h" //Linux needs this?
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#include "stdlib.h" //Linux needs this?
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// Needed for gcc 4.3, due to header revisions.
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#include "stdio.h"
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#include "stdlib.h"
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//------------------------------------------------------------------
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@ -159,36 +161,57 @@ void recCTC1( void )
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{
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if ( _Fs_ != 31 ) return;
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if ( GPR_IS_CONST1(_Rt_) ) {
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if ( GPR_IS_CONST1(_Rt_) )
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{
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MOV32ItoM((uptr)&fpuRegs.fprc[ _Fs_ ], g_cpuConstRegs[_Rt_].UL[0]);
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}
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else {
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else
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{
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int mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_READ);
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if( mmreg >= 0 ) {
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if( mmreg >= 0 )
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{
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SSEX_MOVD_XMM_to_M32((uptr)&fpuRegs.fprc[ _Fs_ ], mmreg);
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}
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#ifdef __x86_64__
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else if ( (mmreg = _checkX86reg(X86TYPE_GPR, _Rt_, MODE_READ) ) >= 0 ) {
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else
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{
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mmreg = _checkX86reg(X86TYPE_GPR, _Rt_, MODE_READ);
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if ( mmreg >= 0 )
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{
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MOV32RtoM((uptr)&fpuRegs.fprc[ _Fs_ ], mmreg);
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}
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#else
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else if ( (mmreg = _checkMMXreg(MMX_GPR+_Rt_, MODE_READ)) >= 0 ) {
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MOVDMMXtoM((uptr)&fpuRegs.fprc[ _Fs_ ], mmreg);
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SetMMXstate();
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}
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#endif
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else {
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else
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{
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_deleteGPRtoXMMreg(_Rt_, 1);
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#ifdef __x86_64__
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_deleteX86reg(X86TYPE_GPR, _Rt_, 1);
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#else
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_deleteMMXreg(MMX_GPR+_Rt_, 1);
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#endif
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MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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MOV32RtoM( (uptr)&fpuRegs.fprc[ _Fs_ ], EAX );
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}
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}
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#else
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else
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{
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mmreg = _checkMMXreg(MMX_GPR+_Rt_, MODE_READ);
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if ( mmreg >= 0 )
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{
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MOVDMMXtoM((uptr)&fpuRegs.fprc[ _Fs_ ], mmreg);
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SetMMXstate();
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}
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else
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{
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_deleteGPRtoXMMreg(_Rt_, 1);
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_deleteMMXreg(MMX_GPR+_Rt_, 1);
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MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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MOV32RtoM( (uptr)&fpuRegs.fprc[ _Fs_ ], EAX );
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}
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}
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#endif
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}
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}
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//------------------------------------------------------------------
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@ -196,106 +219,179 @@ void recCTC1( void )
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//------------------------------------------------------------------
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// MFC1
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//------------------------------------------------------------------
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void recMFC1(void) {
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#ifdef __x86_64__
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void recMFC1(void)
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{
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int regt, regs;
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if ( ! _Rt_ ) return;
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_eeOnWriteReg(_Rt_, 1);
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regs = _checkXMMreg(XMMTYPE_FPREG, _Fs_, MODE_READ);
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if( regs >= 0 ) {
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_deleteGPRtoXMMreg(_Rt_, 2);
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#ifdef __x86_64__
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if( regs >= 0 )
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{
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_deleteGPRtoXMMreg(_Rt_, 2);
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regt = _allocCheckGPRtoX86(g_pCurInstInfo, _Rt_, MODE_WRITE);
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if( regt >= 0 ) {
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if(EEINST_ISLIVE1(_Rt_)) {
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if( regt >= 0 )
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{
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if(EEINST_ISLIVE1(_Rt_))
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{
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SSE2_MOVD_XMM_to_R(RAX, regs);
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// sign extend
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CDQE();
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MOV64RtoR(regt, RAX);
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}
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else {
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else
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{
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SSE2_MOVD_XMM_to_R(regt, regs);
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EEINST_RESETHASLIVE1(_Rt_);
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}
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}
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#else
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regt = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rt_, MODE_WRITE);
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if( regt >= 0 ) {
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SSE2_MOVDQ2Q_XMM_to_MM(regt, regs);
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if(EEINST_ISLIVE1(_Rt_)) _signExtendGPRtoMMX(regt, _Rt_, 0);
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else EEINST_RESETHASLIVE1(_Rt_);
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}
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#endif
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else {
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if(EEINST_ISLIVE1(_Rt_)) {
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else
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{
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if(EEINST_ISLIVE1(_Rt_))
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{
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_signExtendXMMtoM((uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], regs, 0);
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}
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else {
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else
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{
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EEINST_RESETHASLIVE1(_Rt_);
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SSE_MOVSS_XMM_to_M32((uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], regs);
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}
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}
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}
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#ifndef __x86_64__
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else if( (regs = _checkMMXreg(MMX_FPU+_Fs_, MODE_READ)) >= 0 ) {
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// convert to mmx reg
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mmxregs[regs].reg = MMX_GPR+_Rt_;
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mmxregs[regs].mode |= MODE_READ|MODE_WRITE;
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_signExtendGPRtoMMX(regs, _Rt_, 0);
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}
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#endif
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else {
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regt = _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_READ);
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else
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{
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regs = _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_READ);
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if( regt >= 0 ) {
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if( xmmregs[regt].mode & MODE_WRITE ) {
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SSE_MOVHPS_XMM_to_M64((uptr)&cpuRegs.GPR.r[_Rt_].UL[2], regt);
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if( regs >= 0 )
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{
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if( xmmregs[regs].mode & MODE_WRITE )
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{
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SSE_MOVHPS_XMM_to_M64((uptr)&cpuRegs.GPR.r[_Rt_].UL[2], regs);
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}
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xmmregs[regt].inuse = 0;
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xmmregs[regs].inuse = 0;
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}
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#ifdef __x86_64__
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else if( (regt = _allocCheckGPRtoX86(g_pCurInstInfo, _Rt_, MODE_WRITE)) >= 0 ) {
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else
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{
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regt = _allocCheckGPRtoX86(g_pCurInstInfo, _Rt_, MODE_WRITE);
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if(EEINST_ISLIVE1(_Rt_)) {
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if( regt >= 0 )
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{
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if(EEINST_ISLIVE1(_Rt_))
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{
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MOV32MtoR( RAX, (uptr)&fpuRegs.fpr[ _Fs_ ].UL );
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CDQE();
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MOV64RtoR(regt, RAX);
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}
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else {
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else
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{
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MOV32MtoR( regt, (uptr)&fpuRegs.fpr[ _Fs_ ].UL );
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EEINST_RESETHASLIVE1(_Rt_);
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}
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}
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else
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#endif
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{
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_deleteEEreg(_Rt_, 0);
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MOV32MtoR( EAX, (uptr)&fpuRegs.fpr[ _Fs_ ].UL );
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if(EEINST_ISLIVE1(_Rt_)) {
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#ifdef __x86_64__
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if(EEINST_ISLIVE1(_Rt_))
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{
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CDQE();
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MOV64RtoM((uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], RAX);
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#else
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CDQ( );
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MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
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#endif
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}
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else {
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else
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{
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EEINST_RESETHASLIVE1(_Rt_);
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MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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}
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}
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}
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}
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}
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#else
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void recMFC1(void)
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{
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int regt, regs;
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if ( ! _Rt_ ) return;
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_eeOnWriteReg(_Rt_, 1);
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regs = _checkXMMreg(XMMTYPE_FPREG, _Fs_, MODE_READ);
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if( regs >= 0 )
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{
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_deleteGPRtoXMMreg(_Rt_, 2);
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regt = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rt_, MODE_WRITE);
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if( regt >= 0 )
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{
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SSE2_MOVDQ2Q_XMM_to_MM(regt, regs);
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if(EEINST_ISLIVE1(_Rt_))
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_signExtendGPRtoMMX(regt, _Rt_, 0);
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else
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EEINST_RESETHASLIVE1(_Rt_);
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}
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else
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{
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if(EEINST_ISLIVE1(_Rt_))
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{
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_signExtendXMMtoM((uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], regs, 0);
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}
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else
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{
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EEINST_RESETHASLIVE1(_Rt_);
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SSE_MOVSS_XMM_to_M32((uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], regs);
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}
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}
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}
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else
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{
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regs = _checkMMXreg(MMX_FPU+_Fs_, MODE_READ);
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if( regs >= 0 )
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{
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// convert to mmx reg
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mmxregs[regs].reg = MMX_GPR+_Rt_;
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mmxregs[regs].mode |= MODE_READ|MODE_WRITE;
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_signExtendGPRtoMMX(regs, _Rt_, 0);
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}
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else
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{
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regt = _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_READ);
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if( regt >= 0 )
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{
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if( xmmregs[regt].mode & MODE_WRITE )
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{
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SSE_MOVHPS_XMM_to_M64((uptr)&cpuRegs.GPR.r[_Rt_].UL[2], regt);
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}
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xmmregs[regt].inuse = 0;
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}
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_deleteEEreg(_Rt_, 0);
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MOV32MtoR( EAX, (uptr)&fpuRegs.fpr[ _Fs_ ].UL );
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if(EEINST_ISLIVE1(_Rt_))
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{
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CDQ( );
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MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
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}
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else
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{
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EEINST_RESETHASLIVE1(_Rt_);
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MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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}
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}
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}
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}
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#endif
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//------------------------------------------------------------------
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@ -304,49 +400,83 @@ void recMFC1(void) {
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//------------------------------------------------------------------
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void recMTC1(void)
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{
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if( GPR_IS_CONST1(_Rt_) ) {
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if( GPR_IS_CONST1(_Rt_) )
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{
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_deleteFPtoXMMreg(_Fs_, 0);
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MOV32ItoM((uptr)&fpuRegs.fpr[ _Fs_ ].UL, g_cpuConstRegs[_Rt_].UL[0]);
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}
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else {
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else
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{
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int mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_READ);
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if( mmreg >= 0 ) {
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if( g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE ) {
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if( mmreg >= 0 )
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{
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if( g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE )
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{
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// transfer the reg directly
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_deleteGPRtoXMMreg(_Rt_, 2);
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_deleteFPtoXMMreg(_Fs_, 2);
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_allocFPtoXMMreg(mmreg, _Fs_, MODE_WRITE);
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}
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else {
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int mmreg2 = _allocCheckFPUtoXMM(g_pCurInstInfo, _Fs_, MODE_WRITE);
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if( mmreg2 >= 0 ) SSE_MOVSS_XMM_to_XMM(mmreg2, mmreg);
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else SSE_MOVSS_XMM_to_M32((uptr)&fpuRegs.fpr[ _Fs_ ].UL, mmreg);
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}
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}
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#ifndef __x86_64__
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else if( (mmreg = _checkMMXreg(MMX_GPR+_Rt_, MODE_READ)) >= 0 ) {
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else
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{
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int mmreg2 = _allocCheckFPUtoXMM(g_pCurInstInfo, _Fs_, MODE_WRITE);
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if( mmreg2 >= 0 ) {
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SetMMXstate();
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SSE2_MOVQ2DQ_MM_to_XMM(mmreg2, mmreg);
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}
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else {
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SetMMXstate();
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MOVDMMXtoM((uptr)&fpuRegs.fpr[ _Fs_ ].UL, mmreg);
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if( mmreg2 >= 0 )
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SSE_MOVSS_XMM_to_XMM(mmreg2, mmreg);
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else
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SSE_MOVSS_XMM_to_M32((uptr)&fpuRegs.fpr[ _Fs_ ].UL, mmreg);
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}
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}
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#endif
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else {
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int mmreg2 = _allocCheckFPUtoXMM(g_pCurInstInfo, _Fs_, MODE_WRITE);
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else
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#ifdef __x86_64__
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{
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mmreg = _allocCheckFPUtoXMM(g_pCurInstInfo, _Fs_, MODE_WRITE);
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if( mmreg2 >= 0 ) SSE_MOVSS_M32_to_XMM(mmreg2, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]);
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else {
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if( mmreg >= 0 )
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{
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SSE_MOVSS_M32_to_XMM(mmreg, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]);
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}
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else
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{
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MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]);
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MOV32RtoM((uptr)&fpuRegs.fpr[ _Fs_ ].UL, EAX);
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}
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}
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#else
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{
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int mmreg2;
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mmreg = _checkMMXreg(MMX_GPR+_Rt_, MODE_READ);
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mmreg2 = _allocCheckFPUtoXMM(g_pCurInstInfo, _Fs_, MODE_WRITE);
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if( mmreg >= 0 )
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{
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if( mmreg2 >= 0 )
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{
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SetMMXstate();
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SSE2_MOVQ2DQ_MM_to_XMM(mmreg2, mmreg);
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}
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else
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{
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SetMMXstate();
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MOVDMMXtoM((uptr)&fpuRegs.fpr[ _Fs_ ].UL, mmreg);
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}
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}
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else
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{
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if( mmreg2 >= 0 )
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{
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SSE_MOVSS_M32_to_XMM(mmreg2, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]);
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}
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else
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{
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MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]);
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MOV32RtoM((uptr)&fpuRegs.fpr[ _Fs_ ].UL, EAX);
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}
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}
|
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}
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#endif
|
||||
}
|
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}
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//------------------------------------------------------------------
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|
|
@ -799,17 +929,23 @@ static u32 s_signbit = 0x80000000;
|
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|
||||
void recCVT_W()
|
||||
{
|
||||
int t0reg;
|
||||
int regs = _checkXMMreg(XMMTYPE_FPREG, _Fs_, MODE_READ);
|
||||
int regs;
|
||||
|
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if( regs >= 0 ) {
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t0reg = _allocTempXMMreg(XMMT_FPS, -1);
|
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regs = _checkXMMreg(XMMTYPE_FPREG, _Fs_, MODE_READ);
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||||
|
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if( regs >= 0 )
|
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{
|
||||
int t0reg = _allocTempXMMreg(XMMT_FPS, -1);
|
||||
_freeXMMreg(t0reg);
|
||||
|
||||
SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&s_signbit);
|
||||
SSE_CVTTSS2SI_XMM_to_R32(EAX, regs);
|
||||
SSE_MOVSS_XMM_to_M32((uptr)&fpuRegs.fpr[ _Fs_ ], regs);
|
||||
}
|
||||
else SSE_CVTTSS2SI_M32_to_R32(EAX, (uptr)&fpuRegs.fpr[ _Fs_ ]);
|
||||
else
|
||||
{
|
||||
SSE_CVTTSS2SI_M32_to_R32(EAX, (uptr)&fpuRegs.fpr[ _Fs_ ]);
|
||||
}
|
||||
|
||||
_deleteFPtoXMMreg(_Fd_, 2);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue