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Added a check for NOPs in the eerec. Seems like "SLL" and "NOP" share the same opcode table entry :p 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2598 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
ramapcsx2 2010-02-17 09:27:35 +00:00
parent 4b4cdf595f
commit 2edc495520
1 changed files with 10 additions and 3 deletions
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13
pcsx2/x86/ix86-32/iR5900-32.cpp
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@ -1221,9 +1221,16 @@ void recompileNextInstruction(int delayslot)
return;
}
}
//If the COP0 DIE bit is disabled, double the cycles. Happens rarely.
s_nBlockCycles += opcode.cycles * (2 - ((cpuRegs.CP0.n.Config >> 18) & 0x1));
opcode.recompile();
// Check for NOP
if (cpuRegs.code == 0x00000000) {
// Note: Tests on a ps2 suggested more like 5 cycles for a NOP. But there's many factors in this..
s_nBlockCycles +=9 * (2 - ((cpuRegs.CP0.n.Config >> 18) & 0x1));
}
else {
//If the COP0 DIE bit is disabled, cycles should be doubled.
s_nBlockCycles += opcode.cycles * (2 - ((cpuRegs.CP0.n.Config >> 18) & 0x1));
opcode.recompile();
}
if( !delayslot ) {
if( s_bFlushReg ) {