mirror of https://github.com/PCSX2/pcsx2.git
ReorderingMTGS: More tweaks to asm memcpy files (made code changes to Linux side, comment changes to Win32 side).
Linux Devs: Let's get this memcpy thing finalized, if its not already. I'd like to merge the current state of this branch into trunk as soon as possible, since its currently looking very stable and has been, up to this point, a code cleanup and stabilization project. (more invasive changes coming soon) git-svn-id: http://pcsx2.googlecode.com/svn/branches/ReorderingMTGS@3518 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
1c9cefd778
commit
2d4c7aaa25
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@ -42,10 +42,12 @@ void _memset16_unaligned( void* dest, u16 data, size_t size );
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extern void memcpy_vibes(void * dest, const void * src, int size);
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extern void gen_memcpy_vibes();
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#define memcpy_fast memcpy_amd_ // Fast memcpy
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#define memcpy_fast memcpy_amd_ // Fast memcpy
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#define memcpy_aligned(d,s,c) memcpy_amd_(d,s,c) // Memcpy with 16-byte Aligned addresses
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#define memcpy_const memcpy_amd_ // Memcpy with constant size
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#define memcpy_constA memcpy_amd_ // Memcpy with constant size and 16-byte aligned
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#define memcpy_qwc_ memcpy_vibes // Memcpy in aligned qwc increments, with 0x400 qwc or less
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#define memcpy_const memcpy_amd_ // Memcpy with constant size
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#define memcpy_constA memcpy_amd_ // Memcpy with constant size and 16-byte aligned
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#define memcpy_qwc_ memcpy_vibes // Memcpy in aligned qwc increments, with 0x400 qwc or less
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#define memcpy_qwc(d,s,c) memcpy_amd_qwc(d,s,c)
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// Useful alternative if we think memcpy_amd_qwc is buggy
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//#define memcpy_qwc(d,s,c) memcpy_amd_(d,s,c*16)
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@ -41,12 +41,10 @@
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MEMCPY_AMD.CPP
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******************************************************************************/
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// Very optimized memcpy() routine for AMD Athlon and Duron family.
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// This code uses any of FOUR different basic copy methods, depending
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// on the transfer size.
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// NOTE: Since this code uses MOVNTQ (also known as "Non-Temporal MOV" or
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// "Streaming Store"), and also uses the software prefetch instructions,
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// be sure you're running on Athlon/Duron or other recent CPU before calling!
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// be sure you're running on P4/Core2/i7, Athlon/Phenom or newer CPUs before
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// calling!
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#define TINY_BLOCK_COPY 64 // upper limit for movsd type copy
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// The smallest copy uses the X86 "movsd" instruction, in an optimized
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@ -68,10 +66,8 @@ MEMCPY_AMD.CPP
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#if defined(_MSC_VER)
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// --------------------------------------------------------------------------------------
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// Fast memcpy as coded by AMD, and then improved by air.
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// --------------------------------------------------------------------------------------
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// Fast memcpy as coded by AMD, and then improved by air for PCSX2 needs.
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__declspec(naked) void __fastcall memcpy_amd_(void *dest, const void *src, size_t n)
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{
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__asm
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@ -92,6 +88,7 @@ __declspec(naked) void __fastcall memcpy_amd_(void *dest, const void *src, size_
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jbe $memcpy_do_align ; it appears to be slower
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cmp eax, 64*1024
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jbe $memcpy_align_done
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$memcpy_do_align:
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mov eax, 8 ; a trick that's faster than rep movsb...
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sub eax, edi ; align destination to qword
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@ -155,99 +155,96 @@ __forceinline void memcpy_vibes(void * dest, const void * src, int size) {
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}
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#endif
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#endif
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// Since MemcpyVibes is already in the project, I'll just tuck the Linux version of memcpy_amd_qwc here for the moment,
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// to get around compilation issues with having it in the headers.
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#ifdef __LINUX__
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// This can be moved later, but Linux doesn't even compile memcpyFast.cpp, so I figured I'd stick it here for now.
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// Quadword Copy! Count is in QWCs (128 bits). Neither source nor dest need to be aligned.
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__forceinline void memcpy_amd_qwc(void *dest, const void *src, size_t qwc)
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{
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// Optimization Analysis: This code is *nearly* optimal. Do not think that using XMM
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// registers will improve copy performance, because they won't. Use of XMMs is only
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// warranted in situations where both source and dest are guaranteed aligned to 16 bytes,
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// and even then the benefits are typically minimal (sometimes slower depending on the
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// amount of data being copied).
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//
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// Thus: MMX are alignment safe, fast, and widely available. Lets just stick with them.
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// --air
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// Linux Conversion note:
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// This code would benefit nicely from having inline-able GAS syntax, since it should
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// allow GCC to optimize the first 3 instructions out of existence in many scenarios.
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// And its called enough times to probably merit the extra effort to ensure proper
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// optimization. --air
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__asm__
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(
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".intel_syntax noprefix\n"
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//"mov ecx, [%[dest]]\n"
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//"mov edx, [%[src]]\n"
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//"mov eax, [%[qwc]]\n" // keep a copy of count
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"mov eax, %[qwc]\n"
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"shr eax, 1\n"
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"jz memcpy_qwc_1\n" // only one 16 byte block to copy?
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"cmp %[qwc], 64\n" // "IN_CACHE_COPY/32"
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"jb memcpy_qwc_loop1\n" // small copies should be cached (definite speedup --air)
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"memcpy_qwc_loop2:\n" // 32-byte blocks, uncached copy
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"prefetchnta [%[src] + 568]\n" // start reading ahead (tested: it helps! --air)
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"movq mm0,[%[src]+0]\n" // read 64 bits
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"movq mm1,[%[src]+8]\n"
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"movq mm2,[%[src]+16]\n"
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"movntq [%[dest]+0], mm0\n" // write 64 bits, bypassing the cache
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"movntq [%[dest]+8], mm1\n"
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"movq mm3,[%[src]+24]\n"
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"movntq [%[dest]+16], mm2\n"
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"movntq [%[dest]+24], mm3\n"
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"add %[src],32\n" // update source pointer
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"add %[dest],32\n" // update destination pointer
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"sub eax,1\n"
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"jnz memcpy_qwc_loop2\n" // last 64-byte block?
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"sfence\n" // flush the write buffer
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"jmp memcpy_qwc_1\n"
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// 32-byte blocks, cached!
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// This *is* important. Removing this and using exclusively non-temporal stores
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// results in noticeable speed loss!
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"memcpy_qwc_loop1:\n"
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"prefetchnta [%[src] + 568]\n" // start reading ahead (tested: it helps! --air)
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"movq mm0,[%[src]+0]\n" // read 64 bits
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"movq mm1,[%[src]+8]\n"
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"movq mm2,[%[src]+16]\n"
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"movq [%[dest]+0], mm0\n" // write 64 bits, bypassing the cache
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"movq [%[dest]+8], mm1\n"
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"movq mm3,[%[src]+24]\n"
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"movq [%[dest]+16], mm2\n"
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"movq [%[dest]+24], mm3\n"
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"add %[src],32\n" // update source pointer
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"add %[dest],32\n" // update destination pointer
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"sub eax,1\n"
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"jnz memcpy_qwc_loop1\n" // last 64-byte block?
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"memcpy_qwc_1:\n"
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"test %[qwc],1\n"
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"jz memcpy_qwc_final\n"
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"movq mm0,[%[src]]\n"
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"movq mm1,[%[src]+8]\n"
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"movq [%[dest]], mm0\n"
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"movq [%[dest]+8], mm1\n"
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"memcpy_qwc_final:\n"
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"emms\n" // clean up the MMX state
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".att_syntax\n"
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: "=&r"(dest), "=&r"(src), "=&r"(qwc)
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: [dest]"0"(dest), [src]"1"(src), [qwc]"2"(qwc)
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: "memory", "eax", "mm0", "mm1", "mm2", "mm3"
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);
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}
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#endif
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#endif
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// Since MemcpyVibes is already in the project, I'll just tuck the Linux version of memcpy_amd_qwc here for the moment,
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// to get around compilation issues with having it in the headers.
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#ifdef __LINUX__
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// This can be moved later, but Linux doesn't even compile memcpyFast.cpp, so I figured I'd stick it here for now.
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// Quadword Copy! Count is in QWCs (128 bits). Neither source nor dest need to be aligned.
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__forceinline void memcpy_amd_qwc(void *dest, const void *src, size_t qwc)
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{
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// Optimization Analysis: This code is *nearly* optimal. Do not think that using XMM
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// registers will improve copy performance, because they won't. Use of XMMs is only
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// warranted in situations where both source and dest are guaranteed aligned to 16 bytes,
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// and even then the benefits are typically minimal (sometimes slower depending on the
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// amount of data being copied).
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//
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// Thus: MMX are alignment safe, fast, and widely available. Lets just stick with them.
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// --air
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// Linux Conversion note:
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// This code would benefit nicely from having inline-able GAS syntax, since it should
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// allow GCC to optimize the first 3 instructions out of existence in many scenarios.
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// And its called enough times to probably merit the extra effort to ensure proper
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// optimization. --air
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__asm__
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(
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".intel_syntax noprefix\n"
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"mov eax, %[qwc]\n" // keep a copy of count for looping
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"shr eax, 1\n"
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"jz memcpy_qwc_1\n" // only one 16 byte block to copy?
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"cmp eax, 64\n" // "IN_CACHE_COPY/32"
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"jb memcpy_qwc_loop1\n" // small copies should be cached (definite speedup --air)
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"memcpy_qwc_loop2:\n" // 32-byte blocks, uncached copy
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"prefetchnta [%[src] + 568]\n" // start reading ahead (tested: it helps! --air)
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"movq mm0,[%[src]+0]\n" // read 64 bits
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"movq mm1,[%[src]+8]\n"
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"movq mm2,[%[src]+16]\n"
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"movntq [%[dest]+0], mm0\n" // write 64 bits, bypassing the cache
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"movntq [%[dest]+8], mm1\n"
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"movq mm3,[%[src]+24]\n"
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"movntq [%[dest]+16], mm2\n"
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"movntq [%[dest]+24], mm3\n"
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"add %[src],32\n" // update source pointer
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"add %[dest],32\n" // update destination pointer
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"sub eax,1\n"
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"jnz memcpy_qwc_loop2\n" // last 64-byte block?
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"sfence\n" // flush the write buffer
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"jmp memcpy_qwc_1\n"
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// 32-byte blocks, cached!
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// This *is* important. Removing this and using exclusively non-temporal stores
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// results in noticeable speed loss!
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"memcpy_qwc_loop1:\n"
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"prefetchnta [%[src] + 568]\n" // start reading ahead (tested: it helps! --air)
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"movq mm0,[%[src]+0]\n" // read 64 bits
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"movq mm1,[%[src]+8]\n"
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"movq mm2,[%[src]+16]\n"
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"movq [%[dest]+0], mm0\n" // write 64 bits, bypassing the cache
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"movq [%[dest]+8], mm1\n"
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"movq mm3,[%[src]+24]\n"
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"movq [%[dest]+16], mm2\n"
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"movq [%[dest]+24], mm3\n"
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"add %[src],32\n" // update source pointer
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"add %[dest],32\n" // update destination pointer
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"sub eax,1\n"
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"jnz memcpy_qwc_loop1\n" // last 64-byte block?
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"memcpy_qwc_1:\n"
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"testl %[qwc],1\n"
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"jz memcpy_qwc_final\n"
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"movq mm0,[%[src]]\n"
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"movq mm1,[%[src]+8]\n"
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"movq [%[dest]], mm0\n"
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"movq [%[dest]+8], mm1\n"
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"memcpy_qwc_final:\n"
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"emms\n" // clean up the MMX state
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".att_syntax\n"
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: "=&r"(dest), "=&r"(src), "=&r"(qwc)
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: [dest]"0"(dest), [src]"1"(src), [qwc]"2"(qwc)
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: "memory", "eax", "mm0", "mm1", "mm2", "mm3"
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);
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}
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#endif
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