mirror of https://github.com/PCSX2/pcsx2.git
mVU Macro: Implemented more stuff and did a big cleanup.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1707 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
4d7bfbb86e
commit
2c1397e559
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@ -87,11 +87,13 @@ microVUt(void) mVUallocMFLAGb(mV, int reg, int fInstance) {
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}
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microVUt(void) mVUallocCFLAGa(mV, int reg, int fInstance) {
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MOV32MtoR(reg, (uptr)&mVU->clipFlag[fInstance]);
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if (fInstance < 4) MOV32MtoR(reg, (uptr)&mVU->clipFlag[fInstance]); // microVU
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else MOV32MtoR(reg, (uptr)&mVU->regs->VI[REG_CLIP_FLAG].UL); // macroVU
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}
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microVUt(void) mVUallocCFLAGb(mV, int reg, int fInstance) {
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MOV32RtoM((uptr)&mVU->clipFlag[fInstance], reg);
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if (fInstance < 4) MOV32RtoM((uptr)&mVU->clipFlag[fInstance], reg); // microVU
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else MOV32RtoM((uptr)&mVU->regs->VI[REG_CLIP_FLAG].UL, reg); // macroVU
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}
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//------------------------------------------------------------------
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@ -25,319 +25,16 @@
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extern void _vu0WaitMicro();
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//------------------------------------------------------------------
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// Macro VU - Helper Macros
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//------------------------------------------------------------------
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#undef _Ft_
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#undef _Fs_
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#undef _Fd_
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#undef _Fsf_
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#undef _Ftf_
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#undef _Cc_
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#define _Ft_ _Rt_
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#define _Fs_ _Rd_
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#define _Fd_ _Sa_
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#define _Fsf_ ((cpuRegs.code >> 21) & 0x03)
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#define _Ftf_ ((cpuRegs.code >> 23) & 0x03)
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#define _Cc_ (cpuRegs.code & 0x03)
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#define REC_COP2_VU0(f) \
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void recV##f( s32 info ) { \
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recVUMI_##f( &VU0, info ); \
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}
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#define INTERPRETATE_COP2_FUNC(f) \
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void recV##f(s32 info) { \
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MOV32ItoM((uptr)&cpuRegs.code, cpuRegs.code); \
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MOV32ItoM((uptr)&cpuRegs.pc, pc); \
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iFlushCall(FLUSH_EVERYTHING); \
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CALLFunc((uptr)V##f); \
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_freeX86regs(); \
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}
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void recCOP2(s32 info);
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void recCOP2_SPECIAL(s32 info);
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void recCOP2_BC2(s32 info);
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void recCOP2_SPECIAL2(s32 info);
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void rec_C2UNK( s32 info ) {
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Console::Error("Cop2 bad opcode: %x", params cpuRegs.code);
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}
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void _vuRegs_C2UNK(VURegs * VU, _VURegsNum *VUregsn) {
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Console::Error("Cop2 bad _vuRegs code:%x", params cpuRegs.code);
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}
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static void recCFC2(s32 info)
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{
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int mmreg;
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if (cpuRegs.code & 1) {
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iFlushCall(FLUSH_NOCONST);
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CALLFunc((uptr)_vu0WaitMicro);
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}
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if(!_Rt_) return;
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_deleteGPRtoXMMreg(_Rt_, 2);
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mmreg = _checkMMXreg(MMX_GPR+_Rt_, MODE_WRITE);
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if (mmreg >= 0) {
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if( _Fs_ >= 16 ) {
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MOVDMtoMMX(mmreg, (uptr)&VU0.VI[ _Fs_ ].UL);
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if (EEINST_ISLIVE1(_Rt_)) { _signExtendGPRtoMMX(mmreg, _Rt_, 0); }
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else { EEINST_RESETHASLIVE1(_Rt_); }
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}
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else MOVDMtoMMX(mmreg, (uptr)&VU0.VI[ _Fs_ ].UL);
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SetMMXstate();
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}
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else {
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MOV32MtoR(EAX, (uptr)&VU0.VI[ _Fs_ ].UL);
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0],EAX);
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if(EEINST_ISLIVE1(_Rt_)) {
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if( _Fs_ < 16 ) {
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// no sign extending
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MOV32ItoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[1],0);
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}
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else {
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CDQ();
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MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[1], EDX);
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}
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}
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else { EEINST_RESETHASLIVE1(_Rt_); }
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}
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_eeOnWriteReg(_Rt_, 1);
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}
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static void recCTC2(s32 info)
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{
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if (cpuRegs.code & 1) {
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iFlushCall(FLUSH_NOCONST);
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CALLFunc((uptr)_vu0WaitMicro);
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}
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if(!_Fs_) return;
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if( GPR_IS_CONST1(_Rt_) )
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{
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switch(_Fs_) {
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case REG_MAC_FLAG: // read-only
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case REG_TPC: // read-only
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case REG_VPU_STAT: // read-only
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break;
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case REG_FBRST:
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if( g_cpuConstRegs[_Rt_].UL[0] & 0x202 )
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iFlushCall(FLUSH_FREE_TEMPX86);
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_deleteX86reg(X86TYPE_VI, REG_FBRST, 2);
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if( g_cpuConstRegs[_Rt_].UL[0] & 2 )
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CALLFunc((uptr)vu0ResetRegs);
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if( g_cpuConstRegs[_Rt_].UL[0] & 0x200 )
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CALLFunc((uptr)vu1ResetRegs);
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MOV16ItoM((uptr)&VU0.VI[REG_FBRST].UL,g_cpuConstRegs[_Rt_].UL[0]&0x0c0c);
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break;
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case REG_CMSAR1: // REG_CMSAR1
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iFlushCall(FLUSH_NOCONST);// since CALLFunc
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assert( _checkX86reg(X86TYPE_VI, REG_VPU_STAT, 0) < 0 &&
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_checkX86reg(X86TYPE_VI, REG_TPC, 0) < 0 );
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// Execute VU1 Micro SubRoutine
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_callFunctionArg1((uptr)vu1ExecMicro, MEM_CONSTTAG, g_cpuConstRegs[_Rt_].UL[0]&0xffff);
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break;
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default:
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{
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if( _Fs_ < 16 )
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assert( (g_cpuConstRegs[_Rt_].UL[0]&0xffff0000)==0);
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// a lot of games have vu0 spinning on some integer
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// then they modify the register and expect vu0 to stop spinning within 10 cycles (donald duck)
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// Use vu0ExecMicro instead because it properly stalls for already-running micro
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// instructions, and also sets the nextBranchCycle as needed. (air)
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MOV32ItoM((uptr)&VU0.VI[_Fs_].UL,g_cpuConstRegs[_Rt_].UL[0]);
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//PUSH32I( -1 );
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iFlushCall(FLUSH_NOCONST);
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CALLFunc((uptr)CpuVU0.ExecuteBlock);
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//CALLFunc((uptr)vu0ExecMicro);
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//ADD32ItoR( ESP, 4 );
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break;
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}
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}
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}
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else
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{
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switch(_Fs_) {
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case REG_MAC_FLAG: // read-only
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case REG_TPC: // read-only
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case REG_VPU_STAT: // read-only
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break;
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case REG_FBRST:
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iFlushCall(FLUSH_FREE_TEMPX86);
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assert( _checkX86reg(X86TYPE_VI, REG_FBRST, 0) < 0 );
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_eeMoveGPRtoR(EAX, _Rt_);
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TEST32ItoR(EAX,0x2);
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j8Ptr[0] = JZ8(0);
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CALLFunc((uptr)vu0ResetRegs);
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_eeMoveGPRtoR(EAX, _Rt_);
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x86SetJ8(j8Ptr[0]);
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TEST32ItoR(EAX,0x200);
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j8Ptr[0] = JZ8(0);
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CALLFunc((uptr)vu1ResetRegs);
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_eeMoveGPRtoR(EAX, _Rt_);
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x86SetJ8(j8Ptr[0]);
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AND32ItoR(EAX,0x0C0C);
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MOV16RtoM((uptr)&VU0.VI[REG_FBRST].UL,EAX);
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break;
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case REG_CMSAR1: // REG_CMSAR1
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iFlushCall(FLUSH_NOCONST);
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_eeMoveGPRtoR(EAX, _Rt_);
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_callFunctionArg1((uptr)vu1ExecMicro, MEM_X86TAG|EAX, 0); // Execute VU1 Micro SubRoutine
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break;
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default:
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_eeMoveGPRtoM((uptr)&VU0.VI[_Fs_].UL,_Rt_);
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// a lot of games have vu0 spinning on some integer
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// then they modify the register and expect vu0 to stop spinning within 10 cycles (donald duck)
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iFlushCall(FLUSH_NOCONST);
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break;
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}
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}
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}
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static void recQMFC2(s32 info)
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{
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int t0reg, fsreg;
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if (cpuRegs.code & 1) {
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iFlushCall(FLUSH_NOCONST);
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CALLFunc((uptr)_vu0WaitMicro);
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}
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if(!_Rt_) return;
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_deleteMMXreg(MMX_GPR+_Rt_, 2);
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_deleteX86reg(X86TYPE_GPR, _Rt_, 2);
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_eeOnWriteReg(_Rt_, 0);
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// could 'borrow' the reg
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fsreg = _checkXMMreg(XMMTYPE_VFREG, _Fs_, MODE_READ);
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if( fsreg >= 0 ) {
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if ( xmmregs[fsreg].mode & MODE_WRITE ) {
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_xmmregs temp;
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t0reg = _allocGPRtoXMMreg(-1, _Rt_, MODE_WRITE);
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SSEX_MOVDQA_XMM_to_XMM(t0reg, fsreg);
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// change regs
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temp = xmmregs[t0reg];
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xmmregs[t0reg] = xmmregs[fsreg];
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xmmregs[fsreg] = temp;
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}
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else {
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// swap regs
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t0reg = _allocGPRtoXMMreg(-1, _Rt_, MODE_WRITE);
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xmmregs[fsreg] = xmmregs[t0reg];
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xmmregs[t0reg].inuse = 0;
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}
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}
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else {
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t0reg = _allocGPRtoXMMreg(-1, _Rt_, MODE_WRITE);
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if (t0reg >= 0) SSE_MOVAPS_M128_to_XMM( t0reg, (uptr)&VU0.VF[_Fs_].UD[0]);
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else _recMove128MtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0], (uptr)&VU0.VF[_Fs_].UL[0]);
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}
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_clearNeededXMMregs();
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}
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static void recQMTC2(s32 info)
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{
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int mmreg;
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if (cpuRegs.code & 1) {
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iFlushCall(FLUSH_NOCONST);
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CALLFunc((uptr)_vu0WaitMicro);
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}
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if (!_Fs_) return;
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mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_READ);
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if( mmreg >= 0) {
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int fsreg = _checkXMMreg(XMMTYPE_VFREG, _Fs_, MODE_WRITE);
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int flag = ((xmmregs[mmreg].mode&MODE_WRITE) && (g_pCurInstInfo->regs[_Rt_]&(EEINST_LIVE0|EEINST_LIVE1|EEINST_LIVE2)));
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if( fsreg >= 0 ) {
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if (flag) {
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SSE_MOVAPS_XMM_to_XMM(fsreg, mmreg);
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}
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else {
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// swap regs
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xmmregs[mmreg] = xmmregs[fsreg];
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xmmregs[mmreg].mode = MODE_WRITE;
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xmmregs[fsreg].inuse = 0;
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g_xmmtypes[mmreg] = XMMT_FPS;
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}
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}
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else {
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if (flag) SSE_MOVAPS_XMM_to_M128((uptr)&cpuRegs.GPR.r[_Rt_], mmreg);
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// swap regs
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xmmregs[mmreg].type = XMMTYPE_VFREG;
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xmmregs[mmreg].VU = 0;
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xmmregs[mmreg].reg = _Fs_;
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xmmregs[mmreg].mode = MODE_WRITE;
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g_xmmtypes[mmreg] = XMMT_FPS;
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}
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}
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else {
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int fsreg = _allocVFtoXMMreg(&VU0, -1, _Fs_, MODE_WRITE);
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if( fsreg >= 0 ) {
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mmreg = _checkMMXreg(MMX_GPR+_Rt_, MODE_READ);
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if( mmreg >= 0) {
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SetMMXstate();
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SSE2_MOVQ2DQ_MM_to_XMM(fsreg, mmreg);
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SSE_MOVHPS_M64_to_XMM(fsreg, (uptr)&cpuRegs.GPR.r[_Rt_].UL[2]);
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}
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else {
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if( GPR_IS_CONST1( _Rt_ ) ) {
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assert( _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_READ) == -1 );
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_flushConstReg(_Rt_);
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}
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SSE_MOVAPS_M128_to_XMM(fsreg, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]);
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}
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}
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else {
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_deleteEEreg(_Rt_, 0);
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_recMove128MtoM((uptr)&VU0.VF[_Fs_].UL[0], (uptr)&cpuRegs.GPR.r[_Rt_].UL[0]);
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}
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}
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_clearNeededXMMregs();
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}
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//------------------------------------------------------------------
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// Macro VU - Instructions
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// Macro VU - Helper Macros / Functions
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//------------------------------------------------------------------
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using namespace R5900::Dynarec;
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#define printCOP2 0&&
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//#define printCOP2 DevCon::Status
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void setupMacroOp(int mode, const char* opName) {
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DevCon::Status(opName);
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printCOP2(opName);
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microVU0.prog.IRinfo.curPC = 0;
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microVU0.code = cpuRegs.code;
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memset(µVU0.prog.IRinfo.info[0], 0, sizeof(microVU0.prog.IRinfo.info[0]));
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@ -346,6 +43,10 @@ void setupMacroOp(int mode, const char* opName) {
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if (mode & 1) { // Q-Reg will be Read
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SSE_MOVSS_M32_to_XMM(xmmPQ, (uptr)µVU0.regs->VI[REG_Q].UL);
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}
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if (mode & 8) { // Clip Instruction
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microVU0.prog.IRinfo.info[0].cFlag.write = 0xff;
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microVU0.prog.IRinfo.info[0].cFlag.lastWrite = 0xff;
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}
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}
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void endMacroOp(int mode) {
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@ -356,7 +57,7 @@ void endMacroOp(int mode) {
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}
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#define REC_COP2_mVU0(f, opName, mode) \
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void recV##f(s32 info) { \
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void recV##f() { \
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setupMacroOp(mode, opName); \
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if (mode & 4) { \
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mVU_##f(µVU0, 0); \
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@ -368,6 +69,19 @@ void endMacroOp(int mode) {
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endMacroOp(mode); \
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}
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#define INTERPRETATE_COP2_FUNC(f) \
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void recV##f() { \
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MOV32ItoM((uptr)&cpuRegs.code, cpuRegs.code); \
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MOV32ItoM((uptr)&cpuRegs.pc, pc); \
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iFlushCall(FLUSH_EVERYTHING); \
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CALLFunc((uptr)V##f); \
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_freeX86regs(); \
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}
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//------------------------------------------------------------------
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// Macro VU - Instructions
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// Macro VU - Redirect Upper Instructions
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//------------------------------------------------------------------
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@ -465,7 +179,7 @@ REC_COP2_mVU0(MSUBAz, "MSUBAz", 0);
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REC_COP2_mVU0(MSUBAw, "MSUBAw", 0);
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REC_COP2_mVU0(OPMULA, "OPMULA", 0);
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REC_COP2_mVU0(OPMSUB, "OPMSUB", 0);
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REC_COP2_VU0 (CLIP);
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REC_COP2_mVU0(CLIP, "CLIP", 8);
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//------------------------------------------------------------------
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// Macro VU - Redirect Lower Instructions
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@ -498,8 +212,8 @@ REC_COP2_mVU0(RXOR, "RXOR", 0);
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// Macro VU - Misc...
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//------------------------------------------------------------------
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void recVNOP (s32 info) {}
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void recVWAITQ(s32 info) {}
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void recVNOP() {}
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void recVWAITQ(){}
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INTERPRETATE_COP2_FUNC(CALLMS);
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INTERPRETATE_COP2_FUNC(CALLMSR);
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@ -507,115 +221,156 @@ INTERPRETATE_COP2_FUNC(CALLMSR);
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// Macro VU - Branches
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//------------------------------------------------------------------
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static void _setupBranchTest() {
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void _setupBranchTest(u32*(jmpType)(u32), bool isLikely) {
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printCOP2("COP2 Branch");
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_eeFlushAllUnused();
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TEST32ItoM((uptr)&VU0.VI[REG_VPU_STAT].UL, 0x100);
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recDoBranchImm(jmpType(0), isLikely);
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}
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void recBC2F(s32 info) {
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_setupBranchTest();
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recDoBranchImm(JNZ32(0));
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void recBC2F() { _setupBranchTest(JNZ32, false); }
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void recBC2T() { _setupBranchTest(JZ32, false); }
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void recBC2FL() { _setupBranchTest(JNZ32, true); }
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void recBC2TL() { _setupBranchTest(JZ32, true); }
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//------------------------------------------------------------------
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// Macro VU - COP2 Transfer Instructions
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//------------------------------------------------------------------
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|
||||
void COP2_Interlock(bool cond) {
|
||||
if (cond) {
|
||||
iFlushCall(FLUSH_NOCONST);
|
||||
CALLFunc((uptr)_vu0WaitMicro);
|
||||
}
|
||||
}
|
||||
|
||||
void recBC2T(s32 info) {
|
||||
_setupBranchTest();
|
||||
recDoBranchImm(JZ32(0));
|
||||
void TEST_FBRST_RESET(uptr resetFunct, int vuIndex) {
|
||||
TEST32ItoR(EAX, (vuIndex) ? 0x200 : 0x002);
|
||||
j8Ptr[0] = JZ8(0);
|
||||
CALLFunc(resetFunct);
|
||||
MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[_Rt_].UL[0]);
|
||||
x86SetJ8(j8Ptr[0]);
|
||||
}
|
||||
|
||||
void recBC2FL(s32 info) {
|
||||
_setupBranchTest();
|
||||
recDoBranchImm_Likely(JNZ32(0));
|
||||
static void recCFC2() {
|
||||
|
||||
printCOP2("CFC2");
|
||||
COP2_Interlock(cpuRegs.code & 1);
|
||||
if (!_Rt_) return;
|
||||
iFlushCall(FLUSH_EVERYTHING);
|
||||
|
||||
MOV32MtoR(EAX, (uptr)µVU0.regs->VI[_Rd_].UL);
|
||||
MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0], EAX);
|
||||
|
||||
if( _Rd_ >= 16 ) {
|
||||
CDQ(); // Sign Extend
|
||||
MOV32RtoM ((uptr)&cpuRegs.GPR.r[_Rt_].UL[1], EDX);
|
||||
}
|
||||
else MOV32ItoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[1], 0);
|
||||
|
||||
// FixMe: I think this is needed, but not sure how it works
|
||||
_eeOnWriteReg(_Rt_, 1);
|
||||
}
|
||||
|
||||
void recBC2TL(s32 info) {
|
||||
_setupBranchTest();
|
||||
recDoBranchImm_Likely(JZ32(0));
|
||||
static void recCTC2() {
|
||||
|
||||
printCOP2("CTC2");
|
||||
COP2_Interlock(cpuRegs.code & 1);
|
||||
if (!_Rd_) return;
|
||||
iFlushCall(FLUSH_EVERYTHING);
|
||||
|
||||
switch(_Rd_) {
|
||||
case REG_MAC_FLAG: case REG_TPC:
|
||||
case REG_VPU_STAT: break; // Read Only Regs
|
||||
case REG_R:
|
||||
MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[_Rt_].UL[0]);
|
||||
OR32ItoR (EAX, 0x3f800000);
|
||||
MOV32RtoM((uptr)µVU0.regs->VI[REG_R].UL, EAX);
|
||||
break;
|
||||
case REG_CMSAR1: // REG_CMSAR1
|
||||
if (_Rt_) {
|
||||
MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[_Rt_].UL[0]);
|
||||
PUSH32R(EAX);
|
||||
}
|
||||
else PUSH32I(0);
|
||||
CALLFunc((uptr)vu1ExecMicro); // Execute VU1 Micro SubRoutine
|
||||
ADD32ItoR(ESP, 4);
|
||||
break;
|
||||
case REG_FBRST:
|
||||
if (!_Rt_) {
|
||||
MOV32ItoM((uptr)µVU0.regs->VI[REG_FBRST].UL, 0);
|
||||
return;
|
||||
}
|
||||
else MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[_Rt_].UL[0]);
|
||||
|
||||
TEST_FBRST_RESET((uptr)vu0ResetRegs, 0);
|
||||
TEST_FBRST_RESET((uptr)vu1ResetRegs, 1);
|
||||
|
||||
AND32ItoR(EAX, 0x0C0C);
|
||||
MOV32RtoM((uptr)µVU0.regs->VI[REG_FBRST].UL, EAX);
|
||||
break;
|
||||
default:
|
||||
_eeMoveGPRtoM((uptr)µVU0.regs->VI[_Rd_].UL, _Rt_);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void recQMFC2() {
|
||||
|
||||
printCOP2("QMFC2");
|
||||
COP2_Interlock(cpuRegs.code & 1);
|
||||
if (!_Rt_) return;
|
||||
iFlushCall(FLUSH_EVERYTHING);
|
||||
|
||||
// FixMe: For some reason this line is needed or else games break:
|
||||
_eeOnWriteReg(_Rt_, 0);
|
||||
|
||||
SSE_MOVAPS_M128_to_XMM(xmmT1, (uptr)µVU0.regs->VF[_Rd_].UL[0]);
|
||||
SSE_MOVAPS_XMM_to_M128((uptr)&cpuRegs.GPR.r[_Rt_].UL[0], xmmT1);
|
||||
}
|
||||
|
||||
static void recQMTC2() {
|
||||
|
||||
printCOP2("QMTC2");
|
||||
COP2_Interlock(cpuRegs.code & 1);
|
||||
if (!_Rd_) return;
|
||||
iFlushCall(FLUSH_EVERYTHING);
|
||||
|
||||
SSE_MOVAPS_M128_to_XMM(xmmT1, (uptr)&cpuRegs.GPR.r[_Rt_].UL[0]);
|
||||
SSE_MOVAPS_XMM_to_M128((uptr)µVU0.regs->VF[_Rd_].UL[0], xmmT1);
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// Macro VU - Tables
|
||||
//------------------------------------------------------------------
|
||||
|
||||
void _vuRegsCOP2_SPECIAL (VURegs * VU, _VURegsNum *VUregsn);
|
||||
void _vuRegsCOP2_SPECIAL2(VURegs * VU, _VURegsNum *VUregsn);
|
||||
|
||||
// information
|
||||
void _vuRegsQMFC2(VURegs * VU, _VURegsNum *VUregsn) {
|
||||
VUregsn->VFread0 = _Fs_;
|
||||
VUregsn->VFr0xyzw= 0xf;
|
||||
void recCOP2();
|
||||
void recCOP2_BC2();
|
||||
void recCOP2_SPEC1();
|
||||
void recCOP2_SPEC2();
|
||||
void rec_C2UNK() {
|
||||
Console::Error("Cop2 bad opcode: %x", params cpuRegs.code);
|
||||
}
|
||||
|
||||
void _vuRegsCFC2(VURegs * VU, _VURegsNum *VUregsn) {
|
||||
VUregsn->VIread = 1<<_Fs_;
|
||||
}
|
||||
|
||||
void _vuRegsQMTC2(VURegs * VU, _VURegsNum *VUregsn) {
|
||||
VUregsn->VFwrite = _Fs_;
|
||||
VUregsn->VFwxyzw= 0xf;
|
||||
}
|
||||
|
||||
void _vuRegsCTC2(VURegs * VU, _VURegsNum *VUregsn) {
|
||||
VUregsn->VIwrite = 1<<_Fs_;
|
||||
}
|
||||
|
||||
void (*_vuRegsCOP2t[32])(VURegs * VU, _VURegsNum *VUregsn) = {
|
||||
_vuRegs_C2UNK, _vuRegsQMFC2, _vuRegsCFC2, _vuRegs_C2UNK, _vuRegs_C2UNK, _vuRegsQMTC2, _vuRegsCTC2, _vuRegs_C2UNK,
|
||||
_vuRegsNOP, _vuRegs_C2UNK, _vuRegs_C2UNK, _vuRegs_C2UNK, _vuRegs_C2UNK, _vuRegs_C2UNK, _vuRegs_C2UNK, _vuRegs_C2UNK,
|
||||
_vuRegsCOP2_SPECIAL,_vuRegsCOP2_SPECIAL,_vuRegsCOP2_SPECIAL,_vuRegsCOP2_SPECIAL,_vuRegsCOP2_SPECIAL,_vuRegsCOP2_SPECIAL,_vuRegsCOP2_SPECIAL,_vuRegsCOP2_SPECIAL,
|
||||
_vuRegsCOP2_SPECIAL,_vuRegsCOP2_SPECIAL,_vuRegsCOP2_SPECIAL,_vuRegsCOP2_SPECIAL,_vuRegsCOP2_SPECIAL,_vuRegsCOP2_SPECIAL,_vuRegsCOP2_SPECIAL,_vuRegsCOP2_SPECIAL,
|
||||
};
|
||||
|
||||
void (*_vuRegsCOP2SPECIAL1t[64])(VURegs * VU, _VURegsNum *VUregsn) = {
|
||||
_vuRegsADDx, _vuRegsADDy, _vuRegsADDz, _vuRegsADDw, _vuRegsSUBx, _vuRegsSUBy, _vuRegsSUBz, _vuRegsSUBw,
|
||||
_vuRegsMADDx, _vuRegsMADDy, _vuRegsMADDz, _vuRegsMADDw, _vuRegsMSUBx, _vuRegsMSUBy, _vuRegsMSUBz, _vuRegsMSUBw,
|
||||
_vuRegsMAXx, _vuRegsMAXy, _vuRegsMAXz, _vuRegsMAXw, _vuRegsMINIx, _vuRegsMINIy, _vuRegsMINIz, _vuRegsMINIw,
|
||||
_vuRegsMULx, _vuRegsMULy, _vuRegsMULz, _vuRegsMULw, _vuRegsMULq, _vuRegsMAXi, _vuRegsMULi, _vuRegsMINIi,
|
||||
_vuRegsADDq, _vuRegsMADDq, _vuRegsADDi, _vuRegsMADDi, _vuRegsSUBq, _vuRegsMSUBq, _vuRegsSUBi, _vuRegsMSUBi,
|
||||
_vuRegsADD, _vuRegsMADD, _vuRegsMUL, _vuRegsMAX, _vuRegsSUB, _vuRegsMSUB, _vuRegsOPMSUB, _vuRegsMINI,
|
||||
_vuRegsIADD, _vuRegsISUB, _vuRegsIADDI, _vuRegs_C2UNK, _vuRegsIAND, _vuRegsIOR, _vuRegs_C2UNK, _vuRegs_C2UNK,
|
||||
_vuRegsNOP, _vuRegsNOP, _vuRegs_C2UNK, _vuRegs_C2UNK, _vuRegsCOP2_SPECIAL2,_vuRegsCOP2_SPECIAL2,_vuRegsCOP2_SPECIAL2,_vuRegsCOP2_SPECIAL2,
|
||||
};
|
||||
|
||||
void (*_vuRegsCOP2SPECIAL2t[128])(VURegs * VU, _VURegsNum *VUregsn) = {
|
||||
_vuRegsADDAx ,_vuRegsADDAy ,_vuRegsADDAz ,_vuRegsADDAw ,_vuRegsSUBAx ,_vuRegsSUBAy ,_vuRegsSUBAz ,_vuRegsSUBAw,
|
||||
_vuRegsMADDAx ,_vuRegsMADDAy ,_vuRegsMADDAz ,_vuRegsMADDAw ,_vuRegsMSUBAx ,_vuRegsMSUBAy ,_vuRegsMSUBAz ,_vuRegsMSUBAw,
|
||||
_vuRegsITOF0 ,_vuRegsITOF4 ,_vuRegsITOF12 ,_vuRegsITOF15 ,_vuRegsFTOI0 ,_vuRegsFTOI4 ,_vuRegsFTOI12 ,_vuRegsFTOI15,
|
||||
_vuRegsMULAx ,_vuRegsMULAy ,_vuRegsMULAz ,_vuRegsMULAw ,_vuRegsMULAq ,_vuRegsABS ,_vuRegsMULAi ,_vuRegsCLIP,
|
||||
_vuRegsADDAq ,_vuRegsMADDAq ,_vuRegsADDAi ,_vuRegsMADDAi ,_vuRegsSUBAq ,_vuRegsMSUBAq ,_vuRegsSUBAi ,_vuRegsMSUBAi,
|
||||
_vuRegsADDA ,_vuRegsMADDA ,_vuRegsMULA ,_vuRegs_C2UNK ,_vuRegsSUBA ,_vuRegsMSUBA ,_vuRegsOPMULA ,_vuRegsNOP,
|
||||
_vuRegsMOVE ,_vuRegsMR32 ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegsLQI ,_vuRegsSQI ,_vuRegsLQD ,_vuRegsSQD,
|
||||
_vuRegsDIV ,_vuRegsSQRT ,_vuRegsRSQRT ,_vuRegsWAITQ ,_vuRegsMTIR ,_vuRegsMFIR ,_vuRegsILWR ,_vuRegsISWR,
|
||||
_vuRegsRNEXT ,_vuRegsRGET ,_vuRegsRINIT ,_vuRegsRXOR ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK,
|
||||
_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK,
|
||||
_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK,
|
||||
_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK,
|
||||
_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK,
|
||||
_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK,
|
||||
_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK,
|
||||
_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK ,_vuRegs_C2UNK,
|
||||
};
|
||||
|
||||
#define cParams VURegs* VU, _VURegsNum* VUregsn
|
||||
void _vuRegsCOP22(cParams) { _vuRegsCOP2t[_Rs_](VU, VUregsn); }
|
||||
void _vuRegsCOP2_SPECIAL (cParams) { _vuRegsCOP2SPECIAL1t[_Funct_](VU, VUregsn); }
|
||||
void _vuRegsCOP2_SPECIAL2(cParams) { _vuRegsCOP2SPECIAL2t[(cpuRegs.code&3)|((cpuRegs.code>>4)&0x7c)](VU, VUregsn); }
|
||||
// This is called by EE Recs to setup sVU info, this isn't needed for mVU Macro (cottonvibes)
|
||||
void _vuRegsCOP22(VURegs* VU, _VURegsNum* VUregsn) {}
|
||||
|
||||
// Recompilation
|
||||
void (*recCOP2t[32])(s32 info) = {
|
||||
void (*recCOP2t[32])() = {
|
||||
rec_C2UNK, recQMFC2, recCFC2, rec_C2UNK, rec_C2UNK, recQMTC2, recCTC2, rec_C2UNK,
|
||||
recCOP2_BC2, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
|
||||
recCOP2_SPECIAL,recCOP2_SPECIAL,recCOP2_SPECIAL,recCOP2_SPECIAL,recCOP2_SPECIAL,recCOP2_SPECIAL,recCOP2_SPECIAL,recCOP2_SPECIAL,
|
||||
recCOP2_SPECIAL,recCOP2_SPECIAL,recCOP2_SPECIAL,recCOP2_SPECIAL,recCOP2_SPECIAL,recCOP2_SPECIAL,recCOP2_SPECIAL,recCOP2_SPECIAL,
|
||||
recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1,
|
||||
recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1, recCOP2_SPEC1,
|
||||
};
|
||||
|
||||
void (*recCOP2_BC2t[32])(s32 info) = {
|
||||
void (*recCOP2_BC2t[32])() = {
|
||||
recBC2F, recBC2T, recBC2FL, recBC2TL, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
|
||||
rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
|
||||
rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
|
||||
rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK, rec_C2UNK,
|
||||
};
|
||||
|
||||
void (*recCOP2SPECIAL1t[64])(s32 info) = {
|
||||
void (*recCOP2SPECIAL1t[64])() = {
|
||||
recVADDx, recVADDy, recVADDz, recVADDw, recVSUBx, recVSUBy, recVSUBz, recVSUBw,
|
||||
recVMADDx, recVMADDy, recVMADDz, recVMADDw, recVMSUBx, recVMSUBy, recVMSUBz, recVMSUBw,
|
||||
recVMAXx, recVMAXy, recVMAXz, recVMAXw, recVMINIx, recVMINIy, recVMINIz, recVMINIw,
|
||||
|
|
@ -623,10 +378,10 @@ void (*recCOP2SPECIAL1t[64])(s32 info) = {
|
|||
recVADDq, recVMADDq, recVADDi, recVMADDi, recVSUBq, recVMSUBq, recVSUBi, recVMSUBi,
|
||||
recVADD, recVMADD, recVMUL, recVMAX, recVSUB, recVMSUB, recVOPMSUB, recVMINI,
|
||||
recVIADD, recVISUB, recVIADDI, rec_C2UNK, recVIAND, recVIOR, rec_C2UNK, rec_C2UNK,
|
||||
recVCALLMS, recVCALLMSR, rec_C2UNK, rec_C2UNK, recCOP2_SPECIAL2,recCOP2_SPECIAL2,recCOP2_SPECIAL2,recCOP2_SPECIAL2,
|
||||
recVCALLMS, recVCALLMSR,rec_C2UNK, rec_C2UNK, recCOP2_SPEC2, recCOP2_SPEC2, recCOP2_SPEC2, recCOP2_SPEC2,
|
||||
};
|
||||
|
||||
void (*recCOP2SPECIAL2t[128])(s32 info) = {
|
||||
void (*recCOP2SPECIAL2t[128])() = {
|
||||
recVADDAx, recVADDAy, recVADDAz, recVADDAw, recVSUBAx, recVSUBAy, recVSUBAz, recVSUBAw,
|
||||
recVMADDAx,recVMADDAy, recVMADDAz, recVMADDAw, recVMSUBAx, recVMSUBAy, recVMSUBAz, recVMSUBAw,
|
||||
recVITOF0, recVITOF4, recVITOF12, recVITOF15, recVFTOI0, recVFTOI4, recVFTOI12, recVFTOI15,
|
||||
|
|
@ -647,26 +402,9 @@ void (*recCOP2SPECIAL2t[128])(s32 info) = {
|
|||
|
||||
namespace R5900 {
|
||||
namespace Dynarec {
|
||||
namespace OpcodeImpl
|
||||
{
|
||||
void recCOP2()
|
||||
{
|
||||
VU0.code = cpuRegs.code;
|
||||
|
||||
g_pCurInstInfo->vuregs.pipe = 0xff; // to notify eeVURecompileCode that COP2
|
||||
s32 info = eeVURecompileCode(&VU0, &g_pCurInstInfo->vuregs);
|
||||
|
||||
info |= PROCESS_VU_COP2;
|
||||
info |= PROCESS_VU_UPDATEFLAGS;
|
||||
|
||||
recCOP2t[_Rs_]( info );
|
||||
|
||||
_freeX86regs();
|
||||
}
|
||||
}}}
|
||||
|
||||
void recCOP2_BC2(s32 info) { recCOP2_BC2t[_Rt_](info); }
|
||||
void recCOP2_SPECIAL(s32 info) { recCOP2SPECIAL1t[_Funct_]( info ); }
|
||||
void recCOP2_SPECIAL2(s32 info) { recCOP2SPECIAL2t[(cpuRegs.code&3)|((cpuRegs.code>>4)&0x7c)](info); }
|
||||
namespace OpcodeImpl { void recCOP2() { recCOP2t[_Rs_](); }}}}
|
||||
void recCOP2_BC2 () { recCOP2_BC2t[_Rt_](); }
|
||||
void recCOP2_SPEC1() { recCOP2SPECIAL1t[_Funct_](); }
|
||||
void recCOP2_SPEC2() { recCOP2SPECIAL2t[(cpuRegs.code&3)|((cpuRegs.code>>4)&0x7c)](); }
|
||||
|
||||
#endif // CHECK_MACROVU0
|
||||
|
|
|
|||
Loading…
Reference in New Issue