mirror of https://github.com/PCSX2/pcsx2.git
Various tag stuff.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2258 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42
parent
7e2ff95a97
commit
2b1a9277ee
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@ -18,6 +18,7 @@
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#include <ctype.h>
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#include <time.h>
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#include <sys/time.h>
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#include <wx/utils.h>
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extern "C" __aligned16 u8 _xmm_backup[16*2];
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extern "C" __aligned16 u8 _mmx_backup[8*4];
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95
pcsx2/Dmac.h
95
pcsx2/Dmac.h
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@ -25,17 +25,24 @@ extern u8 *psH; // hw mem
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union tDMA_CHCR {
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struct {
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u32 DIR : 1;
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bool DIR : 1;
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u32 reserved1 : 1;
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u32 MOD : 2;
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u32 ASP : 2;
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u32 TTE : 1;
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u32 TIE : 1;
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u32 STR : 1;
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bool TTE : 1;
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bool TIE : 1;
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bool STR : 1;
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u32 reserved2 : 7;
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u32 TAG : 16;
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};
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u32 _u32;
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tDMA_CHCR( u32 val) { _u32 = val; }
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bool test(u32 flags) { return !!(_u32 & flags); }
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void set_flags(u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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};
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union tDMA_SADR {
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@ -44,6 +51,10 @@ union tDMA_SADR {
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u32 reserved2 : 18;
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};
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u32 _u32;
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tDMA_SADR(u32 val) { _u32 = val; }
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void reset() { _u32 = 0; }
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};
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@ -121,7 +132,7 @@ enum DMAInter
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IPU0intr = 0x00080008,
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IPU1intr = 0x00100010,
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SIF0intr = 0x00200020,
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SIF1intr =0x00400040,
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SIF1intr = 0x00400040,
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SIF2intr = 0x00800080,
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SPR0intr = 0x01000100,
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SPR1intr = 0x02000200,
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@ -131,8 +142,8 @@ enum DMAInter
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union tDMAC_CTRL {
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struct {
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u32 DMAE : 1;
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u32 RELE : 1;
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bool DMAE : 1;
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bool RELE : 1;
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u32 MFD : 2;
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u32 STS : 2;
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u32 STD : 2;
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@ -140,26 +151,36 @@ union tDMAC_CTRL {
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u32 reserved1 : 21;
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};
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u32 _u32;
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tDMAC_CTRL(u32 val) { _u32 = val; }
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bool test(u32 flags) { return !!(_u32 & flags); }
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void set_flags(u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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};
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union tDMAC_STAT {
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struct {
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u32 CIS : 10;
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u32 reserved1 : 3;
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u32 SIS : 1;
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u32 MEIS : 1;
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u32 BEIS : 1;
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bool SIS : 1;
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bool MEIS : 1;
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bool BEIS : 1;
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u32 CIM : 10;
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u32 reserved2 : 3;
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u32 SIM : 1;
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u32 MEIM : 1;
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bool SIM : 1;
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bool MEIM : 1;
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u32 reserved3 : 1;
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};
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u32 _u32;
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tDMAC_STAT(u32 val) { _u32 = val; }
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bool test(u32 flags) { return !!(_u32 & flags); }
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void set(u32 flags) { _u32 |= flags; }
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void clear(u32 flags) { _u32 &= ~flags; }
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void set_flags(u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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};
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union tDMAC_PCR {
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@ -171,6 +192,13 @@ union tDMAC_PCR {
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u32 PCE : 1;
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};
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u32 _u32;
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tDMAC_PCR(u32 val) { _u32 = val; }
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bool test(u32 flags) { return !!(_u32 & flags); }
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void set_flags(u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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};
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union tDMAC_SQWC {
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@ -181,6 +209,13 @@ union tDMAC_SQWC {
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u32 reserved2 : 8;
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};
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u32 _u32;
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tDMAC_SQWC(u32 val) { _u32 = val; }
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bool test(u32 flags) { return !!(_u32 & flags); }
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void set_flags(u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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};
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union tDMAC_RBSR {
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@ -189,6 +224,10 @@ union tDMAC_RBSR {
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u32 reserved1 : 1;
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};
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u32 _u32;
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tDMAC_RBSR(u32 val) { _u32 = val; }
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void reset() { _u32 = 0; }
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};
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union tDMAC_RBOR {
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@ -197,6 +236,10 @@ union tDMAC_RBOR {
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u32 reserved1 : 1;
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};
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u32 _u32;
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tDMAC_RBOR(u32 val) { _u32 = val; }
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void reset() { _u32 = 0; }
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};
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union tDMAC_STADR {
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@ -205,6 +248,10 @@ union tDMAC_STADR {
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u32 reserved1 : 1;
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};
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u32 _u32;
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tDMAC_STADR(u32 val) { _u32 = val; }
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void reset() { _u32 = 0; }
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};
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struct DMACregisters
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@ -233,9 +280,12 @@ union tINTC_STAT {
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};
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u32 _u32;
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tINTC_STAT(u32 val) { _u32 = val; }
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bool test(u32 flags) { return !!(_u32 & flags); }
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void set(u32 flags) { _u32 |= flags; }
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void clear(u32 flags) { _u32 &= ~flags; }
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void set_flags(u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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};
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union tINTC_MASK {
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@ -244,6 +294,13 @@ union tINTC_MASK {
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u32 placeholder:22;
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};
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u32 _u32;
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tINTC_MASK(u32 val) { _u32 = val; }
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bool test(u32 flags) { return !!(_u32 & flags); }
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void set_flags(u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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};
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struct INTCregisters
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@ -279,11 +336,11 @@ static __forceinline u32 *_dmaGetAddr(DMACh *dma, u32 addr, u32 num)
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if (ptr == NULL)
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{
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// DMA Error
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dmacRegs->stat.BEIS = 1; // BUS Error
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dmacRegs->stat.BEIS = true; // BUS Error
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// DMA End
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dmacRegs->stat.set(1 << num);
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dma->chcr.STR = 0;
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dmacRegs->stat.set_flags(1 << num);
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dma->chcr.STR = false;
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}
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return ptr;
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12
pcsx2/GS.cpp
12
pcsx2/GS.cpp
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@ -101,16 +101,16 @@ void gsReset()
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GSCSRr = 0x551B4000; // Set the FINISH bit to 1 for now
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GSIMR = 0x7f00;
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gifRegs->stat._u32 = 0;
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gifRegs->ctrl._u32 = 0;
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gifRegs->mode._u32 = 0;
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gifRegs->stat.reset();
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gifRegs->ctrl.reset();
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gifRegs->mode.reset();
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}
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void gsGIFReset()
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{
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gifRegs->stat._u32 = 0;
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gifRegs->ctrl._u32 = 0;
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gifRegs->mode._u32 = 0;
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gifRegs->stat.reset();
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gifRegs->ctrl.reset();
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gifRegs->mode.reset();
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}
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void gsCSRwrite(u32 value)
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@ -59,12 +59,12 @@ __forceinline void gsInterrupt()
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if ((vif1.cmd & 0x7f) == 0x51) // DIRECTHL
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{
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// Not waiting for the end of the Gif transfer.
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if (Path3progress != IMAGE_MODE) vif1Regs->stat.VGW = 0;
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if (Path3progress != IMAGE_MODE) vif1Regs->stat.VGW = false;
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}
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if (Path3progress == STOPPED_MODE)
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{
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gifRegs->stat.clear(GIF_STAT_APATH3 | GIF_STAT_OPH);
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gifRegs->stat.clear_flags(GIF_STAT_APATH3 | GIF_STAT_OPH);
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}
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if ((gif->qwc > 0) || (!gspath3done))
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@ -83,10 +83,10 @@ __forceinline void gsInterrupt()
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gspath3done = false;
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gscycles = 0;
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gif->chcr.STR = 0;
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vif1Regs->stat.VGW = 0;
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gif->chcr.STR = false;
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vif1Regs->stat.VGW = false;
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gifRegs->stat.clear(GIF_STAT_APATH3 | GIF_STAT_OPH | GIF_STAT_P3Q | GIF_STAT_FQC);
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gifRegs->stat.clear_flags(GIF_STAT_APATH3 | GIF_STAT_OPH | GIF_STAT_P3Q | GIF_STAT_FQC);
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clearFIFOstuff(false);
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hwDmacIrq(DMAC_GIF);
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@ -97,7 +97,7 @@ __forceinline void gsInterrupt()
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static u32 WRITERING_DMA(u32 *pMem, u32 qwc)
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{
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gifRegs->stat.APATH = GIF_APATH3;
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gifRegs->stat.OPH = 1;
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gifRegs->stat.OPH = true;
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int size = GetMTGS().PrepDataPacket(GIF_PATH_3, pMem, qwc);
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u8* pgsmem = GetMTGS().GetDataPacketPtr();
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@ -231,7 +231,7 @@ void GIFdma()
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if (Path3progress == STOPPED_MODE) /*|| (vif1Regs->stat._u32 |= VIF1_STAT_VGW) == 0*/
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{
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vif1Regs->stat.VGW = 0;
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vif1Regs->stat.VGW = false;
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if (gif->qwc == 0) CPU_INT(2, 16);
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return;
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}
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@ -313,7 +313,7 @@ void dmaGIF()
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Path3progress = STOPPED_MODE;
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gspath3done = false; // For some reason this doesn't clear? So when the system starts the thread, we will clear it :)
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gifRegs->stat.P3Q = 1;
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gifRegs->stat.P3Q = true;
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gifRegs->stat.FQC |= 0x10; // hack ;)
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clearFIFOstuff(true);
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@ -528,12 +528,12 @@ void gifMFIFOInterrupt()
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if (Path3progress == STOPPED_MODE)
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{
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gifRegs->stat.APATH = GIF_APATH_IDLE;
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gifRegs->stat.OPH = 0;
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gifRegs->stat.OPH = false;
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}
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if ((spr0->chcr.STR) && (spr0->qwc == 0))
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{
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spr0->chcr.STR = 0;
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spr0->chcr.STR = false;
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hwDmacIrq(DMAC_FROM_SPR);
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}
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@ -560,7 +560,7 @@ void gifMFIFOInterrupt()
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gifstate |= GIF_STATE_EMPTY;
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gifempty = true;
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gifRegs->stat.IMT = 0;
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gifRegs->stat.IMT = false;
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return;
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}
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mfifoGIFtransfer(0);
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@ -580,10 +580,10 @@ void gifMFIFOInterrupt()
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gspath3done = false;
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gscycles = 0;
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gifRegs->stat.clear(GIF_STAT_APATH3 | GIF_STAT_OPH | GIF_STAT_P3Q | GIF_STAT_FQC); // OPH, APATH, P3Q, FQC = 0
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gifRegs->stat.clear_flags(GIF_STAT_APATH3 | GIF_STAT_OPH | GIF_STAT_P3Q | GIF_STAT_FQC); // OPH, APATH, P3Q, FQC = 0
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vif1Regs->stat.VGW = 0;
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gif->chcr.STR = 0;
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vif1Regs->stat.VGW = false;
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gif->chcr.STR = false;
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gifstate = GIF_STATE_READY;
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hwDmacIrq(DMAC_GIF);
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clearFIFOstuff(false);
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114
pcsx2/Gif.h
114
pcsx2/Gif.h
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@ -62,32 +62,39 @@ union tGIF_CTRL
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{
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struct
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{
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u32 RST : 1;
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bool RST : 1;
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u32 reserved1 : 2;
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u32 PSE : 1;
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bool PSE : 1;
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u32 reserved2 : 28;
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};
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u32 _u32;
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tGIF_CTRL( u32 val ) : _u32( val )
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{
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}
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tGIF_CTRL(u32 val) { _u32 = val; }
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bool test(u32 flags) { return !!(_u32 & flags); }
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void set_flags(u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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};
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union tGIF_MODE
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{
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struct
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{
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u32 M3R : 1;
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bool M3R : 1;
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u32 reserved1 : 1;
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u32 IMT : 1;
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bool IMT : 1;
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u32 reserved2 : 29;
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};
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u32 _u32;
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tGIF_MODE( u32 val ) : _u32( val )
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{
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}
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tGIF_MODE(u32 val) { _u32 = val; }
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void write(u32 val) { _u32 = val; }
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bool test(u32 flags) { return !!(_u32 & flags); }
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void set_flags(u32 flags) { _u32 |= flags; }
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void clear_flags(u32 flags) { _u32 &= ~flags; }
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void reset() { _u32 = 0; }
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};
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enum gif_paths
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@ -102,31 +109,30 @@ union tGIF_STAT
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{
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struct
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{
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u32 M3R : 1;
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u32 M3P : 1;
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u32 IMT : 1;
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u32 PSE : 1;
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bool M3R : 1;
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bool M3P : 1;
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bool IMT : 1;
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bool PSE : 1;
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u32 reserved1 : 1;
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u32 IP3 : 1;
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u32 P3Q : 1;
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u32 P2Q : 1;
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u32 P1Q : 1;
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u32 OPH : 1;
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bool IP3 : 1;
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bool P3Q : 1;
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bool P2Q : 1;
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bool P1Q : 1;
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bool OPH : 1;
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u32 APATH : 2;
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u32 DIR : 1;
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bool DIR : 1;
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u32 reserved2 : 11;
|
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u32 FQC : 5;
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u32 reserved3 : 3;
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};
|
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u32 _u32;
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|
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tGIF_STAT( u32 val ) : _u32( val )
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{
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}
|
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|
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tGIF_STAT(u32 val) { _u32 = val; }
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|
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bool test(u32 flags) { return !!(_u32 & flags); }
|
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void set(u32 flags) { _u32 |= flags; }
|
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void clear(u32 flags) { _u32 &= ~flags; }
|
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void set_flags(u32 flags) { _u32 |= flags; }
|
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void clear_flags(u32 flags) { _u32 &= ~flags; }
|
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void reset() { _u32 = 0; }
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};
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union tGIF_TAG0
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|
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@ -138,10 +144,13 @@ union tGIF_TAG0
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u32 TAG : 16;
|
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};
|
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u32 _u32;
|
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|
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tGIF_TAG0( u32 val ) : _u32( val )
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{
|
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}
|
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|
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tGIF_TAG0(u32 val) { _u32 = val; }
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|
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bool test(u32 flags) { return !!(_u32 & flags); }
|
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void set_flags(u32 flags) { _u32 |= flags; }
|
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void clear_flags(u32 flags) { _u32 &= ~flags; }
|
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void reset() { _u32 = 0; }
|
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};
|
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|
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union tGIF_TAG1
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|
|
@ -155,10 +164,13 @@ union tGIF_TAG1
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u32 NREG : 4;
|
||||
};
|
||||
u32 _u32;
|
||||
|
||||
tGIF_TAG1( u32 val ) : _u32( val )
|
||||
{
|
||||
}
|
||||
|
||||
tGIF_TAG1(u32 val) { _u32 = val; }
|
||||
|
||||
bool test(u32 flags) { return !!(_u32 & flags); }
|
||||
void set_flags(u32 flags) { _u32 |= flags; }
|
||||
void clear_flags(u32 flags) { _u32 &= ~flags; }
|
||||
void reset() { _u32 = 0; }
|
||||
};
|
||||
|
||||
union tGIF_CNT
|
||||
|
|
@ -173,10 +185,13 @@ union tGIF_CNT
|
|||
|
||||
};
|
||||
u32 _u32;
|
||||
|
||||
tGIF_CNT( u32 val ) : _u32( val )
|
||||
{
|
||||
}
|
||||
|
||||
tGIF_CNT(u32 val) { _u32 = val; }
|
||||
|
||||
bool test(u32 flags) { return !!(_u32 & flags); }
|
||||
void set_flags(u32 flags) { _u32 |= flags; }
|
||||
void clear_flags(u32 flags) { _u32 &= ~flags; }
|
||||
void reset() { _u32 = 0; }
|
||||
};
|
||||
|
||||
union tGIF_P3CNT
|
||||
|
|
@ -187,10 +202,10 @@ union tGIF_P3CNT
|
|||
u32 reserved1 : 17;
|
||||
};
|
||||
u32 _u32;
|
||||
|
||||
tGIF_P3CNT( u32 val ) : _u32( val )
|
||||
{
|
||||
}
|
||||
|
||||
tGIF_P3CNT(u32 val) { _u32 = val; }
|
||||
|
||||
void reset() { _u32 = 0; }
|
||||
};
|
||||
|
||||
union tGIF_P3TAG
|
||||
|
|
@ -202,10 +217,13 @@ union tGIF_P3TAG
|
|||
u32 reserved1 : 16;
|
||||
};
|
||||
u32 _u32;
|
||||
|
||||
tGIF_P3TAG( u32 val ) : _u32( val )
|
||||
{
|
||||
}
|
||||
|
||||
tGIF_P3TAG(u32 val) { _u32 = val; }
|
||||
|
||||
bool test(u32 flags) { return !!(_u32 & flags); }
|
||||
void set_flags(u32 flags) { _u32 |= flags; }
|
||||
void clear_flags(u32 flags) { _u32 &= ~flags; }
|
||||
void reset() { _u32 = 0; }
|
||||
};
|
||||
|
||||
struct GIFregisters
|
||||
|
|
|
|||
|
|
@ -715,15 +715,15 @@ void __fastcall hwWrite32_page_03( u32 mem, u32 value )
|
|||
if (value & 0x1)
|
||||
gsGIFReset();
|
||||
else if ( value & 8 )
|
||||
gifRegs->stat.PSE = 1;
|
||||
gifRegs->stat.PSE = true;
|
||||
else
|
||||
gifRegs->stat.PSE = 0;
|
||||
gifRegs->stat.PSE = false;
|
||||
break;
|
||||
|
||||
case GIF_MODE:
|
||||
{
|
||||
// need to set GIF_MODE (hamster ball)
|
||||
gifRegs->mode._u32 = value;
|
||||
gifRegs->mode.write(value);
|
||||
|
||||
// set/clear bits 0 and 2 as per the GIF_MODE value.
|
||||
const u32 bitmask = GIF_MODE_M3R | GIF_MODE_IMT;
|
||||
|
|
@ -1079,9 +1079,9 @@ void __fastcall hwWrite64_page_03( u32 mem, const mem64_t* srcval )
|
|||
else
|
||||
{
|
||||
if( value & 8 )
|
||||
gifRegs->stat.PSE = 1;
|
||||
gifRegs->stat.PSE = true;
|
||||
else
|
||||
gifRegs->stat.PSE = 0;
|
||||
gifRegs->stat.PSE = false;
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@
|
|||
# define IPU_FORCEINLINE __forceinline
|
||||
#endif
|
||||
|
||||
static tIPU_DMA g_nDMATransfer;
|
||||
static tIPU_DMA g_nDMATransfer(0);
|
||||
|
||||
// FIXME - g_nIPU0Data and Pointer are not saved in the savestate, which breaks savestates for some
|
||||
// FMVs at random (if they get saved during the half frame of a 30fps rate). The fix is complicated
|
||||
|
|
@ -140,7 +140,7 @@ int ipuInit()
|
|||
memzero(*ipuRegs);
|
||||
memzero(g_BP);
|
||||
init_g_decoder();
|
||||
g_nDMATransfer._u32 = 0;
|
||||
g_nDMATransfer.reset();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -148,7 +148,7 @@ int ipuInit()
|
|||
void ipuReset()
|
||||
{
|
||||
memzero(*ipuRegs);
|
||||
g_nDMATransfer._u32 = 0;
|
||||
g_nDMATransfer.reset();
|
||||
}
|
||||
|
||||
void ipuShutdown()
|
||||
|
|
@ -247,7 +247,6 @@ __forceinline u32 ipuRead32(u32 mem)
|
|||
return ipuRegs->ctrl._u32;
|
||||
|
||||
ipucase(IPU_BP): // IPU_BP
|
||||
|
||||
ipuRegs->ipubp = g_BP.BP & 0x7f;
|
||||
ipuRegs->ipubp |= g_BP.IFC << 8;
|
||||
ipuRegs->ipubp |= (g_BP.FP + g_BP.bufferhasnew) << 16;
|
||||
|
|
@ -303,7 +302,7 @@ void ipuSoftReset()
|
|||
|
||||
coded_block_pattern = 0;
|
||||
|
||||
ipuRegs->ctrl._u32 = 0;
|
||||
ipuRegs->ctrl.reset();
|
||||
ipuRegs->top = 0;
|
||||
ipuCurCmd = 0xffffffff;
|
||||
|
||||
|
|
@ -336,7 +335,7 @@ __forceinline void ipuWrite32(u32 mem, u32 value)
|
|||
ipucase(IPU_CTRL): // IPU_CTRL
|
||||
// CTRL = the first 16 bits of ctrl [0x8000ffff], + value for the next 16 bits,
|
||||
// minus the reserved bits. (18-19; 27-29) [0x47f30000]
|
||||
ipuRegs->ctrl._u32 = (value & 0x47f30000) | (ipuRegs->ctrl._u32 & 0x8000ffff);
|
||||
ipuRegs->ctrl.write(value);
|
||||
if (ipuRegs->ctrl.IDP == 3)
|
||||
{
|
||||
Console.WriteLn("IPU Invalid Intra DC Precision, switching to 9 bits");
|
||||
|
|
@ -432,14 +431,16 @@ static __forceinline BOOL ipuIDEC(u32 val)
|
|||
g_decoder.intra_vlc_format = ipuRegs->ctrl.IVF;
|
||||
g_decoder.scan = ipuRegs->ctrl.AS ? mpeg2_scan_alt : mpeg2_scan_norm;
|
||||
g_decoder.intra_dc_precision = ipuRegs->ctrl.IDP;
|
||||
|
||||
//from IDEC value
|
||||
g_decoder.quantizer_scale = idec.QSC;
|
||||
g_decoder.frame_pred_frame_dct = !idec.DTD;
|
||||
g_decoder.sgn = idec.SGN;
|
||||
g_decoder.dte = idec.DTE;
|
||||
g_decoder.ofm = idec.OFM;
|
||||
|
||||
//other stuff
|
||||
g_decoder.dcr = 1;//resets DC prediction value
|
||||
g_decoder.dcr = 1; // resets DC prediction value
|
||||
|
||||
s_routine = so_create(mpeg2sliceIDEC, &s_RoutineDone, s_tempstack, sizeof(s_tempstack));
|
||||
pxAssert(s_routine != NULL);
|
||||
|
|
@ -485,6 +486,7 @@ static __forceinline BOOL ipuBDEC(u32 val)
|
|||
g_decoder.intra_vlc_format = ipuRegs->ctrl.IVF;
|
||||
g_decoder.scan = ipuRegs->ctrl.AS ? mpeg2_scan_alt : mpeg2_scan_norm;
|
||||
g_decoder.intra_dc_precision = ipuRegs->ctrl.IDP;
|
||||
|
||||
//from BDEC value
|
||||
/* JayteeMaster: the quantizer (linear/non linear) depends on the q_scale_type */
|
||||
g_decoder.quantizer_scale = g_decoder.q_scale_type ? non_linear_quantizer_scale [bdec.QSC] : bdec.QSC << 1;
|
||||
|
|
@ -537,6 +539,7 @@ static BOOL __fastcall ipuVDEC(u32 val)
|
|||
}
|
||||
|
||||
g_BP.BP += (g_decoder.bitstream_bits + 16);
|
||||
|
||||
if ((int)g_BP.BP < 0)
|
||||
{
|
||||
g_BP.BP += 128;
|
||||
|
|
@ -1365,7 +1368,7 @@ static __forceinline bool IPU1chain(int &totalqwc)
|
|||
|
||||
if (ipu1dma->qwc > 0)
|
||||
{
|
||||
g_nDMATransfer.ACTV1 = 1;
|
||||
g_nDMATransfer.ACTV1 = true;
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
|
@ -1449,7 +1452,7 @@ int IPU1dma()
|
|||
|
||||
if (!(ipu1dma->chcr.STR) || (cpuRegs.interrupt & (1 << DMAC_TO_IPU))) return 0;
|
||||
|
||||
pxAssert(g_nDMATransfer.TIE1 == 0);
|
||||
pxAssert(g_nDMATransfer.TIE1 == false);
|
||||
|
||||
//We need to make sure GIF has flushed before sending IPU data, it seems to REALLY screw FFX videos
|
||||
flushGIF();
|
||||
|
|
@ -1465,9 +1468,9 @@ int IPU1dma()
|
|||
Console.WriteLn("IPU1 TIE");
|
||||
|
||||
IPU_INT_TO(totalqwc * BIAS);
|
||||
g_nDMATransfer.TIE1 = 1;
|
||||
g_nDMATransfer.DOTIE1 = 0;
|
||||
g_nDMATransfer.ACTV1 = 0;
|
||||
g_nDMATransfer.TIE1 = true;
|
||||
g_nDMATransfer.DOTIE1 = false;
|
||||
g_nDMATransfer.ACTV1 = false;
|
||||
|
||||
return totalqwc;
|
||||
}
|
||||
|
|
@ -1492,7 +1495,7 @@ int IPU1dma()
|
|||
|
||||
IPU_LOG("IPU dmaIrq Set");
|
||||
IPU_INT_TO(totalqwc * BIAS);
|
||||
g_nDMATransfer.TIE1 = 1;
|
||||
g_nDMATransfer.TIE1 = true;
|
||||
return totalqwc;
|
||||
}
|
||||
|
||||
|
|
@ -1503,8 +1506,8 @@ int IPU1dma()
|
|||
}
|
||||
}
|
||||
|
||||
g_nDMATransfer.DOTIE1 = 0;
|
||||
g_nDMATransfer.ACTV1 = 0;
|
||||
g_nDMATransfer.DOTIE1 = false;
|
||||
g_nDMATransfer.ACTV1 = false;
|
||||
}
|
||||
|
||||
// Normal Mode & qwc is finished
|
||||
|
|
@ -1561,7 +1564,7 @@ int IPU1dma()
|
|||
}
|
||||
|
||||
IPU_INT_TO(ipu1cycles + totalqwc * BIAS); // Should it be (ipu1cycles + totalqwc) * BIAS?
|
||||
g_nDMATransfer.TIE1 = 1;
|
||||
g_nDMATransfer.TIE1 = true;
|
||||
return totalqwc;
|
||||
}
|
||||
else
|
||||
|
|
@ -1682,13 +1685,13 @@ int IPU0dma()
|
|||
case NO_STD:
|
||||
break;
|
||||
case STD_GIF: // GIF
|
||||
g_nDMATransfer.GIFSTALL = 1;
|
||||
g_nDMATransfer.GIFSTALL = true;
|
||||
break;
|
||||
case STD_VIF1: // VIF
|
||||
g_nDMATransfer.VIFSTALL = 1;
|
||||
g_nDMATransfer.VIFSTALL = true;
|
||||
break;
|
||||
case STD_SIF1:
|
||||
g_nDMATransfer.SIFSTALL = 1;
|
||||
g_nDMATransfer.SIFSTALL = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -1722,28 +1725,28 @@ void ipu0Interrupt()
|
|||
|
||||
if (g_nDMATransfer.FIREINT0)
|
||||
{
|
||||
g_nDMATransfer.FIREINT0 = 0;
|
||||
g_nDMATransfer.FIREINT0 = false;
|
||||
hwIntcIrq(INTC_IPU);
|
||||
}
|
||||
|
||||
if (g_nDMATransfer.GIFSTALL)
|
||||
{
|
||||
// gif
|
||||
g_nDMATransfer.GIFSTALL = 0;
|
||||
g_nDMATransfer.GIFSTALL = false;
|
||||
if (gif->chcr.STR) GIFdma();
|
||||
}
|
||||
|
||||
if (g_nDMATransfer.VIFSTALL)
|
||||
{
|
||||
// vif
|
||||
g_nDMATransfer.VIFSTALL = 0;
|
||||
g_nDMATransfer.VIFSTALL = false;
|
||||
if (vif1ch->chcr.STR) dmaVIF1();
|
||||
}
|
||||
|
||||
if (g_nDMATransfer.SIFSTALL)
|
||||
{
|
||||
// sif
|
||||
g_nDMATransfer.SIFSTALL = 0;
|
||||
g_nDMATransfer.SIFSTALL = false;
|
||||
|
||||
// Not totally sure whether this needs to be done or not, so I'm
|
||||
// leaving it commented out for the moment.
|
||||
|
|
@ -1752,10 +1755,10 @@ void ipu0Interrupt()
|
|||
|
||||
if (g_nDMATransfer.TIE0)
|
||||
{
|
||||
g_nDMATransfer.TIE0 = 0;
|
||||
g_nDMATransfer.TIE0 = false;
|
||||
}
|
||||
|
||||
ipu0dma->chcr.STR = 0;
|
||||
ipu0dma->chcr.STR = false;
|
||||
hwDmacIrq(DMAC_FROM_IPU);
|
||||
}
|
||||
|
||||
|
|
@ -1766,13 +1769,13 @@ IPU_FORCEINLINE void ipu1Interrupt()
|
|||
if (g_nDMATransfer.FIREINT1)
|
||||
{
|
||||
hwIntcIrq(INTC_IPU);
|
||||
g_nDMATransfer.FIREINT1 = 0;
|
||||
g_nDMATransfer.FIREINT1 = false;
|
||||
}
|
||||
|
||||
if (g_nDMATransfer.TIE1)
|
||||
g_nDMATransfer.TIE1 = 0;
|
||||
g_nDMATransfer.TIE1 = false;
|
||||
else
|
||||
ipu1dma->chcr.STR = 0;
|
||||
ipu1dma->chcr.STR = false;
|
||||
|
||||
hwDmacIrq(DMAC_TO_IPU);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -76,6 +76,17 @@ union tIPU_CTRL {
|
|||
u32 BUSY : 1; // Busy
|
||||
};
|
||||
u32 _u32;
|
||||
|
||||
tIPU_CTRL( u32 val ) { _u32 = val; }
|
||||
|
||||
// CTRL = the first 16 bits of ctrl [0x8000ffff], + value for the next 16 bits,
|
||||
// minus the reserved bits. (18-19; 27-29) [0x47f30000]
|
||||
void write(u32 value) { _u32 = (value & 0x47f30000) | (_u32 & 0x8000ffff); }
|
||||
|
||||
bool test(u32 flags) { return !!(_u32 & flags); }
|
||||
void set_flags(u32 flags) { _u32 |= flags; }
|
||||
void clear_flags(u32 flags) { _u32 &= ~flags; }
|
||||
void reset() { _u32 = 0; }
|
||||
};
|
||||
|
||||
struct tIPU_BP {
|
||||
|
|
@ -104,11 +115,14 @@ union tIPU_CMD_IDEC
|
|||
u32 cmd : 4;
|
||||
};
|
||||
|
||||
u32 value;
|
||||
u32 _u32;
|
||||
|
||||
tIPU_CMD_IDEC( u32 val ) : value( val )
|
||||
{
|
||||
}
|
||||
tIPU_CMD_IDEC( u32 val ) { _u32 = val; }
|
||||
|
||||
bool test(u32 flags) { return !!(_u32 & flags); }
|
||||
void set_flags(u32 flags) { _u32 |= flags; }
|
||||
void clear_flags(u32 flags) { _u32 &= ~flags; }
|
||||
void reset() { _u32 = 0; }
|
||||
};
|
||||
|
||||
union tIPU_CMD_BDEC
|
||||
|
|
@ -124,11 +138,14 @@ union tIPU_CMD_BDEC
|
|||
u32 MBI : 1;
|
||||
u32 cmd : 4;
|
||||
};
|
||||
u32 value;
|
||||
u32 _u32;
|
||||
|
||||
tIPU_CMD_BDEC( u32 val ) : value( val )
|
||||
{
|
||||
}
|
||||
tIPU_CMD_BDEC( u32 val ) { _u32 = val; }
|
||||
|
||||
bool test(u32 flags) { return !!(_u32 & flags); }
|
||||
void set_flags(u32 flags) { _u32 |= flags; }
|
||||
void clear_flags(u32 flags) { _u32 &= ~flags; }
|
||||
void reset() { _u32 = 0; }
|
||||
};
|
||||
|
||||
union tIPU_CMD_CSC
|
||||
|
|
@ -141,28 +158,38 @@ union tIPU_CMD_CSC
|
|||
u32 OFM : 1;
|
||||
u32 cmd : 4;
|
||||
};
|
||||
u32 value;
|
||||
u32 _u32;
|
||||
|
||||
tIPU_CMD_CSC( u32 val ) : value( val )
|
||||
{
|
||||
}
|
||||
tIPU_CMD_CSC( u32 val ){ _u32 = val; }
|
||||
|
||||
bool test(u32 flags) { return !!(_u32 & flags); }
|
||||
void set_flags(u32 flags) { _u32 |= flags; }
|
||||
void clear_flags(u32 flags) { _u32 &= ~flags; }
|
||||
void reset() { _u32 = 0; }
|
||||
};
|
||||
|
||||
union tIPU_DMA
|
||||
{
|
||||
struct
|
||||
{
|
||||
u32 GIFSTALL : 1;
|
||||
u32 TIE0 :1;
|
||||
u32 TIE1 : 1;
|
||||
u32 ACTV1 : 1;
|
||||
u32 DOTIE1 : 1;
|
||||
u32 FIREINT0 : 1;
|
||||
u32 FIREINT1 : 1;
|
||||
u32 VIFSTALL : 1;
|
||||
u32 SIFSTALL : 1;
|
||||
bool GIFSTALL : 1;
|
||||
bool TIE0 :1;
|
||||
bool TIE1 : 1;
|
||||
bool ACTV1 : 1;
|
||||
bool DOTIE1 : 1;
|
||||
bool FIREINT0 : 1;
|
||||
bool FIREINT1 : 1;
|
||||
bool VIFSTALL : 1;
|
||||
bool SIFSTALL : 1;
|
||||
};
|
||||
u32 _u32;
|
||||
|
||||
tIPU_DMA( u32 val ){ _u32 = val; }
|
||||
|
||||
bool test(u32 flags) { return !!(_u32 & flags); }
|
||||
void set_flags(u32 flags) { _u32 |= flags; }
|
||||
void clear_flags(u32 flags) { _u32 &= ~flags; }
|
||||
void reset() { _u32 = 0; }
|
||||
};
|
||||
|
||||
enum SCE_IPU
|
||||
|
|
|
|||
|
|
@ -254,7 +254,7 @@ void SPRFROMinterrupt()
|
|||
}
|
||||
}
|
||||
if (!spr0finished) return;
|
||||
spr0->chcr.STR = 0;
|
||||
spr0->chcr.STR = false;
|
||||
hwDmacIrq(DMAC_FROM_SPR);
|
||||
}
|
||||
|
||||
|
|
@ -429,7 +429,7 @@ void SPRTOinterrupt()
|
|||
{
|
||||
_dmaSPR1();
|
||||
if (!spr1finished) return;
|
||||
spr1->chcr.STR = 0;
|
||||
spr1->chcr.STR = false;
|
||||
hwDmacIrq(DMAC_TO_SPR);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -422,13 +422,13 @@ __forceinline void sif1Interrupt()
|
|||
__forceinline void EEsif0Interrupt()
|
||||
{
|
||||
hwDmacIrq(DMAC_SIF0);
|
||||
sif0dma->chcr.STR = 0;
|
||||
sif0dma->chcr.STR = false;
|
||||
}
|
||||
|
||||
__forceinline void EEsif1Interrupt()
|
||||
{
|
||||
hwDmacIrq(DMAC_SIF1);
|
||||
sif1dma->chcr.STR = 0;
|
||||
sif1dma->chcr.STR = false;
|
||||
}
|
||||
|
||||
__forceinline void dmaSIF0()
|
||||
|
|
@ -485,7 +485,7 @@ __forceinline void dmaSIF2()
|
|||
SIF_LOG("dmaSIF2 chcr = %lx, madr = %lx, qwc = %lx",
|
||||
sif2dma->chcr._u32, sif2dma->madr, sif2dma->qwc);
|
||||
|
||||
sif2dma->chcr.STR = 0;
|
||||
sif2dma->chcr.STR = false;
|
||||
hwDmacIrq(DMAC_SIF2);
|
||||
Console.WriteLn("*PCSX2*: dmaSIF2");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -117,7 +117,7 @@ namespace Tag
|
|||
UpperTransfer(tag, ptag);
|
||||
|
||||
// Set BEIS (BUSERR) in DMAC_STAT register
|
||||
dmacRegs->stat.BEIS = 1;
|
||||
dmacRegs->stat.BEIS = true;
|
||||
return false;
|
||||
}
|
||||
else
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ void vu0ResetRegs()
|
|||
{
|
||||
VU0.VI[REG_VPU_STAT].UL &= ~0xff; // stop vu0
|
||||
VU0.VI[REG_FBRST].UL &= ~0xff; // stop vu0
|
||||
vif0Regs->stat.VEW = 0;
|
||||
vif0Regs->stat.VEW = false;
|
||||
}
|
||||
|
||||
void VU0MI_XGKICK() {
|
||||
|
|
|
|||
|
|
@ -166,7 +166,7 @@ static void _vu0Exec(VURegs* VU)
|
|||
if( VU->ebit-- == 1 ) {
|
||||
_vuFlushAll(VU);
|
||||
VU0.VI[REG_VPU_STAT].UL&= ~0x1; /* E flag */
|
||||
vif0Regs->stat.VEW = 0;
|
||||
vif0Regs->stat.VEW = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ void vu1ResetRegs()
|
|||
{
|
||||
VU0.VI[REG_VPU_STAT].UL &= ~0xff00; // stop vu1
|
||||
VU0.VI[REG_FBRST].UL &= ~0xff00; // stop vu1
|
||||
vif1Regs->stat.VEW = 0;
|
||||
vif1Regs->stat.VEW = false;
|
||||
}
|
||||
|
||||
static int count;
|
||||
|
|
@ -55,7 +55,7 @@ void __fastcall vu1ExecMicro(u32 addr)
|
|||
|
||||
VU0.VI[REG_VPU_STAT].UL|= 0x100;
|
||||
VU0.VI[REG_VPU_STAT].UL&= ~0x7E000;
|
||||
vif1Regs->stat.VEW = 1;
|
||||
vif1Regs->stat.VEW = true;
|
||||
if (addr != -1) VU1.VI[REG_TPC].UL = addr;
|
||||
_vuExecMicroDebug(VU1);
|
||||
|
||||
|
|
|
|||
|
|
@ -159,7 +159,7 @@ static void _vu1Exec(VURegs* VU)
|
|||
if( VU->ebit-- == 1 ) {
|
||||
_vuFlushAll(VU);
|
||||
VU0.VI[REG_VPU_STAT].UL &= ~0x100;
|
||||
vif1Regs->stat.VEW = 0;
|
||||
vif1Regs->stat.VEW = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -582,7 +582,7 @@ void mfifoVIF1transfer(int qwc)
|
|||
|
||||
case TAG_REF: // Ref - Transfer QWC from ADDR field
|
||||
case TAG_REFS: // Refs - Transfer QWC from ADDR field (Stall Control)
|
||||
vif1ch->tadr =qwctag(vif1ch->tadr + 16); //Set TADR to next tag
|
||||
vif1ch->tadr = qwctag(vif1ch->tadr + 16); //Set TADR to next tag
|
||||
vif1.done = false;
|
||||
break;
|
||||
|
||||
|
|
@ -620,27 +620,27 @@ void vifMFIFOInterrupt()
|
|||
}
|
||||
else
|
||||
{
|
||||
vif1Regs->stat.VGW = 0;
|
||||
vif1Regs->stat.VGW = false;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if ((spr0->chcr.STR) && (spr0->qwc == 0))
|
||||
{
|
||||
spr0->chcr.STR = 0;
|
||||
spr0->chcr.STR = false;
|
||||
hwDmacIrq(DMAC_FROM_SPR);
|
||||
}
|
||||
|
||||
if (vif1.irq && vif1.tag.size == 0)
|
||||
{
|
||||
vif1Regs->stat.INT = 1;
|
||||
vif1Regs->stat.INT = true;
|
||||
hwIntcIrq(INTC_VIF1);
|
||||
--vif1.irq;
|
||||
|
||||
if (vif1Regs->stat.test(VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
|
||||
{
|
||||
vif1Regs->stat.FQC = 0; // FQC=0
|
||||
vif1ch->chcr.STR = 0;
|
||||
vif1ch->chcr.STR = false;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
|
@ -686,7 +686,7 @@ void vifMFIFOInterrupt()
|
|||
|
||||
vif1.done = 1;
|
||||
g_vifCycles = 0;
|
||||
vif1ch->chcr.STR = 0;
|
||||
vif1ch->chcr.STR = false;
|
||||
hwDmacIrq(DMAC_VIF1);
|
||||
VIF_LOG("vif mfifo dma end");
|
||||
|
||||
|
|
|
|||
62
pcsx2/Vif.h
62
pcsx2/Vif.h
|
|
@ -86,48 +86,66 @@ enum vif_status
|
|||
//
|
||||
union tVIF_STAT {
|
||||
struct {
|
||||
u32 VPS : 2; // Vif(0/1) status.
|
||||
u32 VEW : 1; // E-bit wait (1 - wait, 0 - don't wait)
|
||||
u32 VGW : 1; // Status waiting for the end of gif transfer (Vif1 only)
|
||||
u32 VPS : 2; // Vif(0/1) status; 00 - idle, 01 - waiting for data following vifcode, 10 - decoding vifcode, 11 - decompressing/trasferring data follwing vifcode.
|
||||
bool VEW : 1; // E-bit wait (1 - wait, 0 - don't wait)
|
||||
bool VGW : 1; // Status waiting for the end of gif transfer (Vif1 only)
|
||||
u32 reserved : 2;
|
||||
u32 MRK : 1; // Mark Detect
|
||||
u32 DBF : 1; // Double Buffer Flag
|
||||
u32 VSS : 1; // Stopped by STOP
|
||||
u32 VFS : 1; // Stopped by ForceBreak
|
||||
u32 VIS : 1; // Vif Interrupt Stall
|
||||
u32 INT : 1; // Intereupt by the i bit.
|
||||
u32 ER0 : 1; // DmaTag Mismatch error.
|
||||
u32 ER1 : 1; // VifCode error
|
||||
bool MRK : 1; // Mark Detect
|
||||
bool DBF : 1; // Double Buffer Flag
|
||||
bool VSS : 1; // Stopped by STOP
|
||||
bool VFS : 1; // Stopped by ForceBreak
|
||||
bool VIS : 1; // Vif Interrupt Stall
|
||||
bool INT : 1; // Intereupt by the i bit.
|
||||
bool ER0 : 1; // DmaTag Mismatch error.
|
||||
bool ER1 : 1; // VifCode error
|
||||
u32 reserved2 : 9;
|
||||
u32 FDR : 1; // VIF/FIFO transfer direction. (0 - memory -> Vif, 1 - Vif -> memory)
|
||||
bool FDR : 1; // VIF/FIFO transfer direction. (false - memory -> Vif, true - Vif -> memory)
|
||||
u32 FQC : 5; // Amount of data. Up to 8 qwords on Vif0, 16 on Vif1.
|
||||
};
|
||||
u32 _u32;
|
||||
|
||||
tVIF_STAT(u32 val) { _u32 = val; }
|
||||
|
||||
bool test(u32 flags) { return !!(_u32 & flags); }
|
||||
void set(u32 flags) { _u32 |= flags; }
|
||||
void clear(u32 flags) { _u32 &= ~flags; }
|
||||
void set_flags(u32 flags) { _u32 |= flags; }
|
||||
void clear_flags(u32 flags) { _u32 &= ~flags; }
|
||||
void reset() { _u32 = 0; }
|
||||
};
|
||||
|
||||
union tVIF_FBRST {
|
||||
struct {
|
||||
u32 RST : 1; // Resets Vif(0/1) when written.
|
||||
u32 FBK : 1; // Causes a Forcebreak to Vif((0/1) when 1 is written. (Stall)
|
||||
u32 STP : 1; // Stops after the end of the Vifcode in progress when written. (Stall)
|
||||
u32 STC : 1; // Cancels the Vif(0/1) stall and clears Vif Stats VSS, VFS, VIS, INT, ER0 & ER1.
|
||||
bool RST : 1; // Resets Vif(0/1) when written.
|
||||
bool FBK : 1; // Causes a Forcebreak to Vif((0/1) when true. (Stall)
|
||||
bool STP : 1; // Stops after the end of the Vifcode in progress when true. (Stall)
|
||||
bool STC : 1; // Cancels the Vif(0/1) stall and clears Vif Stats VSS, VFS, VIS, INT, ER0 & ER1.
|
||||
u32 reserved : 28;
|
||||
};
|
||||
u32 _u32;
|
||||
|
||||
tVIF_FBRST(u32 val) { _u32 = val; }
|
||||
|
||||
bool test(u32 flags) { return !!(_u32 & flags); }
|
||||
void set_flags(u32 flags) { _u32 |= flags; }
|
||||
void clear_flags(u32 flags) { _u32 &= ~flags; }
|
||||
void reset() { _u32 = 0; }
|
||||
};
|
||||
|
||||
union tVIF_ERR {
|
||||
struct {
|
||||
u32 MII : 1; // Masks Stat INT.
|
||||
u32 ME0 : 1; // Masks Stat Err0.
|
||||
u32 ME1 : 1; // Masks Stat Err1.
|
||||
bool MII : 1; // Masks Stat INT.
|
||||
bool ME0 : 1; // Masks Stat Err0.
|
||||
bool ME1 : 1; // Masks Stat Err1.
|
||||
u32 reserved : 29;
|
||||
};
|
||||
u32 _u32;
|
||||
|
||||
tVIF_ERR(u32 val) { _u32 = val; }
|
||||
|
||||
void write(u32 val) { _u32 = val; }
|
||||
bool test(u32 flags) { return !!(_u32 & flags); }
|
||||
void set_flags(u32 flags) { _u32 |= flags; }
|
||||
void clear_flags(u32 flags) { _u32 &= ~flags; }
|
||||
void reset() { _u32 = 0; }
|
||||
};
|
||||
|
||||
struct vifCycle {
|
||||
|
|
@ -138,7 +156,7 @@ struct vifCycle {
|
|||
struct VIFregisters {
|
||||
tVIF_STAT stat;
|
||||
u32 pad0[3];
|
||||
u32 fbrst;
|
||||
tVIF_FBRST fbrst;
|
||||
u32 pad1[3];
|
||||
tVIF_ERR err;
|
||||
u32 pad2[3];
|
||||
|
|
|
|||
|
|
@ -309,7 +309,7 @@ static void Vif0CMDSTMod() // STMOD
|
|||
static void Vif0CMDMark() // MARK
|
||||
{
|
||||
vif0Regs->mark = (u16)vif0Regs->code;
|
||||
vif0Regs->stat.MRK = 1;
|
||||
vif0Regs->stat.MRK = true;
|
||||
vif0.cmd &= ~0x7f;
|
||||
}
|
||||
|
||||
|
|
@ -358,7 +358,7 @@ static void Vif0CMDNull() // invalid opcode
|
|||
if (!(vif0Regs->err.ME1)) //Ignore vifcode and tag mismatch error
|
||||
{
|
||||
Console.WriteLn("UNKNOWN VifCmd: %x", vif0.cmd);
|
||||
vif0Regs->stat.ER1 = 1;
|
||||
vif0Regs->stat.ER1 = true;
|
||||
vif0.irq++;
|
||||
}
|
||||
vif0.cmd &= ~0x7f;
|
||||
|
|
@ -410,7 +410,7 @@ int VIF0transfer(u32 *data, int size, int istag)
|
|||
if (!(vif0Regs->err.ME1)) //Ignore vifcode and tag mismatch error
|
||||
{
|
||||
Console.WriteLn("UNKNOWN VifCmd: %x", vif0.cmd);
|
||||
vif0Regs->stat.ER1 = 1;
|
||||
vif0Regs->stat.ER1 = true;
|
||||
vif0.irq++;
|
||||
}
|
||||
vif0.cmd = 0;
|
||||
|
|
@ -449,7 +449,7 @@ int VIF0transfer(u32 *data, int size, int istag)
|
|||
{
|
||||
vif0.vifstalled = true;
|
||||
|
||||
if (((vif0Regs->code >> 24) & 0x7f) != 0x7) vif0Regs->stat.VIS = 1;
|
||||
if (((vif0Regs->code >> 24) & 0x7f) != 0x7) vif0Regs->stat.VIS = true;
|
||||
//else Console.WriteLn("VIF0 IRQ on MARK");
|
||||
|
||||
// spiderman doesn't break on qw boundaries
|
||||
|
|
@ -465,7 +465,7 @@ int VIF0transfer(u32 *data, int size, int istag)
|
|||
return -2;
|
||||
}
|
||||
|
||||
vif0Regs->stat.VPS = 0; //Vif goes idle as the stall happened between commands;
|
||||
vif0Regs->stat.VPS = VPS_IDLE; //Vif goes idle as the stall happened between commands;
|
||||
if (vif0.cmd) vif0Regs->stat.VPS |= VPS_WAITING; //Otherwise we wait for the data
|
||||
|
||||
if (!istag)
|
||||
|
|
@ -552,14 +552,14 @@ void vif0Interrupt()
|
|||
|
||||
if (vif0.irq && (vif0.tag.size == 0))
|
||||
{
|
||||
vif0Regs->stat.INT = 1;
|
||||
vif0Regs->stat.INT = true;
|
||||
hwIntcIrq(VIF0intc);
|
||||
--vif0.irq;
|
||||
|
||||
if (vif0Regs->stat.test(VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS))
|
||||
{
|
||||
vif0Regs->stat.FQC = 0; // FQC=0
|
||||
vif0ch->chcr.STR = 0;
|
||||
vif0Regs->stat.FQC = 0;
|
||||
vif0ch->chcr.STR = false;
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -598,9 +598,9 @@ void vif0Interrupt()
|
|||
if (vif0ch->qwc > 0) Console.WriteLn("VIF0 Ending with QWC left");
|
||||
if (vif0.cmd != 0) Console.WriteLn("vif0.cmd still set %x", vif0.cmd);
|
||||
|
||||
vif0ch->chcr.STR = 0;
|
||||
vif0ch->chcr.STR = false;
|
||||
hwDmacIrq(DMAC_VIF0);
|
||||
vif0Regs->stat.FQC = 0; // FQC=0
|
||||
vif0Regs->stat.FQC = 0;
|
||||
}
|
||||
|
||||
// Vif0 Data Transfer Table
|
||||
|
|
@ -678,7 +678,7 @@ void vif0Write32(u32 mem, u32 value)
|
|||
VIF_LOG("VIF0_MARK write32 0x%8.8x", value);
|
||||
|
||||
/* Clear mark flag in VIF0_STAT and set mark with 'value' */
|
||||
vif0Regs->stat.MRK = 0;
|
||||
vif0Regs->stat.MRK = false;
|
||||
vif0Regs->mark = value;
|
||||
break;
|
||||
|
||||
|
|
@ -695,16 +695,16 @@ void vif0Write32(u32 mem, u32 value)
|
|||
psHu64(VIF0_FIFO) = 0;
|
||||
psHu64(VIF0_FIFO + 8) = 0;
|
||||
vif0.done = true;
|
||||
vif0Regs->err._u32 = 0;
|
||||
vif0Regs->stat.clear(VIF0_STAT_FQC | VIF0_STAT_INT | VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS | VIF0_STAT_VPS); // FQC=0
|
||||
vif0Regs->err.reset();
|
||||
vif0Regs->stat.clear_flags(VIF0_STAT_FQC | VIF0_STAT_INT | VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS | VIF0_STAT_VPS); // FQC=0
|
||||
}
|
||||
|
||||
if (value & 0x2) // Forcebreak Vif,
|
||||
{
|
||||
/* I guess we should stop the VIF dma here, but not 100% sure (linuz) */
|
||||
cpuRegs.interrupt &= ~1; //Stop all vif0 DMA's
|
||||
vif0Regs->stat.VFS = 1;
|
||||
vif0Regs->stat.VPS = 0;
|
||||
vif0Regs->stat.VFS = true;
|
||||
vif0Regs->stat.VPS = VPS_IDLE;
|
||||
vif0.vifstalled = true;
|
||||
Console.WriteLn("vif0 force break");
|
||||
}
|
||||
|
|
@ -713,8 +713,8 @@ void vif0Write32(u32 mem, u32 value)
|
|||
{
|
||||
// Not completely sure about this, can't remember what game, used this, but 'draining' the VIF helped it, instead of
|
||||
// just stoppin the VIF (linuz).
|
||||
vif0Regs->stat.VSS = 1;
|
||||
vif0Regs->stat.VPS = 0;
|
||||
vif0Regs->stat.VSS = true;
|
||||
vif0Regs->stat.VPS = VPS_IDLE;
|
||||
vif0.vifstalled = true;
|
||||
}
|
||||
|
||||
|
|
@ -726,7 +726,7 @@ void vif0Write32(u32 mem, u32 value)
|
|||
if (vif0Regs->stat.test(VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS))
|
||||
cancel = true;
|
||||
|
||||
vif0Regs->stat.clear(VIF0_STAT_VSS | VIF0_STAT_VFS | VIF0_STAT_VIS |
|
||||
vif0Regs->stat.clear_flags(VIF0_STAT_VSS | VIF0_STAT_VFS | VIF0_STAT_VIS |
|
||||
VIF0_STAT_INT | VIF0_STAT_ER0 | VIF0_STAT_ER1);
|
||||
if (cancel)
|
||||
{
|
||||
|
|
@ -740,7 +740,7 @@ void vif0Write32(u32 mem, u32 value)
|
|||
else
|
||||
_VIF0chain();
|
||||
|
||||
vif0ch->chcr.STR = 1;
|
||||
vif0ch->chcr.STR = true;
|
||||
CPU_INT(0, g_vifCycles); // Gets the timing right - Flatout
|
||||
}
|
||||
}
|
||||
|
|
@ -752,7 +752,7 @@ void vif0Write32(u32 mem, u32 value)
|
|||
VIF_LOG("VIF0_ERR write32 0x%8.8x", value);
|
||||
|
||||
/* Set VIF0_ERR with 'value' */
|
||||
vif0Regs->err._u32 = value;
|
||||
vif0Regs->err.write(value);
|
||||
break;
|
||||
|
||||
case VIF0_R0:
|
||||
|
|
@ -789,7 +789,7 @@ void vif0Reset()
|
|||
psHu64(VIF0_FIFO) = 0;
|
||||
psHu64(VIF0_FIFO + 8) = 0;
|
||||
|
||||
vif0Regs->stat.VPS = 0;
|
||||
vif0Regs->stat.VPS = VPS_IDLE;
|
||||
vif0Regs->stat.FQC = 0;
|
||||
|
||||
vif0.done = true;
|
||||
|
|
|
|||
|
|
@ -242,13 +242,13 @@ static int __fastcall Vif1TransDirectHL(u32 *data)
|
|||
{
|
||||
if (gif->chcr.STR && (!vif1Regs->mskpath3 && (Path3progress == IMAGE_MODE))) //PATH3 is in image mode, so wait for end of transfer
|
||||
{
|
||||
vif1Regs->stat.VGW = 1;
|
||||
vif1Regs->stat.VGW = true;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
gifRegs->stat.APATH |= GIF_APATH2;
|
||||
gifRegs->stat.OPH = 1;
|
||||
gifRegs->stat.OPH = true;
|
||||
|
||||
|
||||
if (splitptr > 0) //Leftover data from the last packet, filling the rest and sending to the GS
|
||||
|
|
@ -297,7 +297,7 @@ static int __fastcall Vif1TransDirectHL(u32 *data)
|
|||
}
|
||||
else
|
||||
{
|
||||
gifRegs->stat.clear(GIF_STAT_APATH2 | GIF_STAT_OPH);
|
||||
gifRegs->stat.clear_flags(GIF_STAT_APATH2 | GIF_STAT_OPH);
|
||||
ret = vif1.tag.size;
|
||||
vif1.tag.size = 0;
|
||||
vif1.cmd = 0;
|
||||
|
|
@ -388,7 +388,7 @@ static void Vif1CMDSTCycl() // STCYCL
|
|||
static void Vif1CMDOffset() // OFFSET
|
||||
{
|
||||
vif1Regs->ofst = vif1Regs->code & 0x3ff;
|
||||
vif1Regs->stat.DBF = 0;
|
||||
vif1Regs->stat.DBF = false;
|
||||
vif1Regs->tops = vif1Regs->base;
|
||||
vif1.cmd &= ~0x7f;
|
||||
}
|
||||
|
|
@ -420,13 +420,13 @@ void Vif1MskPath3() // MSKPATH3
|
|||
|
||||
if (vif1Regs->mskpath3)
|
||||
{
|
||||
gifRegs->stat.M3P = 1;
|
||||
gifRegs->stat.M3P = true;
|
||||
}
|
||||
else
|
||||
{
|
||||
//Let the Gif know it can transfer again (making sure any vif stall isnt unset prematurely)
|
||||
Path3progress = TRANSFER_MODE;
|
||||
gifRegs->stat.IMT = 0;
|
||||
gifRegs->stat.IMT = false;
|
||||
CPU_INT(2, 4);
|
||||
}
|
||||
|
||||
|
|
@ -451,7 +451,7 @@ static void Vif1CMDMskPath3() // MSKPATH3
|
|||
static void Vif1CMDMark() // MARK
|
||||
{
|
||||
vif1Regs->mark = (u16)vif1Regs->code;
|
||||
vif1Regs->stat.MRK = 1;
|
||||
vif1Regs->stat.MRK = true;
|
||||
vif1.cmd &= ~0x7f;
|
||||
}
|
||||
|
||||
|
|
@ -464,7 +464,7 @@ static void Vif1CMDFlush() // FLUSH/E/A
|
|||
// Gif is already transferring so wait for it.
|
||||
if (((Path3progress != STOPPED_MODE) || !vif1Regs->mskpath3) && gif->chcr.STR)
|
||||
{
|
||||
vif1Regs->stat.VGW = 1;
|
||||
vif1Regs->stat.VGW = true;
|
||||
CPU_INT(2, 4);
|
||||
}
|
||||
}
|
||||
|
|
@ -526,7 +526,7 @@ static void Vif1CMDNull() // invalid opcode
|
|||
if (!(vif1Regs->err.ME1)) //Ignore vifcode and tag mismatch error
|
||||
{
|
||||
Console.WriteLn("UNKNOWN VifCmd: %x\n", vif1.cmd);
|
||||
vif1Regs->stat.ER1 = 1;
|
||||
vif1Regs->stat.ER1 = true;
|
||||
vif1.irq++;
|
||||
}
|
||||
vif1.cmd = 0;
|
||||
|
|
@ -624,7 +624,7 @@ int VIF1transfer(u32 *data, int size, int istag)
|
|||
if (!(vif0Regs->err.ME1)) //Ignore vifcode and tag mismatch error
|
||||
{
|
||||
Console.WriteLn("UNKNOWN VifCmd: %x", vif1.cmd);
|
||||
vif1Regs->stat.ER1 = 1;
|
||||
vif1Regs->stat.ER1 = true;
|
||||
vif1.irq++;
|
||||
}
|
||||
vif1.cmd = 0;
|
||||
|
|
@ -664,7 +664,7 @@ int VIF1transfer(u32 *data, int size, int istag)
|
|||
{
|
||||
vif1.vifstalled = true;
|
||||
|
||||
if (((vif1Regs->code >> 24) & 0x7f) != 0x7) vif1Regs->stat.VIS = 1; // Note: commenting this out fixes WALL-E
|
||||
if (((vif1Regs->code >> 24) & 0x7f) != 0x7) vif1Regs->stat.VIS = true; // Note: commenting this out fixes WALL-E
|
||||
|
||||
if (vif1ch->qwc == 0 && (vif1.irqoffset == 0 || istag == 1)) vif1.inprogress &= ~0x1;
|
||||
|
||||
|
|
@ -680,7 +680,7 @@ int VIF1transfer(u32 *data, int size, int istag)
|
|||
return -2;
|
||||
}
|
||||
|
||||
vif1Regs->stat.VPS = 0; //Vif goes idle as the stall happened between commands;
|
||||
vif1Regs->stat.VPS = VPS_IDLE; //Vif goes idle as the stall happened between commands;
|
||||
if (vif1.cmd) vif1Regs->stat.VPS = VPS_WAITING; //Otherwise we wait for the data
|
||||
|
||||
if (!istag)
|
||||
|
|
@ -709,7 +709,7 @@ void vif1TransferFromMemory()
|
|||
if (pMem == NULL) //Is vif0ptag empty?
|
||||
{
|
||||
Console.WriteLn("Vif1 Tag BUSERR");
|
||||
dmacRegs->stat.BEIS = 1; //Bus Error
|
||||
dmacRegs->stat.BEIS = true; //Bus Error
|
||||
vif1Regs->stat.FQC = 0;
|
||||
|
||||
vif1ch->qwc = 0;
|
||||
|
|
@ -887,7 +887,7 @@ __forceinline void vif1Interrupt()
|
|||
}
|
||||
else
|
||||
{
|
||||
vif1Regs->stat.VGW = 0;
|
||||
vif1Regs->stat.VGW = false;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -895,7 +895,7 @@ __forceinline void vif1Interrupt()
|
|||
|
||||
if (vif1.irq && vif1.tag.size == 0)
|
||||
{
|
||||
vif1Regs->stat.INT = 1;
|
||||
vif1Regs->stat.INT = true;
|
||||
hwIntcIrq(VIF1intc);
|
||||
--vif1.irq;
|
||||
if (vif1Regs->stat.test(VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
|
||||
|
|
@ -903,7 +903,7 @@ __forceinline void vif1Interrupt()
|
|||
vif1Regs->stat.FQC = 0;
|
||||
|
||||
// One game doesn't like vif stalling at end, can't remember what. Spiderman isn't keen on it tho
|
||||
vif1ch->chcr.STR = 0;
|
||||
vif1ch->chcr.STR = false;
|
||||
return;
|
||||
}
|
||||
else if ((vif1ch->qwc > 0) || (vif1.irqoffset > 0))
|
||||
|
|
@ -947,8 +947,8 @@ __forceinline void vif1Interrupt()
|
|||
if (vif1.cmd != 0) Console.WriteLn("vif1.cmd still set %x tag size %x", vif1.cmd, vif1.tag.size);
|
||||
#endif
|
||||
|
||||
vif1Regs->stat.VPS = 0; //Vif goes idle as the stall happened between commands;
|
||||
vif1ch->chcr.STR = 0;
|
||||
vif1Regs->stat.VPS = VPS_IDLE; //Vif goes idle as the stall happened between commands;
|
||||
vif1ch->chcr.STR = false;
|
||||
g_vifCycles = 0;
|
||||
hwDmacIrq(DMAC_VIF1);
|
||||
|
||||
|
|
@ -963,7 +963,7 @@ void dmaVIF1()
|
|||
{
|
||||
VIF_LOG("dmaVIF1 chcr = %lx, madr = %lx, qwc = %lx\n"
|
||||
" tadr = %lx, asr0 = %lx, asr1 = %lx",
|
||||
vif1ch->chcr, vif1ch->madr, vif1ch->qwc,
|
||||
vif1ch->chcr._u32, vif1ch->madr, vif1ch->qwc,
|
||||
vif1ch->tadr, vif1ch->asr0, vif1ch->asr1);
|
||||
|
||||
g_vifCycles = 0;
|
||||
|
|
@ -973,7 +973,7 @@ void dmaVIF1()
|
|||
{
|
||||
//Console.WriteLn("VIFMFIFO\n");
|
||||
// Test changed because the Final Fantasy 12 opening somehow has the tag in *Undefined* mode, which is not in the documentation that I saw.
|
||||
if (vif1ch->chcr.MOD == NORMAL_MODE) Console.WriteLn("MFIFO mode is normal (which isn't normal here)! %x", vif1ch->chcr);
|
||||
if (vif1ch->chcr.MOD == NORMAL_MODE) Console.WriteLn("MFIFO mode is normal (which isn't normal here)! %x", vif1ch->chcr._u32);
|
||||
vifMFIFOInterrupt();
|
||||
return;
|
||||
}
|
||||
|
|
@ -1004,7 +1004,7 @@ void dmaVIF1()
|
|||
if (vif1.dmamode != VIF_NORMAL_FROM_MEM_MODE)
|
||||
vif1Regs->stat.FQC = 0x10;
|
||||
else
|
||||
vif1Regs->stat.set(min((u16)16, vif1ch->qwc) << 24);
|
||||
vif1Regs->stat.set_flags(min((u16)16, vif1ch->qwc) << 24);
|
||||
|
||||
// Chain Mode
|
||||
vif1.done = false;
|
||||
|
|
@ -1019,7 +1019,7 @@ void vif1Write32(u32 mem, u32 value)
|
|||
VIF_LOG("VIF1_MARK write32 0x%8.8x", value);
|
||||
|
||||
/* Clear mark flag in VIF1_STAT and set mark with 'value' */
|
||||
vif1Regs->stat.MRK = 0;
|
||||
vif1Regs->stat.MRK = false;
|
||||
vif1Regs->mark = value;
|
||||
break;
|
||||
|
||||
|
|
@ -1038,20 +1038,20 @@ void vif1Write32(u32 mem, u32 value)
|
|||
if(vif1Regs->mskpath3)
|
||||
{
|
||||
vif1Regs->mskpath3 = 0;
|
||||
gifRegs->stat.IMT = 0;
|
||||
gifRegs->stat.IMT = false;
|
||||
if (gif->chcr.STR) CPU_INT(2, 4);
|
||||
}
|
||||
|
||||
vif1Regs->err._u32 = 0;
|
||||
vif1Regs->err.reset();
|
||||
vif1.inprogress = 0;
|
||||
vif1Regs->stat.clear(VIF1_STAT_FQC | VIF1_STAT_FDR | VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS | VIF1_STAT_VPS); // FQC=0
|
||||
vif1Regs->stat.clear_flags(VIF1_STAT_FQC | VIF1_STAT_FDR | VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS | VIF1_STAT_VPS); // FQC=0
|
||||
}
|
||||
|
||||
if (value & 0x2) // Forcebreak Vif.
|
||||
{
|
||||
/* I guess we should stop the VIF dma here, but not 100% sure (linuz) */
|
||||
vif1Regs->stat.VFS = 1;
|
||||
vif1Regs->stat.VPS = 0;
|
||||
vif1Regs->stat.VFS = true;
|
||||
vif1Regs->stat.VPS = VPS_IDLE;
|
||||
cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's
|
||||
vif1.vifstalled = true;
|
||||
Console.WriteLn("vif1 force break");
|
||||
|
|
@ -1061,8 +1061,8 @@ void vif1Write32(u32 mem, u32 value)
|
|||
{
|
||||
// Not completely sure about this, can't remember what game used this, but 'draining' the VIF helped it, instead of
|
||||
// just stoppin the VIF (linuz).
|
||||
vif1Regs->stat.VSS = 1;
|
||||
vif1Regs->stat.VPS = 0;
|
||||
vif1Regs->stat.VSS = true;
|
||||
vif1Regs->stat.VPS = VPS_IDLE;
|
||||
cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's
|
||||
vif1.vifstalled = true;
|
||||
}
|
||||
|
|
@ -1077,7 +1077,7 @@ void vif1Write32(u32 mem, u32 value)
|
|||
cancel = true;
|
||||
}
|
||||
|
||||
vif1Regs->stat.clear(VIF1_STAT_VSS | VIF1_STAT_VFS | VIF1_STAT_VIS |
|
||||
vif1Regs->stat.clear_flags(VIF1_STAT_VSS | VIF1_STAT_VFS | VIF1_STAT_VIS |
|
||||
VIF1_STAT_INT | VIF1_STAT_ER0 | VIF1_STAT_ER1);
|
||||
|
||||
if (cancel)
|
||||
|
|
@ -1101,7 +1101,7 @@ void vif1Write32(u32 mem, u32 value)
|
|||
break;
|
||||
}
|
||||
|
||||
vif1ch->chcr.STR = 1;
|
||||
vif1ch->chcr.STR = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1111,7 +1111,7 @@ void vif1Write32(u32 mem, u32 value)
|
|||
VIF_LOG("VIF1_ERR write32 0x%8.8x", value);
|
||||
|
||||
/* Set VIF1_ERR with 'value' */
|
||||
vif1Regs->err._u32 = value;
|
||||
vif1Regs->err.write(value);
|
||||
break;
|
||||
|
||||
case VIF1_STAT: // STAT
|
||||
|
|
@ -1129,7 +1129,8 @@ void vif1Write32(u32 mem, u32 value)
|
|||
}
|
||||
#endif
|
||||
|
||||
vif1Regs->stat._u32 = (vif1Regs->stat._u32 & ~VIF1_STAT_FDR) | (value & VIF1_STAT_FDR);
|
||||
vif1Regs->stat.FDR = (value & VIF1_STAT_FDR);
|
||||
//vif1Regs->stat._u32 = (vif1Regs->stat._u32 & ~VIF1_STAT_FDR) | (value & VIF1_STAT_FDR);
|
||||
if (vif1Regs->stat.FDR)
|
||||
{
|
||||
vif1Regs->stat.FQC = 1; // Hack but it checks this is true before transfer? (fatal frame)
|
||||
|
|
@ -1182,7 +1183,7 @@ void vif1Reset()
|
|||
psHu64(VIF1_FIFO) = 0;
|
||||
psHu64(VIF1_FIFO + 8) = 0;
|
||||
|
||||
vif1Regs->stat.VPS = 0;
|
||||
vif1Regs->stat.VPS = VPS_IDLE;
|
||||
vif1Regs->stat.FQC = 0; // FQC=0
|
||||
|
||||
vif1.done = true;
|
||||
|
|
|
|||
|
|
@ -830,13 +830,13 @@ template<const u32 VIFdmanum> void vuExecMicro(u32 addr)
|
|||
{
|
||||
/* it is, so set tops with base, and clear the stat DBF flag */
|
||||
VU->vifRegs->tops = VU->vifRegs->base;
|
||||
VU->vifRegs->stat.DBF = 0;
|
||||
VU->vifRegs->stat.DBF = false;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* it is not, so set tops with base + offset, and set stat DBF flag */
|
||||
VU->vifRegs->tops = VU->vifRegs->base + VU->vifRegs->ofst;
|
||||
VU->vifRegs->stat.DBF = 1;
|
||||
VU->vifRegs->stat.DBF = true;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue