mirror of https://github.com/PCSX2/pcsx2.git
backup, just ignore this
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@672 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
c1a59e6cc6
commit
2add61d729
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@ -236,7 +236,7 @@ BEGIN
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GROUPBOX "Other Options",IDC_STATIC,281,210,237,34,BS_LEFT
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LTEXT "These options specify how PCSX2's recompilers will clamp Infinities and NaN (Not a Number) values in the opcode instructions.",IDC_STATIC,286,94,224,19
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LTEXT "*None* - No clamping. (Fastest Mode)\n*Normal* - Clamps the result.\n*Extra* - Clamps the operands, the result, and anywhere in between.\n*Extra + Preserve Sign* - Same as ""Extra"", except preserves NaN's sign when clamping the operands.",IDC_STATIC,286,114,224,48
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LTEXT "*Full* - Attempts to emulates large numbers correctly for the EE's FPU. VU's clamp mode should be set to ""Extra + Preserve Sign"" for this to work best. (but still works for most games even with ""Normal"" VU clamping)",IDC_STATIC,287,163,214,36
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LTEXT "*Full* - Attempts to emulate large numbers correctly for the EE's FPU. VU's clamp mode should be set to ""Extra + Preserve Sign"" for this to work best. (but still works for most games even with ""Normal"" VU clamping)",IDC_STATIC,287,163,214,36
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LTEXT "Flush to Zero - Makes floating point underflows become zero.\nDenormals are Zero - Makes floating point denormals become zero.",IDC_STATIC,287,222,224,18
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END
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@ -17,8 +17,10 @@
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*/
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#pragma once
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#define _EmitterId_ (vuIndex+1)
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#include "Common.h"
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#include "VU.h"
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#include "ix86/ix86.h"
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#include "microVU_Misc.h"
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#include "microVU_Alloc.h"
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#include "microVU_Tables.h"
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@ -110,6 +112,7 @@ struct microVU {
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VURegs* regs; // VU Regs Struct
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u8* cache; // Dynarec Cache Start (where we will start writing the recompiled code to)
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u8* ptr; // Pointer to next place to write recompiled code to
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u32 code; // Contains the current Instruction
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/*
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uptr x86eax; // Accumulator register. Used in arithmetic operations.
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uptr x86ecx; // Counter register. Used in shift/rotate instructions.
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@ -30,32 +30,59 @@ extern PCSX2_ALIGNED16(microVU microVU1);
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//------------------------------------------------------------------
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// Micro VU - recPass 1 Functions
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//------------------------------------------------------------------
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/*
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#define setFd (mVU->prog.prog[mVU->prog.cur].allocInfo.info[pc] & (1<<7))
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#define getFd (mVU->prog.prog[mVU->prog.cur].allocInfo.info[pc] & (1<<1))
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#define getFs (mVU->prog.prog[mVU->prog.cur].allocInfo.info[pc] & (1<<2))
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#define getFt (mVU->prog.prog[mVU->prog.cur].allocInfo.info[pc] & (1<<3))
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*/
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#define makeFdFd (makeFd == 0)
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#define makeFdFs (makeFd == 1)
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#define makeFdFt (makeFd == 2)
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microVUt(void) mVUallocFMAC1a(u32 code, int& Fd, int& Fs, int& Ft, const int makeFd) {
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microVU* mVU = mVUx;
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if (_Fs_ == 0) { Fs = xmmZ; } else { Fs = xmmFs; }
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if (_Ft_ == 0) { Ft = xmmZ; } else { Ft = xmmFt; }
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if (makeFdFd) {Fd = xmmFd;}
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else if (makeFdFs) {Fd = Fs;}
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else if (makeFdFt) {Fd = Ft;}
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if (_Fs_) SSE_MOVAPS_M128_to_XMM(Fs, (uptr)&mVU->regs->VF[_Fs_].UL[0]);
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if (_Ft_ == _Ft_) SSE_MOVAPS_M128_to_XMM(Ft, (uptr)&mVU->regs->VF[_Ft_].UL[0]);
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#define getReg(reg, _reg_) { \
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mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], _X_Y_Z_W); \
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if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, _X_Y_Z_W); \
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}
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microVUt(void) mVUallocFMAC1b(u32 code, u32 pc, int& Fd) {
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#define getZeroSS(reg) { \
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if (_W) { mVUloadReg(reg, (uptr)&mVU->regs->VF[0].UL[0], _X_Y_Z_W); } \
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else { SSE_XORPS_XMM_to_XMM(reg, reg); } \
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}
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#define getZero(reg) { \
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if (_W) { mVUloadReg(reg, (uptr)&mVU->regs->VF[0].UL[0], _X_Y_Z_W); } \
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else { SSE_XORPS_XMM_to_XMM(reg, reg); } \
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}
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// Note: If _Ft_ is 0, then don't modify xmm reg Ft, because its equal to xmmZ (unless _XYZW_SS, then you can modify xmm reg Ft)
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microVUt(void) mVUallocFMAC1a(int& Fd, int& Fs, int& Ft, const bool makeFd) {
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microVU* mVU = mVUx;
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if (_Fd_ == 0) return;
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else mVUsaveReg<vuIndex>(code, Fd, (uptr)&mVU->regs->VF[_Fd_].UL[0]);
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Fs = xmmFs;
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Ft = xmmFt;
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if (_XYZW_SS) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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if (_Ft_ == _Fs_) { Ft = Fs; }
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else {
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if (!_Ft_) { getZeroSS(Ft); }
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else { getReg(Ft, _Ft_); }
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}
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}
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else {
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if (!_Fs_) { getZero(Fs); }
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else { getReg(Fs, _Fs_); }
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if (_Ft_ == _Fs_) { Ft = Fs; }
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else {
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if (!_Ft_) { getZero(Ft); }
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else { getReg(Ft, _Ft_); }
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}
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}
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if (makeFdFs) {Fd = Fs;}
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else {Fd = xmmFd;}
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}
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microVUt(void) mVUallocFMAC1b(int& Fd) {
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microVU* mVU = mVUx;
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if (!_Fd_) return;
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if (CHECK_VU_OVERFLOW) mVUclamp1<vuIndex>(Fd, xmmT1, _X_Y_Z_W);
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mVUsaveReg<vuIndex>(Fd, (uptr)&mVU->regs->VF[_Fd_].UL[0], _X_Y_Z_W);
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}
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#endif //PCSX2_MICROVU
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@ -44,6 +44,13 @@ struct microAllocInfo {
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// bit 4 = ACC1 or ACC2?
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// bit 5 = Read Q1/P1 or backup?
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// bit 6 = Write to Q2/P2?
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// bit 7 = Write Fd/Acc to backup memory?
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// bit 7 = Write Fd/Acc/Result to backup memory?
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// bit 8 = Update Status Flags?
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// bit 9 = Update Mac Flags?
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// bit 10 = Used with bit 11 to make a 2-bit key for status/mac flag instance
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// bit 11 = (00 = instance #0, 01 = instance #1, 10 = instance #2, 11 = instance #3)
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u32 curPC;
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};
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microVUt(void) mVUallocFMAC1a(int& Fd, int& Fs, int& Ft, const bool makeFd);
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microVUt(void) mVUallocFMAC1b(int& Fd);
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@ -23,28 +23,55 @@
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extern PCSX2_ALIGNED16(microVU microVU0);
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extern PCSX2_ALIGNED16(microVU microVU1);
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//------------------------------------------------------------------
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// Micro VU - Clamp Functions
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//------------------------------------------------------------------
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// Used for Result Clamping
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microVUx(void) mVUclamp1(int reg, int regTemp, int xyzw) {
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}
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// Used for Operand Clamping
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microVUx(void) mVUclamp2(int reg, int regTemp, int xyzw) {
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}
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//------------------------------------------------------------------
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// Micro VU - Misc Functions
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//------------------------------------------------------------------
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microVUx(void) mVUsaveReg(u32 code, int reg, u32 offset) {
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switch ( _X_Y_Z_W ) {
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microVUx(void) mVUunpack_xyzw(int dstreg, int srcreg, int xyzw) {
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switch ( xyzw ) {
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case 0: SSE2_PSHUFD_XMM_to_XMM(dstreg, srcreg, 0x00); break;
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case 1: SSE2_PSHUFD_XMM_to_XMM(dstreg, srcreg, 0x55); break;
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case 2: SSE2_PSHUFD_XMM_to_XMM(dstreg, srcreg, 0xaa); break;
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case 3: SSE2_PSHUFD_XMM_to_XMM(dstreg, srcreg, 0xff); break;
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}
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}
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microVUx(void) mVUloadReg(int reg, u32 offset, int xyzw) {
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switch( xyzw ) {
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case 8: SSE_MOVSS_M32_to_XMM(reg, offset); break; // X
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case 4: SSE_MOVSS_M32_to_XMM(reg, offset+4); break; // Y
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case 2: SSE_MOVSS_M32_to_XMM(reg, offset+8); break; // Z
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case 1: SSE_MOVSS_M32_to_XMM(reg, offset+12); break; // W
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case 3: SSE_MOVHPS_M64_to_XMM(reg, offset+8); break; // ZW (not sure if this is faster than default)
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case 12: SSE_MOVLPS_M64_to_XMM(reg, offset); break; // XY (not sure if this is faster than default)
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default: SSE_MOVAPS_M128_to_XMM(reg, offset); break;
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}
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}
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microVUx(void) mVUsaveReg(int reg, u32 offset, int xyzw) {
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switch ( xyzw ) {
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case 1: // W
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//SSE2_PSHUFD_XMM_to_XMM(xmmT1, reg, 0x27);
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//SSE_MOVSS_XMM_to_M32(offset+12, xmmT1);
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SSE_MOVSS_XMM_to_M32(offset+12, reg);
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break;
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case 2: // Z
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//SSE_MOVHLPS_XMM_to_XMM(xmmT1, reg);
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//SSE_MOVSS_XMM_to_M32(offset+8, xmmT1);
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SSE_MOVSS_XMM_to_M32(offset+8, reg);
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break;
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case 3: // ZW
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SSE_MOVHPS_XMM_to_M64(offset+8, reg);
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break;
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case 4: // Y
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//SSE2_PSHUFLW_XMM_to_XMM(xmmT1, reg, 0x4e);
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//SSE_MOVSS_XMM_to_M32(offset+4, xmmT1);
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SSE_MOVSS_XMM_to_M32(offset+4, reg);
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break;
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case 5: // YW
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@ -52,7 +79,6 @@ microVUx(void) mVUsaveReg(u32 code, int reg, u32 offset) {
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SSE_MOVHLPS_XMM_to_XMM(xmmT1, reg);
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SSE_MOVSS_XMM_to_M32(offset+4, reg);
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SSE_MOVSS_XMM_to_M32(offset+12, xmmT1);
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SSE_SHUFPS_XMM_to_XMM(reg, reg, 0xB1);
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break;
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case 6: // YZ
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SSE2_PSHUFD_XMM_to_XMM(xmmT1, reg, 0xc9);
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@ -96,8 +122,7 @@ microVUx(void) mVUsaveReg(u32 code, int reg, u32 offset) {
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SSE_MOVSS_XMM_to_M32(offset+8, xmmT1);
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break;
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case 15: // XYZW
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if( offset & 15 ) SSE_MOVUPS_XMM_to_M128(offset, reg);
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else SSE_MOVAPS_XMM_to_M128(offset, reg);
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SSE_MOVAPS_XMM_to_M128(offset, reg);
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break;
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}
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}
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@ -18,57 +18,36 @@
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#pragma once
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#ifdef __LINUX__
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#include "ix86/ix86.h"
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#endif
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//------------------------------------------------------------------
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// Helper Macros
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//------------------------------------------------------------------
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#define _Ft_ ((code >> 16) & 0x1F) // The rt part of the instruction register
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#define _Fs_ ((code >> 11) & 0x1F) // The rd part of the instruction register
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#define _Fd_ ((code >> 6) & 0x1F) // The sa part of the instruction register
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#define _Ft_ ((mVU->code >> 16) & 0x1F) // The rt part of the instruction register
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#define _Fs_ ((mVU->code >> 11) & 0x1F) // The rd part of the instruction register
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#define _Fd_ ((mVU->code >> 6) & 0x1F) // The sa part of the instruction register
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#define _X ((code>>24) & 0x1)
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#define _Y ((code>>23) & 0x1)
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#define _Z ((code>>22) & 0x1)
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#define _W ((code>>21) & 0x1)
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#define _X ((mVU->code>>24) & 0x1)
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#define _Y ((mVU->code>>23) & 0x1)
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#define _Z ((mVU->code>>22) & 0x1)
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#define _W ((mVU->code>>21) & 0x1)
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#define _XYZW_SS (_X+_Y+_Z+_W==1)
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#define _X_Y_Z_W (((code >> 21 ) & 0xF ) )
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#define _X_Y_Z_W (((mVU->code >> 21 ) & 0xF ) )
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#define _Fsf_ ((code >> 21) & 0x03)
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#define _Ftf_ ((code >> 23) & 0x03)
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#define _Fsf_ ((mVU->code >> 21) & 0x03)
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#define _Ftf_ ((mVU->code >> 23) & 0x03)
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#define _Imm11_ (s32)(code & 0x400 ? 0xfffffc00 | (code & 0x3ff) : code & 0x3ff)
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#define _UImm11_ (s32)(code & 0x7ff)
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/*
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#define VU_VFx_ADDR(x) (uptr)&VU->VF[x].UL[0]
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#define VU_VFy_ADDR(x) (uptr)&VU->VF[x].UL[1]
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#define VU_VFz_ADDR(x) (uptr)&VU->VF[x].UL[2]
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#define VU_VFw_ADDR(x) (uptr)&VU->VF[x].UL[3]
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#define _Imm11_ (s32)(mVU->code & 0x400 ? 0xfffffc00 | (mVU->code & 0x3ff) : mVU->code & 0x3ff)
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#define _UImm11_ (s32)(mVU->code & 0x7ff)
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#define VU_REGR_ADDR (uptr)&VU->VI[REG_R]
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#define VU_REGQ_ADDR (uptr)&VU->VI[REG_Q]
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#define VU_REGMAC_ADDR (uptr)&VU->VI[REG_MAC_FLAG]
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#define VU_VI_ADDR(x, read) GetVIAddr(VU, x, read, info)
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#define VU_ACCx_ADDR (uptr)&VU->ACC.UL[0]
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#define VU_ACCy_ADDR (uptr)&VU->ACC.UL[1]
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#define VU_ACCz_ADDR (uptr)&VU->ACC.UL[2]
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#define VU_ACCw_ADDR (uptr)&VU->ACC.UL[3]
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*/
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#define xmmT1 0 // XMM0
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#define xmmFd 1 // XMM1
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#define xmmFs 2 // XMM2
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#define xmmFt 3 // XMM3
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#define xmmACC1 4 // XMM4
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#define xmmACC2 5 // XMM5
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#define xmmPQ 6 // XMM6
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#define xmmZ 7 // XMM7
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#define xmmT1 0 // XMM0 // Temp Reg
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#define xmmFd 1 // XMM1 // Holds the Value of Fd
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#define xmmFs 2 // XMM2 // Holds the Value of Fs
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#define xmmFt 3 // XMM3 // Holds the Value of Ft
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#define xmmACC1 4 // XMM4 // Holds the Value of ACC
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#define xmmACC2 5 // XMM5 // Holds the Backup Value of ACC
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#define xmmPQ 6 // XMM6 // Holds the Value and Backup Values of P and Q regs
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#define xmmF 7 // XMM7 // Holds 4 instances of the status and mac flags (macflagX4::statusflagX4)
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// Template Stuff
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#define mVUx (vuIndex ? µVU1 : µVU0)
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@ -76,4 +55,11 @@
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#define microVUx(aType) template<int vuIndex> aType
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#define microVUf(aType) template<int vuIndex, int recPass> aType
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microVUx(void) mVUsaveReg(u32 code, int reg, u32 offset);
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#define mVUallocInfo mVU->prog.prog[mVU->prog.cur].allocInfo
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#define isNOP (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<0))
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#define getFd (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<1))
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#define getFs (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<2))
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#define getFt (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<3))
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#define setFd (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<7))
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#define doFlags (mVUallocInfo.info[mVUallocInfo.curPC] & (3<<8))
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@ -20,57 +20,75 @@
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#include "microVU.h"
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#ifdef PCSX2_MICROVU
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/*
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Cotton's Notes on how things will work (*experimental*, subject to change if I get different ideas):
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//------------------------------------------------------------------
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// mVUupdateFlags() - Updates status/mac flags
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//------------------------------------------------------------------
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Guide:
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Fd, Fs, Ft = operands in the Micro Instructions
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Acc = VU's Accumulator register
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Fs/t = shorthand notation I made-up for "Fs or Ft"
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xmmFd, xmmFs, xmmFt, xmmAcc = XMM regs that hold Fd, Fs, Ft, and Acc values respectively.
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xmmZ = XMM reg that holds the zero Register; always {0, 0, 0, 1.0}
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xmmT1, xmmT2, xmmT3 = temp regs.
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microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw) {
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microVU* mVU = mVUx;
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static u8 *pjmp, *pjmp2;
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static u32 *pjmp32;
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static u32 macaddr, stataddr, prevstataddr;
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static int x86macflag, x86statflag, x86temp;
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General:
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XMM0 is a volatile temp reg throughout the recs. You can always freely use it.
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EAX is a volatile temp reg. You can always freely use it.
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//SysPrintf ("mVUupdateFlags\n");
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if( !(doFlags) ) return;
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Mapping:
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xmmT1 = xmm0
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xmmFd = xmm1
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xmmFs = xmm2
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xmmFt = xmm3
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xmmACC1 = xmm4
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xmmACC2 = xmm5
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xmmPQ = xmm6
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xmmZ = xmm7
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//macaddr = VU_VI_ADDR(REG_MAC_FLAG, 0);
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//stataddr = VU_VI_ADDR(REG_STATUS_FLAG, 0); // write address
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//prevstataddr = VU_VI_ADDR(REG_STATUS_FLAG, 2); // previous address
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|
||||
Most of the time the above mapping will be true, unless I find a reason not to do it this way :)
|
||||
|
||||
Opcodes:
|
||||
Fd's 4-vectors must be preserved (kept valid); Unless operation is single-scalar, then only 'x' XMM vector
|
||||
will contain valid data for X, Y, Z, or W, and the other XMM vectors will be garbage and freely modifiable.
|
||||
SSE2_PSHUFD_XMM_to_XMM(regT1, reg, 0x1B); // Flip wzyx to xyzw
|
||||
MOV32MtoR(x86statflag, prevstataddr); // Load the previous status in to x86statflag
|
||||
AND16ItoR(x86statflag, 0xff0); // Keep Sticky and D/I flags
|
||||
|
||||
Fs and Ft are temp regs that won't be used after the opcode, so their values can be freely modified.
|
||||
//-------------------------Check for Signed flags------------------------------
|
||||
|
||||
If (Fd == 0), Then you don't need to explicitly handle this case in the opcode implementation,
|
||||
since its dealt-with in the analyzing microVU pipeline functions.
|
||||
(So just do the normal operation and don't worry about it.)
|
||||
// The following code makes sure the Signed Bit isn't set with Negative Zero
|
||||
SSE_XORPS_XMM_to_XMM(regT2, regT2); // Clear regT2
|
||||
SSE_CMPEQPS_XMM_to_XMM(regT2, regT1); // Set all F's if each vector is zero
|
||||
SSE_MOVMSKPS_XMM_to_R32(EAX, regT2); // Used for Zero Flag Calculation
|
||||
SSE_ANDNPS_XMM_to_XMM(regT2, regT1);
|
||||
|
||||
If (_X_Y_Z_W == 0) Then same as above. (btw, I'm'm not sure if this case ever happens...)
|
||||
SSE_MOVMSKPS_XMM_to_R32(x86macflag, regT2); // Move the sign bits of the t1reg
|
||||
|
||||
If (Fd == Fs/t), Then xmmFd != xmmFs/t (unless its more optimized this way! it'll be commented on the opcode)
|
||||
AND16ItoR(x86macflag, _X_Y_Z_W ); // Grab "Is Signed" bits from the previous calculation
|
||||
pjmp = JZ8(0); // Skip if none are
|
||||
OR16ItoR(x86statflag, 0x82); // SS, S flags
|
||||
SHL16ItoR(x86macflag, 4);
|
||||
if (_XYZW_SS) pjmp2 = JMP8(0); // If negative and not Zero, we can skip the Zero Flag checking
|
||||
x86SetJ8(pjmp);
|
||||
|
||||
Clamping:
|
||||
Fs/t can always be clamped by case 15 (all vectors modified) since they won't be written back.
|
||||
//-------------------------Check for Zero flags------------------------------
|
||||
|
||||
Problems:
|
||||
The biggest problem I think I'll have is xgkick opcode having variable timing/stalling.
|
||||
AND16ItoR(EAX, _X_Y_Z_W ); // Grab "Is Zero" bits from the previous calculation
|
||||
pjmp = JZ8(0); // Skip if none are
|
||||
OR16ItoR(x86statflag, 0x41); // ZS, Z flags
|
||||
OR32RtoR(x86macflag, EAX);
|
||||
x86SetJ8(pjmp);
|
||||
|
||||
Other Notes:
|
||||
These notes are mostly to help me (cottonvibes) remember good ideas and to help confused devs to
|
||||
have an idea of how things work. Right now its all theoretical and I'll change things once implemented ;p
|
||||
*/
|
||||
//-------------------------Finally: Send the Flags to the Mac Flag Address------------------------------
|
||||
|
||||
if (_XYZW_SS) x86SetJ8(pjmp2); // If we skipped the Zero Flag Checking, return here
|
||||
|
||||
MOV16RtoM(macaddr, x86macflag);
|
||||
MOV16RtoM(stataddr, x86statflag);
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// Helper Macros
|
||||
//------------------------------------------------------------------
|
||||
|
||||
#define mVU_FMAC1(operation) { \
|
||||
if (isNOP) return; \
|
||||
int Fd, Fs, Ft; \
|
||||
mVUallocFMAC1a<vuIndex>(Fd, Fs, Ft, 1); \
|
||||
if (_XYZW_SS) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \
|
||||
else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \
|
||||
mVUupdateFlags<vuIndex>(Fd, xmmT1, Ft, _X_Y_Z_W); \
|
||||
mVUallocFMAC1b<vuIndex>(Fd); \
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// Micro VU Micromode Upper instructions
|
||||
|
|
@ -78,8 +96,9 @@ have an idea of how things work. Right now its all theoretical and I'll change t
|
|||
|
||||
microVUf(void) mVU_ABS(){}
|
||||
microVUf(void) mVU_ADD() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
else {}
|
||||
else { mVU_FMAC1(ADD); }
|
||||
}
|
||||
microVUf(void) mVU_ADDi(){}
|
||||
microVUf(void) mVU_ADDq(){}
|
||||
|
|
@ -94,7 +113,11 @@ microVUf(void) mVU_ADDAx(){}
|
|||
microVUf(void) mVU_ADDAy(){}
|
||||
microVUf(void) mVU_ADDAz(){}
|
||||
microVUf(void) mVU_ADDAw(){}
|
||||
microVUf(void) mVU_SUB(){}
|
||||
microVUf(void) mVU_SUB(){
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
else { mVU_FMAC1(SUB); }
|
||||
}
|
||||
microVUf(void) mVU_SUBi(){}
|
||||
microVUf(void) mVU_SUBq(){}
|
||||
microVUf(void) mVU_SUBx(){}
|
||||
|
|
@ -108,7 +131,11 @@ microVUf(void) mVU_SUBAx(){}
|
|||
microVUf(void) mVU_SUBAy(){}
|
||||
microVUf(void) mVU_SUBAz(){}
|
||||
microVUf(void) mVU_SUBAw(){}
|
||||
microVUf(void) mVU_MUL(){}
|
||||
microVUf(void) mVU_MUL(){
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
else { mVU_FMAC1(MUL); }
|
||||
}
|
||||
microVUf(void) mVU_MULi(){}
|
||||
microVUf(void) mVU_MULq(){}
|
||||
microVUf(void) mVU_MULx(){}
|
||||
|
|
|
|||
Loading…
Reference in New Issue