From 2a92edd7edbfcb6e7e19ef667658fc1c9907c92f Mon Sep 17 00:00:00 2001 From: Stenzek Date: Thu, 29 Dec 2022 01:09:39 +1000 Subject: [PATCH] x86/iR5900: Don't rename GPR from mf{hi,lo} when in xmm Redundant codegen, also incorrect when not in GPR. --- pcsx2/x86/ix86-32/iR5900Move.cpp | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/pcsx2/x86/ix86-32/iR5900Move.cpp b/pcsx2/x86/ix86-32/iR5900Move.cpp index b7f4c6fad4..fc10125cb9 100644 --- a/pcsx2/x86/ix86-32/iR5900Move.cpp +++ b/pcsx2/x86/ix86-32/iR5900Move.cpp @@ -179,10 +179,7 @@ static void recMTHILO(bool hi, bool upper) } else { - // try rename rs -> {hi,lo} - const int gprs = _checkX86reg(X86TYPE_GPR, _Rs_, MODE_READ); - if (gprs >= 0 && !upper && _eeTryRenameReg(reg, _Rs_, gprs, -1, 0) >= 0) - return; + int gprs = _allocIfUsedGPRtoX86(_Rs_, MODE_READ); if (xmmhilo >= 0) { @@ -192,8 +189,9 @@ static void recMTHILO(bool hi, bool upper) } else if (GPR_IS_CONST1(_Rs_)) { - _eeMoveGPRtoR(rax, _Rs_); - xPINSR.Q(xRegisterSSE(xmmhilo), rax, static_cast(upper)); + // force it into a register, since we need to load the constant anyway + gprs = _allocX86reg(X86TYPE_GPR, _Rs_, MODE_READ); + xPINSR.Q(xRegisterSSE(xmmhilo), xRegister64(gprs), static_cast(upper)); } else { @@ -202,11 +200,21 @@ static void recMTHILO(bool hi, bool upper) } else { + // try rename rs -> {hi,lo} + if (gprs >= 0 && !upper && _eeTryRenameReg(reg, _Rs_, gprs, -1, 0) >= 0) + return; + const int gprreg = upper ? -1 : _allocIfUsedGPRtoX86(reg, MODE_WRITE); if (gprreg >= 0) + { _eeMoveGPRtoR(xRegister64(gprreg), _Rs_); + } else - _eeMoveGPRtoM((uptr)(hi ? &cpuRegs.HI.UD[static_cast(upper)] : &cpuRegs.LO.UD[static_cast(upper)]), _Rs_); + { + // force into a register, since we need to load it to write anyway + gprs = _allocX86reg(X86TYPE_GPR, _Rs_, MODE_READ); + xMOV(ptr64[hi ? &cpuRegs.HI.UD[static_cast(upper)] : &cpuRegs.LO.UD[static_cast(upper)]], xRegister64(gprs)); + } } } }