From 286769dc034ddbc97c71337876101d1d10d9c253 Mon Sep 17 00:00:00 2001
From: refractionpcsx2 <refraction@gmail.com>
Date: Sat, 24 Oct 2015 13:24:57 +0100
Subject: [PATCH] VIF MFifo: Simulate buffer filling time from Scratchpad.
 -Fixes other Chessmaster hang. -having it say it has data really quickly if
 the data incoming was huge seemed to throw it off.  I suspect it may actually
 be the time it takes to fill 16qw (or whatever is incoming if lower) is the
 wait time but it seems rather happy with the incoming data size.

---
 pcsx2/Vif.cpp        | 2 +-
 pcsx2/Vif1_MFIFO.cpp | 8 +++-----
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/pcsx2/Vif.cpp b/pcsx2/Vif.cpp
index 88335daf5c..d1e5a0df96 100644
--- a/pcsx2/Vif.cpp
+++ b/pcsx2/Vif.cpp
@@ -271,7 +271,7 @@ __fi void vif1FBRST(u32 value) {
 				    case MFD_VIF1:
                         //Console.WriteLn("MFIFO Stall");
 						//MFIFO active and not empty
-                        if(vif1ch.chcr.STR == true && !(vif1.inprogress & 0x10)) CPU_INT(DMAC_MFIFO_VIF, 0);
+                        if(vif1ch.chcr.STR == true) CPU_INT(DMAC_MFIFO_VIF, 0);
                         break;
 
                     case NO_MFD:
diff --git a/pcsx2/Vif1_MFIFO.cpp b/pcsx2/Vif1_MFIFO.cpp
index e4feb0049a..2777820c2c 100644
--- a/pcsx2/Vif1_MFIFO.cpp
+++ b/pcsx2/Vif1_MFIFO.cpp
@@ -187,7 +187,8 @@ void mfifoVIF1transfer(int qwc)
 			if(vif1ch.chcr.STR == true && !(cpuRegs.interrupt & (1<<DMAC_MFIFO_VIF)) && !vif1Regs.stat.INT)
 			{
 				SPR_LOG("Data Added, Resuming");
-				CPU_INT(DMAC_MFIFO_VIF, 16);
+				//Need to simulate the time it takes to copy here, if the VIF resumes before the SPR has finished, it isn't happy.
+				CPU_INT(DMAC_MFIFO_VIF, qwc * BIAS);
 			}
 
 			//Apparently this is bad, i guess so, the data is going to memory rather than the FIFO
@@ -329,10 +330,7 @@ void vifMFIFOInterrupt()
 
 		hwIntcIrq(INTC_VIF1);
 		--vif1.irq;
-		if (vif1.inprogress & 0x10) {
-			FireMFIFOEmpty();
-			//if (!(vif1.done && vif1ch.qwc == 0))return;
-		}
+		
 		if (vif1Regs.stat.test(VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS)) {
 			//vif1Regs.stat.FQC = 0; // FQC=0
 			//vif1ch.chcr.STR = false;