mirror of https://github.com/PCSX2/pcsx2.git
Remove some code from DMAC.h and into LegacyDmac.cpp (these changes are mostly related to the new dmac prep on the other branch, but I'm doing them here to help keep major refactoring differences and merge conflicts to a minimum between the two branches).
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3710 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
f6a541928a
commit
27a3f11278
149
pcsx2/Dmac.h
149
pcsx2/Dmac.h
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@ -171,10 +171,6 @@ union tDMA_QWC {
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tDMA_TAG tag() const { return (tDMA_TAG)_u32; }
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};
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static void setDmacStat(u32 num);
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static tDMA_TAG *dmaGetAddr(u32 addr, bool write);
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static void throwBusError(const char *s);
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struct DMACh {
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tDMA_CHCR chcr;
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u32 _null0[3];
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@ -200,63 +196,14 @@ struct DMACh {
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qwc = ptag[0].QWC;
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}
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bool transfer(const char *s, tDMA_TAG* ptag)
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{
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if (ptag == NULL) // Is ptag empty?
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{
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throwBusError(s);
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return false;
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}
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chcrTransfer(ptag);
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bool transfer(const char *s, tDMA_TAG* ptag);
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void unsafeTransfer(tDMA_TAG* ptag);
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tDMA_TAG *getAddr(u32 addr, u32 num, bool write);
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tDMA_TAG *DMAtransfer(u32 addr, u32 num);
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tDMA_TAG dma_tag();
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qwcTransfer(ptag);
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return true;
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}
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void unsafeTransfer(tDMA_TAG* ptag)
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{
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chcrTransfer(ptag);
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qwcTransfer(ptag);
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}
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tDMA_TAG *getAddr(u32 addr, u32 num, bool write)
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{
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tDMA_TAG *ptr = dmaGetAddr(addr, write);
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if (ptr == NULL)
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{
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throwBusError("dmaGetAddr");
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setDmacStat(num);
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chcr.STR = false;
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}
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return ptr;
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}
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tDMA_TAG *DMAtransfer(u32 addr, u32 num)
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{
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tDMA_TAG *tag = getAddr(addr, num, false);
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if (tag == NULL) return NULL;
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chcrTransfer(tag);
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qwcTransfer(tag);
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return tag;
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}
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tDMA_TAG dma_tag()
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{
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return chcr.tag();
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}
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wxString cmq_to_str() const
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{
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return wxsFormat(L"chcr = %lx, madr = %lx, qwc = %lx", chcr._u32, madr, qwc);
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}
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wxString cmqt_to_str() const
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{
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return wxsFormat(L"chcr = %lx, madr = %lx, qwc = %lx, tadr = %1x", chcr._u32, madr, qwc, tadr);
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}
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wxString cmq_to_str() const;
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wxString cmqt_to_str() const;
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};
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enum INTCIrqs
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@ -599,80 +546,10 @@ static DMACh& gifch = (DMACh&)eeHw[0xA000];
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static DMACh& spr0ch = (DMACh&)eeHw[0xD000];
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static DMACh& spr1ch = (DMACh&)eeHw[0xD400];
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static __fi void throwBusError(const char *s)
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{
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Console.Error("%s BUSERR", s);
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dmacRegs.stat.BEIS = true;
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}
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static __fi void setDmacStat(u32 num)
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{
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dmacRegs.stat.set_flags(1 << num);
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}
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// Note: Dma addresses are guaranteed to be aligned to 16 bytes (128 bits)
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static __fi tDMA_TAG *SPRdmaGetAddr(u32 addr, bool write)
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{
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// if (addr & 0xf) { DMA_LOG("*PCSX2*: DMA address not 128bit aligned: %8.8x", addr); }
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//For some reason Getaway references SPR Memory from itself using SPR0, oh well, let it i guess...
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if((addr & 0x70000000) == 0x70000000)
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{
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return (tDMA_TAG*)&eeMem->Scratch[addr & 0x3ff0];
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}
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// FIXME: Why??? DMA uses physical addresses
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addr &= 0x1ffffff0;
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if (addr < Ps2MemSize::Base)
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{
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return (tDMA_TAG*)&eeMem->Main[addr];
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}
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else if (addr < 0x10000000)
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{
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return (tDMA_TAG*)(write ? eeMem->ZeroWrite : eeMem->ZeroRead);
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}
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else if ((addr >= 0x11004000) && (addr < 0x11010000))
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{
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//Access for VU Memory
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return (tDMA_TAG*)vtlb_GetPhyPtr(addr & 0x1FFFFFF0);
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}
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else
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{
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Console.Error( "*PCSX2*: DMA error: %8.8x", addr);
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return NULL;
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}
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}
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// Note: Dma addresses are guaranteed to be aligned to 16 bytes (128 bits)
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static __ri tDMA_TAG *dmaGetAddr(u32 addr, bool write)
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{
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// if (addr & 0xf) { DMA_LOG("*PCSX2*: DMA address not 128bit aligned: %8.8x", addr); }
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if (DMA_TAG(addr).SPR) return (tDMA_TAG*)&eeMem->Scratch[addr & 0x3ff0];
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// FIXME: Why??? DMA uses physical addresses
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addr &= 0x1ffffff0;
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if (addr < Ps2MemSize::Base)
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{
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return (tDMA_TAG*)&eeMem->Main[addr];
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}
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else if (addr < 0x10000000)
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{
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return (tDMA_TAG*)(write ? eeMem->ZeroWrite : eeMem->ZeroRead);
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}
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else if (addr < 0x10004000)
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{
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// Secret scratchpad address for DMA = end of maximum main memory?
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//Console.Warning("Writing to the scratchpad without the SPR flag set!");
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return (tDMA_TAG*)&eeMem->Scratch[addr & 0x3ff0];
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}
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else
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{
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Console.Error( "*PCSX2*: DMA error: %8.8x", addr);
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return NULL;
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}
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}
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extern void throwBusError(const char *s);
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extern void setDmacStat(u32 num);
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extern tDMA_TAG *SPRdmaGetAddr(u32 addr, bool write);
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extern tDMA_TAG *dmaGetAddr(u32 addr, bool write);
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extern void hwIntcIrq(int n);
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extern void hwDmacIrq(int n);
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@ -681,5 +558,5 @@ extern bool hwMFIFOWrite(u32 addr, const u128* data, uint size_qwc);
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extern bool hwDmacSrcChainWithStack(DMACh& dma, int id);
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extern bool hwDmacSrcChain(DMACh& dma, int id);
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template< uint page >
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extern bool dmacWrite32( u32 mem, mem32_t& value );
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template< uint page > u32 dmacRead32( u32 mem );
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template< uint page > extern bool dmacWrite32( u32 mem, mem32_t& value );
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@ -48,12 +48,7 @@ mem32_t __fastcall _hwRead32(u32 mem)
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case 0x02: return ipuRead32( mem );
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case 0x03:
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if ((mem == GIF_STAT) && CHECK_OPHFLAGHACK)
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{
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gifRegs.stat.OPH = !gifRegs.stat.OPH;
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}
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break;
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case 0x03: return dmacRead32<0x03>( mem );
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case 0x04:
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case 0x05:
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@ -20,6 +20,140 @@
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#include "ps2/HwInternal.h"
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bool DMACh::transfer(const char *s, tDMA_TAG* ptag)
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{
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if (ptag == NULL) // Is ptag empty?
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{
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throwBusError(s);
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return false;
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}
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chcrTransfer(ptag);
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qwcTransfer(ptag);
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return true;
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}
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void DMACh::unsafeTransfer(tDMA_TAG* ptag)
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{
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chcrTransfer(ptag);
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qwcTransfer(ptag);
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}
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tDMA_TAG *DMACh::getAddr(u32 addr, u32 num, bool write)
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{
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tDMA_TAG *ptr = dmaGetAddr(addr, write);
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if (ptr == NULL)
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{
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throwBusError("dmaGetAddr");
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setDmacStat(num);
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chcr.STR = false;
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}
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return ptr;
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}
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tDMA_TAG *DMACh::DMAtransfer(u32 addr, u32 num)
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{
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tDMA_TAG *tag = getAddr(addr, num, false);
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if (tag == NULL) return NULL;
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chcrTransfer(tag);
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qwcTransfer(tag);
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return tag;
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}
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tDMA_TAG DMACh::dma_tag()
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{
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return chcr.tag();
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}
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wxString DMACh::cmq_to_str() const
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{
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return wxsFormat(L"chcr = %lx, madr = %lx, qwc = %lx", chcr._u32, madr, qwc);
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}
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wxString DMACh::cmqt_to_str() const
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{
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return wxsFormat(L"chcr = %lx, madr = %lx, qwc = %lx, tadr = %1x", chcr._u32, madr, qwc, tadr);
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}
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__fi void throwBusError(const char *s)
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{
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Console.Error("%s BUSERR", s);
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dmacRegs.stat.BEIS = true;
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}
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__fi void setDmacStat(u32 num)
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{
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dmacRegs.stat.set_flags(1 << num);
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}
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// Note: Dma addresses are guaranteed to be aligned to 16 bytes (128 bits)
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__fi tDMA_TAG *SPRdmaGetAddr(u32 addr, bool write)
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{
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// if (addr & 0xf) { DMA_LOG("*PCSX2*: DMA address not 128bit aligned: %8.8x", addr); }
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//For some reason Getaway references SPR Memory from itself using SPR0, oh well, let it i guess...
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if((addr & 0x70000000) == 0x70000000)
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{
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return (tDMA_TAG*)&eeMem->Scratch[addr & 0x3ff0];
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}
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// FIXME: Why??? DMA uses physical addresses
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addr &= 0x1ffffff0;
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if (addr < Ps2MemSize::Base)
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{
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return (tDMA_TAG*)&eeMem->Main[addr];
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}
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else if (addr < 0x10000000)
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{
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return (tDMA_TAG*)(write ? eeMem->ZeroWrite : eeMem->ZeroRead);
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}
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else if ((addr >= 0x11004000) && (addr < 0x11010000))
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{
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//Access for VU Memory
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return (tDMA_TAG*)vtlb_GetPhyPtr(addr & 0x1FFFFFF0);
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}
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else
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{
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Console.Error( "*PCSX2*: DMA error: %8.8x", addr);
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return NULL;
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}
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}
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// Note: Dma addresses are guaranteed to be aligned to 16 bytes (128 bits)
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__ri tDMA_TAG *dmaGetAddr(u32 addr, bool write)
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{
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// if (addr & 0xf) { DMA_LOG("*PCSX2*: DMA address not 128bit aligned: %8.8x", addr); }
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if (DMA_TAG(addr).SPR) return (tDMA_TAG*)&eeMem->Scratch[addr & 0x3ff0];
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// FIXME: Why??? DMA uses physical addresses
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addr &= 0x1ffffff0;
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if (addr < Ps2MemSize::Base)
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{
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return (tDMA_TAG*)&eeMem->Main[addr];
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}
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else if (addr < 0x10000000)
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{
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return (tDMA_TAG*)(write ? eeMem->ZeroWrite : eeMem->ZeroRead);
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}
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else if (addr < 0x10004000)
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{
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// Secret scratchpad address for DMA = end of maximum main memory?
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//Console.Warning("Writing to the scratchpad without the SPR flag set!");
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return (tDMA_TAG*)&eeMem->Scratch[addr & 0x3ff0];
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}
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else
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{
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Console.Error( "*PCSX2*: DMA error: %8.8x", addr);
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return NULL;
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}
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}
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// Returns true if the DMA is enabled and executed successfully. Returns false if execution
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// was blocked (DMAE or master DMA enabler).
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static bool QuickDmaExec( void (*func)(), u32 mem)
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@ -139,25 +273,16 @@ static __ri void DmaExec( void (*func)(), u32 mem, u32 value )
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} //else QueuedDMA._u16 &~= (1 << ChannelNumber(mem)); //
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}
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// DmaExec8 should only be called for the second byte of CHCR.
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// Testing Note: dark cloud 2 uses 8 bit DMAs register writes.
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static __fi void DmaExec8( void (*func)(), u32 mem, u8 value )
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{
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pxAssumeMsg( (mem & 0xf) == 1, "DmaExec8 should only be called for the second byte of CHCR" );
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// The calling function calls this when the second byte (bits 8->15) is written. Only bit 8
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// is effective, and it is the STR (start) bit. :)
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DmaExec( func, mem & ~0xf, (u32)value<<8 );
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}
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static __fi void DmaExec16( void (*func)(), u32 mem, u16 value )
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{
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DmaExec( func, mem, (u32)value );
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}
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template< uint page >
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__fi u32 dmacRead32( u32 mem )
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{
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// Fixme: OPH hack. Toggle the flag on each GIF_STAT access. (rama)
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if (IsPageFor(mem) && (mem == GIF_STAT) && CHECK_OPHFLAGHACK)
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{
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gifRegs.stat.OPH = !gifRegs.stat.OPH;
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}
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return psHu32(mem);
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}
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// Returns TRUE if the caller should do writeback of the register to eeHw; false if the
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@ -326,17 +451,16 @@ __fi bool dmacWrite32( u32 mem, mem32_t& value )
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return true;
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}
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template u32 dmacRead32<0x03>( u32 mem );
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template bool dmacWrite32<0x00>( u32 mem, mem32_t& value );
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template bool dmacWrite32<0x01>( u32 mem, mem32_t& value );
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template bool dmacWrite32<0x02>( u32 mem, mem32_t& value );
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template bool dmacWrite32<0x03>( u32 mem, mem32_t& value );
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template bool dmacWrite32<0x04>( u32 mem, mem32_t& value );
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template bool dmacWrite32<0x05>( u32 mem, mem32_t& value );
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template bool dmacWrite32<0x06>( u32 mem, mem32_t& value );
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template bool dmacWrite32<0x07>( u32 mem, mem32_t& value );
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template bool dmacWrite32<0x08>( u32 mem, mem32_t& value );
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template bool dmacWrite32<0x09>( u32 mem, mem32_t& value );
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template bool dmacWrite32<0x0a>( u32 mem, mem32_t& value );
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@ -344,5 +468,4 @@ template bool dmacWrite32<0x0b>( u32 mem, mem32_t& value );
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template bool dmacWrite32<0x0c>( u32 mem, mem32_t& value );
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template bool dmacWrite32<0x0d>( u32 mem, mem32_t& value );
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template bool dmacWrite32<0x0e>( u32 mem, mem32_t& value );
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template bool dmacWrite32<0x0f>( u32 mem, mem32_t& value );
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