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psxmode:EE: Plug SBUS PGIF register 

v2: improve code integration
v3: fix conflict between sif2/pgif code
This commit is contained in:
Robert 2016-09-23 10:33:03 +02:00 committed by Gregory Hainaut
parent 43e8796b2c
commit 277b8f3503
3 changed files with 63 additions and 9 deletions
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6
pcsx2/Hw.h
View File

@ -80,7 +80,9 @@ namespace EEMemoryMap
static const uint SIO_Start = 0x1000F100;
static const uint SIO_End = 0x1000F200;
static const uint SBUS_Start = 0x1000F200;
static const uint SBUS_End = 0x1000F400;
static const uint SBUS_End = 0x1000F300;
static const uint SBUS_PS1_Start = 0x1000F300;
static const uint SBUS_PS1_End = 0x1000F400;
// MCH area -- Really not sure what this area is. Information is lacking.
static const uint MCH_Start = 0x1000F400;
@ -330,7 +332,7 @@ enum EERegisterAddresses
SBUS_F250 = 0x1000F250,
SBUS_F260 = 0x1000F260,
SBUS_F300 = 0x1000F300,
SBUS_F380 = 0x1000F380,
SBUS_F380 = 0x1000F380,
MCH_RICM = 0x1000F430,
MCH_DRD = 0x1000F440,

30
pcsx2/HwRead.cpp
View File

@ -21,6 +21,8 @@
#include "ps2/HwInternal.h"
#include "ps2/eeHwTraceLog.inl"
#include "ps2/pgif.h"
using namespace R5900;
static __fi void IntCHackCheck()
@ -92,8 +94,13 @@ mem32_t __fastcall _hwRead32(u32 mem)
return psHu32(INTC_STAT);
}
// todo: psx mode: this is new
if (((mem & 0x1FFFFFFF) >= EEMemoryMap::SBUS_PS1_Start) && ((mem & 0x1FFFFFFF) < EEMemoryMap::SBUS_PS1_End)) {
return PGIFr((mem & 0x1FFFFFFF));
}
// WARNING: this code is never executed anymore due to previous condition.
// It requires investigation of what to do.
if ((mem & 0x1000ff00) == 0x1000f300)
{
int ret = 0;
@ -139,14 +146,21 @@ mem32_t __fastcall _hwRead32(u32 mem)
switch( mem )
{
case SIO_ISR:
case SBUS_F260:
case 0x1000f410:
case MCH_RICM:
return 0;
case SBUS_F240:
#if PSX_EXTRALOGS
DevCon.Warning("Read SBUS_F240 %x ", psHu32(SBUS_F240));
#endif
return psHu32(SBUS_F240) | 0xF0000102;
case SBUS_F260:
#if PSX_EXTRALOGS
DevCon.Warning("Read SBUS_F260 %x ", psHu32(SBUS_F260));
#endif
return psHu32(SBUS_F260);
case MCH_DRD:
if( !((psHu32(MCH_RICM) >> 6) & 0xF) )
{
@ -347,6 +361,14 @@ void __fastcall _hwRead128(u32 mem, mem128_t* result )
ZeroQWC( result );
break;
case 0x0F:
// todo: psx mode: this is new
if (((mem & 0x1FFFFFFF) >= EEMemoryMap::SBUS_PS1_Start) && ((mem & 0x1FFFFFFF) < EEMemoryMap::SBUS_PS1_End)) {
PGIFrQword((mem & 0x1FFFFFFF), result);
return;
}
// WARNING: this code is never executed anymore due to previous condition.
// It requires investigation of what to do.
if ((mem & 0xffffff00) == 0x1000f300)
{
DevCon.Warning("128bit read from %x wibble", mem);

36
pcsx2/HwWrite.cpp
View File

@ -22,6 +22,8 @@
#include "ps2/HwInternal.h"
#include "ps2/eeHwTraceLog.inl"
#include "ps2/pgif.h"
using namespace R5900;
// Shift the middle 8 bits (bits 4-12) into the lower 8 bits.
@ -47,7 +49,11 @@ void __fastcall _hwWrite32( u32 mem, u32 value )
#if PSX_EXTRALOGS
if ((mem & 0x1000ff00) == 0x1000f300) DevCon.Warning("32bit Write to SIF Register %x value %x", mem, value);
//if ((mem & 0x1000ff00) == 0x1000f200) DevCon.Warning("Write to SIF Register %x value %x", mem, value);
// todo: psx mode: this is new
if (((mem & 0x1FFFFFF0) == 0x1000f010) || ((mem & 0x1FFFFFF0) == 0x1000f010)) Console.WriteLn("EE ###INTC hwWR 0x%08X = 0x%08X PC=%08X ", mem, value, cpuRegs.pc);
#endif
switch (page)
{
case 0x00: if (!rcntWrite32<0x00>(mem, value)) return; break;
@ -172,7 +178,10 @@ void __fastcall _hwWrite32( u32 mem, u32 value )
psHu32(mem) &= ~value;
return;
mcase(SBUS_F240):
mcase(SBUS_F240) :
#if PSX_EXTRALOGS
DevCon.Warning("Write SBUS_F240 %x ", value);
#endif
if(!(value & 0x100))
psHu32(mem) &= ~0x100;
else
@ -180,9 +189,14 @@ void __fastcall _hwWrite32( u32 mem, u32 value )
return;
mcase(SBUS_F260):
psHu32(mem) = 0;
#if PSX_EXTRALOGS
DevCon.Warning("Write SBUS_F260 %x ", psHu32(SBUS_F260));
#endif
psHu32(mem) = value;
return;
// TODO: psx handling is done in the default case. Keep the code until we decide if we decide which interface to use (sif2/Pgif dma)
#if 0
mcase(SBUS_F300) :
psxHu32(0x1f801814) = value;
/*
@ -211,6 +225,8 @@ void __fastcall _hwWrite32( u32 mem, u32 value )
mcase(SBUS_F380) :
psHu32(mem) = value;
return;
#endif
mcase(MCH_RICM)://MCH_RICM: x:4|SA:12|x:5|SDEV:1|SOP:4|SBC:1|SDEV:5
if ((((value >> 16) & 0xFFF) == 0x21) && (((value >> 6) & 0xF) == 1) && (((psHu32(0xf440) >> 7) & 1) == 0))//INIT & SRP=0
rdram_sdevid = 0; // if SIO repeater is cleared, reset sdevid
@ -225,6 +241,13 @@ void __fastcall _hwWrite32( u32 mem, u32 value )
mcase(DMAC_ENABLEW):
if (!dmacWrite32<0x0f>(DMAC_ENABLEW, value)) return;
default:
// TODO: psx add the real address in a sbus mcase
if (((mem & 0x1FFFFFFF) >= EEMemoryMap::SBUS_PS1_Start) && ((mem & 0x1FFFFFFF) < EEMemoryMap::SBUS_PS1_End)) {
PGIFw((mem & 0x1FFFFFFF), value);
return;
}
//mcase(SIO_ISR):
//mcase(0x1000f410):
// Mystery Regs! No one knows!?
@ -423,9 +446,16 @@ void __fastcall _hwWrite128(u32 mem, const mem128_t* srcval)
//WriteFIFO_IPUout(srcval);
}
return;
case 0x0F:
// todo: psx mode: this is new
if (((mem & 0x1FFFFFFF) >= EEMemoryMap::SBUS_PS1_Start) && ((mem & 0x1FFFFFFF) < EEMemoryMap::SBUS_PS1_End)) {
PGIFwQword((mem & 0x1FFFFFFF), (void*)srcval);
return;
}
default: break;
}