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microVU: 

- Fixed a Q/P instance bug. This fixed some graphical corruption in Haunting Ground, might fix some other games too.
- Minor Changes...

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1225 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes 2009-05-20 03:05:36 +00:00
parent faf535a461
commit 23c833e922
5 changed files with 20 additions and 19 deletions
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1
pcsx2/x86/microVU.h
View File

@ -115,7 +115,6 @@ struct microVU {
u8* startFunct; // Ptr Function to the Start code for recompiled programs
u8* exitFunct; // Ptr Function to the Exit code for recompiled programs
u32 code; // Contains the current Instruction
u32 iReg; // iReg (only used in recompilation, not execution)
u32 divFlag; // 1 instance of I/D flags
u32 VIbackup[2]; // Holds a backup of a VI reg if modified before a branch
u32 branch; // Holds branch compare result (IBxx) OR Holds address to Jump to (JALR/JR)

14
pcsx2/x86/microVU_Alloc.inl
View File

@ -29,7 +29,7 @@
#define getReg(reg, _reg_) { \
mVUloadReg<vuIndex>(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], _X_Y_Z_W); \
if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, _X_Y_Z_W); \
if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT2, _X_Y_Z_W); \
}
#define getZero(reg) { \
@ -83,12 +83,12 @@ microVUt(void) mVUallocFMAC2b(int& Ft) {
#define getReg3SS(reg, _reg_) { \
mVUloadReg<vuIndex>(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], (1 << (3 - _bc_))); \
if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, (1 << (3 - _bc_))); \
if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT2, (1 << (3 - _bc_))); \
}
#define getReg3(reg, _reg_) { \
mVUloadReg<vuIndex>(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], (1 << (3 - _bc_))); \
if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, (1 << (3 - _bc_))); \
if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT2, (1 << (3 - _bc_))); \
mVUunpack_xyzw<vuIndex>(reg, reg, 0); \
}
@ -135,7 +135,7 @@ microVUt(void) mVUallocFMAC3b(int& Fd) {
#define getReg4(reg, _reg_) { \
mVUloadReg<vuIndex>(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], _xyzw_ACC); \
if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, _xyzw_ACC); \
if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT2, _xyzw_ACC); \
}
#define getZero4(reg) { \
@ -204,7 +204,7 @@ microVUt(void) mVUallocFMAC5b(int& ACC, int& Fs) {
#define getIreg(reg, modXYZW) { \
MOV32MtoR(gprT1, (uptr)&mVU->regs->VI[REG_I].UL); \
SSE2_MOVD_R_to_XMM(reg, gprT1); \
if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, 8); \
if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT2, 8); \
if (!((_XYZW_SS && modXYZW) || (_X_Y_Z_W == 8))) { mVUunpack_xyzw<vuIndex>(reg, reg, 0); } \
}
@ -496,7 +496,7 @@ microVUt(void) mVUallocFMAC16b(int& ACCw, int& ACCr) {
#define getReg9(reg, _reg_) { \
mVUloadReg<vuIndex>(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], 1); \
if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, 1); \
if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT2, 1); \
mVUunpack_xyzw<vuIndex>(reg, reg, 0); \
}
@ -754,7 +754,7 @@ microVUt(void) mVUallocVIb(int GPRreg, int _reg_) {
} \
else { \
mVUloadReg<vuIndex>(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], (1 << (3 - _fxf_))); \
if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, (1 << (3 - _fxf_))); \
if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT2, (1 << (3 - _fxf_))); \
} \
}

16
pcsx2/x86/microVU_Compile.inl
View File

@ -135,16 +135,14 @@ microVUt(void) mVUsetCycles() {
tCycles(mVUregs.xgkick, mVUregsTemp.xgkick);
}
microVUt(void) mVUendProgram(int fStatus, int fMac, int fClip) {
microVUt(void) mVUendProgram(int qInst, int pInst, int fStatus, int fMac, int fClip) {
microVU* mVU = mVUx;
incCycles(100); // Ensures Valid P/Q instances (And sets all cycle data to 0)
mVUcycles -= 100;
// Save P/Q Regs
if (mVU->q) { SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, 0xe5); }
if (qInst) { SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, 0xe5); }
SSE_MOVSS_XMM_to_M32((uptr)&mVU->regs->VI[REG_Q].UL, xmmPQ);
if (vuIndex) {
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, mVU->p ? 3 : 2);
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, pInst ? 3 : 2);
SSE_MOVSS_XMM_to_M32((uptr)&mVU->regs->VI[REG_P].UL, xmmPQ);
}
@ -180,7 +178,7 @@ microVUt(void) mVUtestCycles() {
PUSH32R(gprR);
CALLFunc((uptr)mVUwarning);
POP32R(gprR);
mVUendProgram<vuIndex>(sI, 0, cI);
mVUendProgram<vuIndex>(0, 0, sI, 0, cI);
x86SetJ8(jmp8);
SUB32ItoM((uptr)&mVU->cycles, mVUcycles);
}
@ -345,9 +343,13 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
mVUprint("mVUcompile ebit");
if (x == (vuIndex?(0x3fff/8):(0xfff/8))) { Console::Error("microVU%d: Possible infinite compiling loop!", params vuIndex); }
incCycles(100); // Ensures Valid P/Q instances (And sets all cycle data to 0)
mVUcycles -= 100;
// Do E-bit end stuff here
mVUsetupRange<vuIndex>(xPC - 8);
mVUendProgram<vuIndex>(findFlagInst(xStatus, 0x7fffffff), findFlagInst(xMac, 0x7fffffff), findFlagInst(xClip, 0x7fffffff));
mVUendProgram<vuIndex>(mVU->q, mVU->p, findFlagInst(xStatus, 0x7fffffff), findFlagInst(xMac, 0x7fffffff), findFlagInst(xClip, 0x7fffffff));
return thisPtr; //ToDo: Save pipeline state?
}

4
pcsx2/x86/microVU_Lower.inl
View File

@ -70,7 +70,7 @@ microVUf(void) mVU_DIV() {
x86SetJ8(cjmp);
MOV32ItoM((uptr)&mVU->divFlag, 0); // Clear I/D flags
SSE_DIVSS_XMM_to_XMM(xmmFs, xmmFt);
mVUclamp1<vuIndex>(xmmFs, xmmFt, 8);
if (CHECK_VU_OVERFLOW) mVUclamp1<vuIndex>(xmmFs, xmmFt, 8);
x86SetJ8(djmp);
if (writeQ) SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, 0xe1);
@ -128,7 +128,7 @@ microVUf(void) mVU_RSQRT() {
djmp = JMP8(0);
x86SetJ8(ajmp);
SSE_DIVSS_XMM_to_XMM(xmmFs, xmmFt);
mVUclamp1<vuIndex>(xmmFs, xmmFt, 8);
if (CHECK_VU_OVERFLOW) mVUclamp1<vuIndex>(xmmFs, xmmFt, 8);
x86SetJ8(djmp);
if (writeQ) SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, 0xe1);

4
pcsx2/x86/microVU_Misc.inl
View File

@ -99,7 +99,7 @@ microVUx(void) mVUsaveReg(int reg, uptr offset, int xyzw, bool modXYZW) {
if (modXYZW && (xyzw == 8 || xyzw == 4 || xyzw == 2 || xyzw == 1)) {
mVUunpack_xyzw<vuIndex>(reg, reg, 0);
}
mVUmergeRegs<vuIndex>(xmmT2, reg, xyzw);
mVUmergeRegs(xmmT2, reg, xyzw);
SSE_MOVAPS_XMM_to_M128(offset, xmmT2);
return;*/
@ -158,7 +158,7 @@ microVUx(void) mVUsaveReg2(int reg, int gprReg, u32 offset, int xyzw) {
if (xyzw == 8 || xyzw == 4 || xyzw == 2 || xyzw == 1) {
mVUunpack_xyzw<vuIndex>(reg, reg, 0);
}
mVUmergeRegs<vuIndex>(xmmT2, reg, xyzw);
mVUmergeRegs(xmmT2, reg, xyzw);
SSE_MOVAPSRtoRm(gprReg, xmmT2, offset);
return;*/