mirror of https://github.com/PCSX2/pcsx2.git
Added a little OOP to the CPU detection code, and turned one monolithic cpu detection function into several isolated ones (isolated by what general info they detect).
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3136 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
19fb2ec775
commit
23857a0e16
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@ -17,82 +17,111 @@
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#include "x86emitter.h"
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// this is all that needs to be called and will fill up the below structs
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extern void cpudetectInit();
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// Returns the number of available logical CPUs (cores plus hyperthreaded cpus)
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extern void CountLogicalCores( int LogicalCoresPerPhysicalCPU, int PhysicalCoresPerPhysicalCPU );
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// --------------------------------------------------------------------------------------
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// x86CPU_INFO
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// --------------------------------------------------------------------------------------
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struct x86CPU_INFO
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enum x86VendorType
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{
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u32 FamilyID; // Processor Family
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u32 Model; // Processor Model
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u32 TypeID; // Processor Type
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u32 StepID; // Stepping ID
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x86Vendor_Intel=0,
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x86Vendor_AMD,
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x86Vendor_Unknown,
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};
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// --------------------------------------------------------------------------------------
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// x86capabilities
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// --------------------------------------------------------------------------------------
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class x86capabilities
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{
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public:
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bool isIdentified;
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u32 LogicalCoresPerPhysicalCPU;
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u32 PhysicalCoresPerPhysicalCPU;
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public:
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x86VendorType VendorID;
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uint FamilyID; // Processor Family
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uint Model; // Processor Model
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uint TypeID; // Processor Type
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uint StepID; // Stepping ID
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u32 Flags; // Feature Flags
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u32 Flags2; // More Feature Flags
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u32 EFlags; // Extended Feature Flags
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u32 EFlags2; // Extended Feature Flags pg2
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u32 PhysicalCores;
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u32 LogicalCores;
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char VendorName[16]; // Vendor/Creator ID
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char TypeName[20]; // cpu type
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char FamilyName[50]; // the original cpu name
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// Speed - speed of cpu in mhz
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// This is a rough "real" measure of the cpu speed, taken at application startup.
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// Not to be considered totally accurate: Power saving CPUs and SpeedStep can skew
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// results considerably.
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u32 Speed;
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// ----------------------------------------------------------------------------
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// x86 CPU Capabilities Section (all boolean flags!)
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// ----------------------------------------------------------------------------
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u32 hasFloatingPointUnit:1;
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u32 hasVirtual8086ModeEnhancements:1;
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u32 hasDebuggingExtensions:1;
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u32 hasPageSizeExtensions:1;
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u32 hasTimeStampCounter:1;
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u32 hasModelSpecificRegisters:1;
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u32 hasPhysicalAddressExtension:1;
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u32 hasCOMPXCHG8BInstruction:1;
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u32 hasAdvancedProgrammableInterruptController:1;
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u32 hasSEPFastSystemCall:1;
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u32 hasMemoryTypeRangeRegisters:1;
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u32 hasPTEGlobalFlag:1;
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u32 hasMachineCheckArchitecture:1;
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u32 hasConditionalMoveAndCompareInstructions:1;
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u32 hasFGPageAttributeTable:1;
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u32 has36bitPageSizeExtension:1;
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u32 hasProcessorSerialNumber:1;
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u32 hasCFLUSHInstruction:1;
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u32 hasDebugStore:1;
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u32 hasACPIThermalMonitorAndClockControl:1;
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u32 hasMultimediaExtensions:1;
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u32 hasFastStreamingSIMDExtensionsSaveRestore:1;
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u32 hasStreamingSIMDExtensions:1;
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u32 hasStreamingSIMD2Extensions:1;
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u32 hasSelfSnoop:1;
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u32 hasMultiThreading:1; // is TRUE for both multi-core and Hyperthreaded CPUs.
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u32 hasThermalMonitor:1;
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u32 hasIntel64BitArchitecture:1;
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u32 hasStreamingSIMD3Extensions:1;
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u32 hasSupplementalStreamingSIMD3Extensions:1;
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u32 hasStreamingSIMD4Extensions:1;
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u32 hasStreamingSIMD4Extensions2:1;
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u32 hasFloatingPointUnit :1;
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u32 hasVirtual8086ModeEnhancements :1;
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u32 hasDebuggingExtensions :1;
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u32 hasPageSizeExtensions :1;
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u32 hasTimeStampCounter :1;
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u32 hasModelSpecificRegisters :1;
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u32 hasPhysicalAddressExtension :1;
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u32 hasCOMPXCHG8BInstruction :1;
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u32 hasAdvancedProgrammableInterruptController :1;
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u32 hasSEPFastSystemCall :1;
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u32 hasMemoryTypeRangeRegisters :1;
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u32 hasPTEGlobalFlag :1;
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u32 hasMachineCheckArchitecture :1;
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u32 hasConditionalMoveAndCompareInstructions :1;
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u32 hasFGPageAttributeTable :1;
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u32 has36bitPageSizeExtension :1;
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u32 hasProcessorSerialNumber :1;
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u32 hasCFLUSHInstruction :1;
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u32 hasDebugStore :1;
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u32 hasACPIThermalMonitorAndClockControl :1;
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u32 hasMultimediaExtensions :1;
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u32 hasFastStreamingSIMDExtensionsSaveRestore :1;
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u32 hasStreamingSIMDExtensions :1;
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u32 hasStreamingSIMD2Extensions :1;
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u32 hasSelfSnoop :1;
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// AMD-specific CPU Features
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u32 hasMultimediaExtensionsExt:1;
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u32 hasAMD64BitArchitecture:1;
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u32 has3DNOWInstructionExtensionsExt:1;
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u32 has3DNOWInstructionExtensions:1;
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u32 hasStreamingSIMD4ExtensionsA:1;
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// is TRUE for both multi-core and Hyperthreaded CPUs.
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u32 hasMultiThreading :1;
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u32 hasThermalMonitor :1;
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u32 hasIntel64BitArchitecture :1;
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u32 hasStreamingSIMD3Extensions :1;
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u32 hasSupplementalStreamingSIMD3Extensions :1;
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u32 hasStreamingSIMD4Extensions :1;
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u32 hasStreamingSIMD4Extensions2 :1;
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// AMD-specific CPU Features
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u32 hasMultimediaExtensionsExt :1;
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u32 hasAMD64BitArchitecture :1;
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u32 has3DNOWInstructionExtensionsExt :1;
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u32 has3DNOWInstructionExtensions :1;
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u32 hasStreamingSIMD4ExtensionsA :1;
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// Core Counts!
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u32 PhysicalCores;
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u32 LogicalCores;
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public:
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x86capabilities()
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{
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isIdentified = false;
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VendorID = x86Vendor_Unknown;
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LogicalCoresPerPhysicalCPU = 1;
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PhysicalCoresPerPhysicalCPU = 1;
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}
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void Identify();
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void CountCores();
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wxString GetTypeName() const;
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u32 CalculateMHz() const;
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void SIMD_ExceptionTest();
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void SIMD_EstablishMXCSRmask();
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protected:
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s64 _CPUSpeedHz( u64 time ) const;
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void CountLogicalCores();
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};
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enum SSE_RoundMode
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@ -168,7 +197,7 @@ extern SSE_MXCSR MXCSR_Mask;
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//////////////////////////////////////////////////////////////////////////////////////////
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extern __aligned16 x86CPU_INFO x86caps;
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extern __aligned16 x86capabilities x86caps;
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extern bool g_EEFreezeRegs;
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@ -19,20 +19,20 @@
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// Note: Apparently this solution is Linux/Solaris only.
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// FreeBSD/OsX need something far more complicated (apparently)
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void CountLogicalCores( int LogicalCoresPerPhysicalCPU, int PhysicalCoresPerPhysicalCPU )
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void x86capabilities::CountLogicalCores()
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{
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const uint numCPU = sysconf( _SC_NPROCESSORS_ONLN );
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if( numCPU > 0 )
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{
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//isMultiCore = numCPU > 1;
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x86caps.LogicalCores = numCPU;
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x86caps.PhysicalCores = ( numCPU / LogicalCoresPerPhysicalCPU ) * PhysicalCoresPerPhysicalCPU;
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LogicalCores = numCPU;
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PhysicalCores = ( numCPU / LogicalCoresPerPhysicalCPU ) * PhysicalCoresPerPhysicalCPU;
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}
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else
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{
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// Indeterminate?
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x86caps.LogicalCores = 1;
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x86caps.PhysicalCores = 1;
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LogicalCores = 1;
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PhysicalCores = 1;
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}
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}
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@ -17,12 +17,12 @@
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#include "PrecompiledHeader.h"
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#include "cpudetect_internal.h"
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void CountLogicalCores( int LogicalCoresPerPhysicalCPU, int PhysicalCoresPerPhysicalCPU )
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void x86capabilities::CountLogicalCores()
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{
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DWORD vProcessCPUs;
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DWORD vSystemCPUs;
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x86caps.LogicalCores = 1;
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LogicalCores = 1;
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if( !GetProcessAffinityMask (GetCurrentProcess (),
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&vProcessCPUs, &vSystemCPUs) ) return;
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@ -36,11 +36,11 @@ void CountLogicalCores( int LogicalCoresPerPhysicalCPU, int PhysicalCoresPerPhys
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CPUs++;
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}
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x86caps.LogicalCores = CPUs;
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LogicalCores = CPUs;
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if( LogicalCoresPerPhysicalCPU > CPUs) // for 1-socket HTT-disabled machines
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LogicalCoresPerPhysicalCPU = CPUs;
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x86caps.PhysicalCores = ( CPUs / LogicalCoresPerPhysicalCPU ) * PhysicalCoresPerPhysicalCPU;
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PhysicalCores = ( CPUs / LogicalCoresPerPhysicalCPU ) * PhysicalCoresPerPhysicalCPU;
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}
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bool _test_instruction( void* pfnCall )
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@ -19,7 +19,11 @@
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using namespace x86Emitter;
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__aligned16 x86CPU_INFO x86caps;
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__aligned16 x86capabilities x86caps;
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// Recompiled code buffer for SSE and MXCSR feature testing.
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static __pagealigned u8 recSSE[__pagesize];
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static __pagealigned u8 targetFXSAVE[512];
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#ifdef __LINUX__
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# include <sys/time.h>
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@ -31,34 +35,71 @@ static const char* bool_to_char( bool testcond )
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return testcond ? "true" : "false";
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}
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static s64 CPUSpeedHz( u64 time )
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// Warning! We've had problems with the MXCSR detection code causing stack corruption in
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// MSVC PGO builds. The problem was fixed when I moved the MXCSR code to this function, and
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// moved the recSSE[] array to a global static (it was local to cpudetectInit). Commented
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// here in case the nutty crash ever re-surfaces. >_<
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void x86capabilities::SIMD_EstablishMXCSRmask()
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{
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if( !hasStreamingSIMDExtensions ) return;
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MXCSR_Mask.bitmask = 0xFFBF; // MMX/SSE default
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if( hasStreamingSIMD2Extensions )
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{
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// This is generally safe assumption, but FXSAVE is the "correct" way to
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// detect MXCSR masking features of the cpu, so we use it's result below
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// and override this.
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MXCSR_Mask.bitmask = 0xFFFF; // SSE2 features added
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}
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if( !CanEmitShit() ) return;
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// the fxsave buffer must be 16-byte aligned to avoid GPF. I just save it to an
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// unused portion of recSSE, since it has plenty of room to spare.
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HostSys::MemProtectStatic( recSSE, Protect_ReadWrite, true );
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xSetPtr( recSSE );
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xFXSAVE( targetFXSAVE );
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xRET();
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HostSys::MemProtectStatic( recSSE, Protect_ReadOnly, true );
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CallAddress( recSSE );
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u32 result = (u32&)targetFXSAVE[28]; // bytes 28->32 are the MXCSR_Mask.
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if( result != 0 )
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MXCSR_Mask.bitmask = result;
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}
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// Counts the number of cpu cycles executed over the requested number of PerformanceCounter
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// ticks. Returns that exact count.
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// For best results you should pick a period of time long enough to get a reading that won't
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// be prone to rounding error; but short enough that it'll be highly unlikely to be interrupted
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// by the operating system task switches.
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s64 x86capabilities::_CPUSpeedHz( u64 time ) const
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{
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u64 timeStart, timeStop;
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s64 startCycle, endCycle;
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if( ! x86caps.hasTimeStampCounter )
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if( ! hasTimeStampCounter )
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return 0;
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SingleCoreAffinity affinity_lock;
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// Align the cpu execution to a cpuTick boundary.
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do { timeStart = GetCPUTicks();
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do {
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timeStart = GetCPUTicks();
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startCycle = __rdtsc();
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} while( GetCPUTicks() == timeStart );
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do
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{
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timeStop = GetCPUTicks();
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startCycle = __rdtsc();
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} while( ( timeStop - timeStart ) == 0 );
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timeStart = timeStop;
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do
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{
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do {
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timeStop = GetCPUTicks();
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endCycle = __rdtsc();
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}
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while( ( timeStop - timeStart ) < time );
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} while( ( timeStop - timeStart ) < time );
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s64 cycleCount = endCycle - startCycle;
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s64 timeCount = timeStop - timeStart;
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@ -73,92 +114,111 @@ static s64 CPUSpeedHz( u64 time )
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return (s64)newCycleCount;
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}
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// Recompiled code buffer for SSE and MXCSR feature testing.
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static __pagealigned u8 recSSE[__pagesize];
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// Warning! We've had problems with the MXCSR detection code causing stack corruption in
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// MSVC PGO builds. The problem was fixed when I moved the MXCSR code to this function, and
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// moved the recSSE[] array to a global static (it was local to cpudetectInit). Commented
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// here in case the nutty crash ever re-surfaces. >_<
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void EstablishMXCSRmask()
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wxString x86capabilities::GetTypeName() const
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{
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if( !x86caps.hasStreamingSIMDExtensions ) return;
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MXCSR_Mask.bitmask = 0xFFBF; // MMX/SSE default
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if( x86caps.hasStreamingSIMD2Extensions )
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switch( TypeID )
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{
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// This is generally safe assumption, but FXSAVE is the "correct" way to
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// detect MXCSR masking features of the cpu, so we use it's result below
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// and override this.
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MXCSR_Mask.bitmask = 0xFFFF; // SSE2 features added
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case 0: return L"Standard OEM";
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case 1: return L"Overdrive";
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case 2: return L"Dual";
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case 3: return L"Reserved";
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default: return L"Unknown";
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}
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if( !CanEmitShit() ) return;
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// the fxsave buffer must be 16-byte aligned to avoid GPF. I just save it to an
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// unused portion of recSSE, since it has plenty of room to spare.
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xSetPtr( recSSE );
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xFXSAVE( recSSE + 1024 );
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xRET();
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CallAddress( recSSE );
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u32 result = (u32&)recSSE[1024+28]; // bytes 28->32 are the MXCSR_Mask.
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if( result != 0 )
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MXCSR_Mask.bitmask = result;
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}
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void cpudetectInit()
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void x86capabilities::CountCores()
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{
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Identify();
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s32 regs[ 4 ];
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u32 cmds;
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LogicalCoresPerPhysicalCPU = 0;
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PhysicalCoresPerPhysicalCPU = 1;
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// detect multicore for Intel cpu
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__cpuid( regs, 0 );
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cmds = regs[ 0 ];
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if( cmds >= 0x00000001 )
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LogicalCoresPerPhysicalCPU = ( regs[1] >> 16 ) & 0xff;
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if ((cmds >= 0x00000004) && (VendorID == x86Vendor_Intel))
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{
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__cpuid( regs, 0x00000004 );
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PhysicalCoresPerPhysicalCPU += ( regs[0] >> 26) & 0x3f;
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}
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__cpuid( regs, 0x80000000 );
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cmds = regs[ 0 ];
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// detect multicore for AMD cpu
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if ((cmds >= 0x80000008) && (VendorID == x86Vendor_AMD) )
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{
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__cpuid( regs, 0x80000008 );
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PhysicalCoresPerPhysicalCPU += ( regs[2] ) & 0xff;
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}
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if( !hasMultiThreading || LogicalCoresPerPhysicalCPU == 0 )
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LogicalCoresPerPhysicalCPU = 1;
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// This will assign values into LogicalCores and PhysicalCores
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CountLogicalCores();
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}
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static const char* tbl_x86vendors[] =
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{
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"GenuineIntel",
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"AuthenticAMD"
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"Unknown ",
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};
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// Performs all _cpuid-related activity. This fills *most* of the x86caps structure, except for
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// the cpuSpeed and the mxcsr masks. Those must be completed manually.
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void x86capabilities::Identify()
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{
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if( isIdentified ) return;
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isIdentified = true;
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s32 regs[ 4 ];
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u32 cmds;
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//AMD 64 STUFF
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u32 x86_64_8BITBRANDID;
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u32 x86_64_12BITBRANDID;
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memzero( x86caps.VendorName );
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x86caps.FamilyID = 0;
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x86caps.Model = 0;
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x86caps.TypeID = 0;
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x86caps.StepID = 0;
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x86caps.Flags = 0;
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x86caps.EFlags = 0;
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memzero( VendorName );
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__cpuid( regs, 0 );
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cmds = regs[ 0 ];
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((u32*)x86caps.VendorName)[ 0 ] = regs[ 1 ];
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((u32*)x86caps.VendorName)[ 1 ] = regs[ 3 ];
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((u32*)x86caps.VendorName)[ 2 ] = regs[ 2 ];
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((u32*)VendorName)[ 0 ] = regs[ 1 ];
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((u32*)VendorName)[ 1 ] = regs[ 3 ];
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((u32*)VendorName)[ 2 ] = regs[ 2 ];
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|
||||
u32 LogicalCoresPerPhysicalCPU = 0;
|
||||
u32 PhysicalCoresPerPhysicalCPU = 1;
|
||||
// Determine Vendor Specifics!
|
||||
// It's really not recommended that we base much (if anything) on CPU vendor names,
|
||||
// however it's currently necessary in order to gain a (pseudo)reliable count of cores
|
||||
// and threads used by the CPU (AMD and Intel can't agree on how to make this info available).
|
||||
|
||||
int& vid = (int&)VendorID;
|
||||
for( vid=0; vid<x86Vendor_Unknown; ++vid )
|
||||
{
|
||||
if( memcmp( VendorName, tbl_x86vendors[vid], 12 ) == 0 ) break;
|
||||
}
|
||||
|
||||
if ( cmds >= 0x00000001 )
|
||||
{
|
||||
__cpuid( regs, 0x00000001 );
|
||||
|
||||
x86caps.StepID = regs[ 0 ] & 0xf;
|
||||
x86caps.Model = (regs[ 0 ] >> 4) & 0xf;
|
||||
x86caps.FamilyID = (regs[ 0 ] >> 8) & 0xf;
|
||||
x86caps.TypeID = (regs[ 0 ] >> 12) & 0x3;
|
||||
StepID = regs[ 0 ] & 0xf;
|
||||
Model = (regs[ 0 ] >> 4) & 0xf;
|
||||
FamilyID = (regs[ 0 ] >> 8) & 0xf;
|
||||
TypeID = (regs[ 0 ] >> 12) & 0x3;
|
||||
x86_64_8BITBRANDID = regs[ 1 ] & 0xff;
|
||||
x86caps.Flags = regs[ 3 ];
|
||||
x86caps.Flags2 = regs[ 2 ];
|
||||
|
||||
LogicalCoresPerPhysicalCPU = ( regs[1] >> 16 ) & 0xff;
|
||||
}
|
||||
|
||||
// detect multicore for Intel cpu
|
||||
|
||||
if ((cmds >= 0x00000004) && !strcmp("GenuineIntel",x86caps.VendorName))
|
||||
{
|
||||
__cpuid( regs, 0x00000004 );
|
||||
PhysicalCoresPerPhysicalCPU += ( regs[0] >> 26) & 0x3f;
|
||||
Flags = regs[ 3 ];
|
||||
Flags2 = regs[ 2 ];
|
||||
}
|
||||
|
||||
__cpuid( regs, 0x80000000 );
|
||||
|
|
@ -168,111 +228,82 @@ void cpudetectInit()
|
|||
__cpuid( regs, 0x80000001 );
|
||||
|
||||
x86_64_12BITBRANDID = regs[1] & 0xfff;
|
||||
x86caps.EFlags2 = regs[ 2 ];
|
||||
x86caps.EFlags = regs[ 3 ];
|
||||
EFlags2 = regs[ 2 ];
|
||||
EFlags = regs[ 3 ];
|
||||
}
|
||||
|
||||
// detect multicore for AMD cpu
|
||||
memzero( FamilyName );
|
||||
__cpuid( (int*)FamilyName, 0x80000002);
|
||||
__cpuid( (int*)(FamilyName+16), 0x80000003);
|
||||
__cpuid( (int*)(FamilyName+32), 0x80000004);
|
||||
|
||||
if ((cmds >= 0x80000008) && !strcmp("AuthenticAMD",x86caps.VendorName))
|
||||
{
|
||||
__cpuid( regs, 0x80000008 );
|
||||
PhysicalCoresPerPhysicalCPU += ( regs[2] ) & 0xff;
|
||||
}
|
||||
hasFloatingPointUnit = ( Flags >> 0 ) & 1;
|
||||
hasVirtual8086ModeEnhancements = ( Flags >> 1 ) & 1;
|
||||
hasDebuggingExtensions = ( Flags >> 2 ) & 1;
|
||||
hasPageSizeExtensions = ( Flags >> 3 ) & 1;
|
||||
hasTimeStampCounter = ( Flags >> 4 ) & 1;
|
||||
hasModelSpecificRegisters = ( Flags >> 5 ) & 1;
|
||||
hasPhysicalAddressExtension = ( Flags >> 6 ) & 1;
|
||||
hasMachineCheckArchitecture = ( Flags >> 7 ) & 1;
|
||||
hasCOMPXCHG8BInstruction = ( Flags >> 8 ) & 1;
|
||||
hasAdvancedProgrammableInterruptController = ( Flags >> 9 ) & 1;
|
||||
hasSEPFastSystemCall = ( Flags >> 11 ) & 1;
|
||||
hasMemoryTypeRangeRegisters = ( Flags >> 12 ) & 1;
|
||||
hasPTEGlobalFlag = ( Flags >> 13 ) & 1;
|
||||
hasMachineCheckArchitecture = ( Flags >> 14 ) & 1;
|
||||
hasConditionalMoveAndCompareInstructions = ( Flags >> 15 ) & 1;
|
||||
hasFGPageAttributeTable = ( Flags >> 16 ) & 1;
|
||||
has36bitPageSizeExtension = ( Flags >> 17 ) & 1;
|
||||
hasProcessorSerialNumber = ( Flags >> 18 ) & 1;
|
||||
hasCFLUSHInstruction = ( Flags >> 19 ) & 1;
|
||||
hasDebugStore = ( Flags >> 21 ) & 1;
|
||||
hasACPIThermalMonitorAndClockControl = ( Flags >> 22 ) & 1;
|
||||
hasMultimediaExtensions = ( Flags >> 23 ) & 1; //mmx
|
||||
hasFastStreamingSIMDExtensionsSaveRestore = ( Flags >> 24 ) & 1;
|
||||
hasStreamingSIMDExtensions = ( Flags >> 25 ) & 1; //sse
|
||||
hasStreamingSIMD2Extensions = ( Flags >> 26 ) & 1; //sse2
|
||||
hasSelfSnoop = ( Flags >> 27 ) & 1;
|
||||
hasMultiThreading = ( Flags >> 28 ) & 1;
|
||||
hasThermalMonitor = ( Flags >> 29 ) & 1;
|
||||
hasIntel64BitArchitecture = ( Flags >> 30 ) & 1;
|
||||
|
||||
switch(x86caps.TypeID)
|
||||
{
|
||||
case 0:
|
||||
strcpy( x86caps.TypeName, "Standard OEM");
|
||||
break;
|
||||
case 1:
|
||||
strcpy( x86caps.TypeName, "Overdrive");
|
||||
break;
|
||||
case 2:
|
||||
strcpy( x86caps.TypeName, "Dual");
|
||||
break;
|
||||
case 3:
|
||||
strcpy( x86caps.TypeName, "Reserved");
|
||||
break;
|
||||
default:
|
||||
strcpy( x86caps.TypeName, "Unknown");
|
||||
break;
|
||||
}
|
||||
// -------------------------------------------------
|
||||
// --> SSE3 / SSSE3 / SSE4.1 / SSE 4.2 detection <--
|
||||
// -------------------------------------------------
|
||||
|
||||
#if 0
|
||||
// vendor identification, currently unneeded.
|
||||
// It's really not recommended that we base much (if anything) on CPU vendor names.
|
||||
// But the code is left in as an ifdef, for possible future reference.
|
||||
hasStreamingSIMD3Extensions = ( Flags2 >> 0 ) & 1; //sse3
|
||||
hasSupplementalStreamingSIMD3Extensions = ( Flags2 >> 9 ) & 1; //ssse3
|
||||
hasStreamingSIMD4Extensions = ( Flags2 >> 19 ) & 1; //sse4.1
|
||||
hasStreamingSIMD4Extensions2 = ( Flags2 >> 20 ) & 1; //sse4.2
|
||||
|
||||
int cputype=0; // Cpu type
|
||||
static const char* Vendor_Intel = "GenuineIntel";
|
||||
static const char* Vendor_AMD = "AuthenticAMD";
|
||||
// Ones only for AMDs:
|
||||
hasMultimediaExtensionsExt = ( EFlags >> 22 ) & 1; //mmx2
|
||||
hasAMD64BitArchitecture = ( EFlags >> 29 ) & 1; //64bit cpu
|
||||
has3DNOWInstructionExtensionsExt = ( EFlags >> 30 ) & 1; //3dnow+
|
||||
has3DNOWInstructionExtensions = ( EFlags >> 31 ) & 1; //3dnow
|
||||
hasStreamingSIMD4ExtensionsA = ( EFlags2 >> 6 ) & 1; //INSERTQ / EXTRQ / MOVNT
|
||||
|
||||
if( memcmp( x86caps.VendorName, Vendor_Intel, 12 ) == 0 ) { cputype = 0; } else
|
||||
if( memcmp( x86caps.VendorName, Vendor_AMD, 12 ) == 0 ) { cputype = 1; }
|
||||
|
||||
if ( x86caps.VendorName[ 0 ] == 'G' ) { cputype = 0; }
|
||||
if ( x86caps.VendorName[ 0 ] == 'A' ) { cputype = 1; }
|
||||
#endif
|
||||
|
||||
memzero( x86caps.FamilyName );
|
||||
__cpuid( (int*)x86caps.FamilyName, 0x80000002);
|
||||
__cpuid( (int*)(x86caps.FamilyName+16), 0x80000003);
|
||||
__cpuid( (int*)(x86caps.FamilyName+32), 0x80000004);
|
||||
|
||||
//capabilities
|
||||
x86caps.hasFloatingPointUnit = ( x86caps.Flags >> 0 ) & 1;
|
||||
x86caps.hasVirtual8086ModeEnhancements = ( x86caps.Flags >> 1 ) & 1;
|
||||
x86caps.hasDebuggingExtensions = ( x86caps.Flags >> 2 ) & 1;
|
||||
x86caps.hasPageSizeExtensions = ( x86caps.Flags >> 3 ) & 1;
|
||||
x86caps.hasTimeStampCounter = ( x86caps.Flags >> 4 ) & 1;
|
||||
x86caps.hasModelSpecificRegisters = ( x86caps.Flags >> 5 ) & 1;
|
||||
x86caps.hasPhysicalAddressExtension = ( x86caps.Flags >> 6 ) & 1;
|
||||
x86caps.hasMachineCheckArchitecture = ( x86caps.Flags >> 7 ) & 1;
|
||||
x86caps.hasCOMPXCHG8BInstruction = ( x86caps.Flags >> 8 ) & 1;
|
||||
x86caps.hasAdvancedProgrammableInterruptController = ( x86caps.Flags >> 9 ) & 1;
|
||||
x86caps.hasSEPFastSystemCall = ( x86caps.Flags >> 11 ) & 1;
|
||||
x86caps.hasMemoryTypeRangeRegisters = ( x86caps.Flags >> 12 ) & 1;
|
||||
x86caps.hasPTEGlobalFlag = ( x86caps.Flags >> 13 ) & 1;
|
||||
x86caps.hasMachineCheckArchitecture = ( x86caps.Flags >> 14 ) & 1;
|
||||
x86caps.hasConditionalMoveAndCompareInstructions = ( x86caps.Flags >> 15 ) & 1;
|
||||
x86caps.hasFGPageAttributeTable = ( x86caps.Flags >> 16 ) & 1;
|
||||
x86caps.has36bitPageSizeExtension = ( x86caps.Flags >> 17 ) & 1;
|
||||
x86caps.hasProcessorSerialNumber = ( x86caps.Flags >> 18 ) & 1;
|
||||
x86caps.hasCFLUSHInstruction = ( x86caps.Flags >> 19 ) & 1;
|
||||
x86caps.hasDebugStore = ( x86caps.Flags >> 21 ) & 1;
|
||||
x86caps.hasACPIThermalMonitorAndClockControl = ( x86caps.Flags >> 22 ) & 1;
|
||||
x86caps.hasMultimediaExtensions = ( x86caps.Flags >> 23 ) & 1; //mmx
|
||||
x86caps.hasFastStreamingSIMDExtensionsSaveRestore = ( x86caps.Flags >> 24 ) & 1;
|
||||
x86caps.hasStreamingSIMDExtensions = ( x86caps.Flags >> 25 ) & 1; //sse
|
||||
x86caps.hasStreamingSIMD2Extensions = ( x86caps.Flags >> 26 ) & 1; //sse2
|
||||
x86caps.hasSelfSnoop = ( x86caps.Flags >> 27 ) & 1;
|
||||
x86caps.hasMultiThreading = ( x86caps.Flags >> 28 ) & 1;
|
||||
x86caps.hasThermalMonitor = ( x86caps.Flags >> 29 ) & 1;
|
||||
x86caps.hasIntel64BitArchitecture = ( x86caps.Flags >> 30 ) & 1;
|
||||
|
||||
//that is only for AMDs
|
||||
x86caps.hasMultimediaExtensionsExt = ( x86caps.EFlags >> 22 ) & 1; //mmx2
|
||||
x86caps.hasAMD64BitArchitecture = ( x86caps.EFlags >> 29 ) & 1; //64bit cpu
|
||||
x86caps.has3DNOWInstructionExtensionsExt = ( x86caps.EFlags >> 30 ) & 1; //3dnow+
|
||||
x86caps.has3DNOWInstructionExtensions = ( x86caps.EFlags >> 31 ) & 1; //3dnow
|
||||
x86caps.hasStreamingSIMD4ExtensionsA = ( x86caps.EFlags2 >> 6 ) & 1; //INSERTQ / EXTRQ / MOVNT
|
||||
isIdentified = true;
|
||||
}
|
||||
|
||||
u32 x86capabilities::CalculateMHz() const
|
||||
{
|
||||
InitCPUTicks();
|
||||
u64 span = GetTickFrequency();
|
||||
|
||||
if( (span % 1000) < 400 ) // helps minimize rounding errors
|
||||
x86caps.Speed = (u32)( CPUSpeedHz( span / 1000 ) / 1000 );
|
||||
return (u32)( _CPUSpeedHz( span / 1000 ) / 1000 );
|
||||
else
|
||||
x86caps.Speed = (u32)( CPUSpeedHz( span / 500 ) / 2000 );
|
||||
|
||||
// --> SSE3 / SSSE3 / SSE4.1 / SSE 4.2 detection <--
|
||||
|
||||
x86caps.hasStreamingSIMD3Extensions = ( x86caps.Flags2 >> 0 ) & 1; //sse3
|
||||
x86caps.hasSupplementalStreamingSIMD3Extensions = ( x86caps.Flags2 >> 9 ) & 1; //ssse3
|
||||
x86caps.hasStreamingSIMD4Extensions = ( x86caps.Flags2 >> 19 ) & 1; //sse4.1
|
||||
x86caps.hasStreamingSIMD4Extensions2 = ( x86caps.Flags2 >> 20 ) & 1; //sse4.2
|
||||
return (u32)( _CPUSpeedHz( span / 500 ) / 2000 );
|
||||
}
|
||||
|
||||
// Special extended version of SIMD testning, which uses exceptions to double-check the presence
|
||||
// of SSE2/3/4 instructions. Useful if you don't trust cpuid (at least one report of an invalid
|
||||
// cpuid has been reported on a Core2 Quad -- the user fixed it by clearing his CMOS).
|
||||
//
|
||||
// Results of CPU
|
||||
void x86capabilities::SIMD_ExceptionTest()
|
||||
{
|
||||
HostSys::MemProtectStatic( recSSE, Protect_ReadWrite, true );
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
|
@ -299,6 +330,8 @@ void cpudetectInit()
|
|||
xMOVDQU( xmm1, ptr[ecx] );
|
||||
xRET();
|
||||
|
||||
HostSys::MemProtectStatic( recSSE, Protect_ReadOnly, true );
|
||||
|
||||
bool sse3_result = _test_instruction( recSSE ); // sse3
|
||||
bool ssse3_result = _test_instruction( funcSSSE3 );
|
||||
bool sse41_result = _test_instruction( funcSSE41 );
|
||||
|
|
@ -308,52 +341,32 @@ void cpudetectInit()
|
|||
// more reliable gauge of the cpu's actual ability. But since a difference in bit
|
||||
// and actual ability may represent a cmos/bios problem, we report it to the user.
|
||||
|
||||
if( sse3_result != !!x86caps.hasStreamingSIMD3Extensions )
|
||||
if( sse3_result != !!hasStreamingSIMD3Extensions )
|
||||
{
|
||||
Console.Warning( "SSE3 Detection Inconsistency: cpuid=%s, test_result=%s",
|
||||
bool_to_char( !!x86caps.hasStreamingSIMD3Extensions ), bool_to_char( sse3_result ) );
|
||||
bool_to_char( !!hasStreamingSIMD3Extensions ), bool_to_char( sse3_result ) );
|
||||
|
||||
x86caps.hasStreamingSIMD3Extensions = sse3_result;
|
||||
hasStreamingSIMD3Extensions = sse3_result;
|
||||
}
|
||||
|
||||
if( ssse3_result != !!x86caps.hasSupplementalStreamingSIMD3Extensions )
|
||||
if( ssse3_result != !!hasSupplementalStreamingSIMD3Extensions )
|
||||
{
|
||||
Console.Warning( "SSSE3 Detection Inconsistency: cpuid=%s, test_result=%s",
|
||||
bool_to_char( !!x86caps.hasSupplementalStreamingSIMD3Extensions ), bool_to_char( ssse3_result ) );
|
||||
bool_to_char( !!hasSupplementalStreamingSIMD3Extensions ), bool_to_char( ssse3_result ) );
|
||||
|
||||
x86caps.hasSupplementalStreamingSIMD3Extensions = ssse3_result;
|
||||
hasSupplementalStreamingSIMD3Extensions = ssse3_result;
|
||||
}
|
||||
|
||||
if( sse41_result != !!x86caps.hasStreamingSIMD4Extensions )
|
||||
if( sse41_result != !!hasStreamingSIMD4Extensions )
|
||||
{
|
||||
Console.Warning( "SSE4 Detection Inconsistency: cpuid=%s, test_result=%s",
|
||||
bool_to_char( !!x86caps.hasStreamingSIMD4Extensions ), bool_to_char( sse41_result ) );
|
||||
bool_to_char( !!hasStreamingSIMD4Extensions ), bool_to_char( sse41_result ) );
|
||||
|
||||
x86caps.hasStreamingSIMD4Extensions = sse41_result;
|
||||
hasStreamingSIMD4Extensions = sse41_result;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Establish MXCSR Mask...
|
||||
|
||||
// HACK! For some reason the "proper" fxsave code below causes some kind of stackframe
|
||||
// corruption in MSVC PGO builds. The culprit appears to be execution of FXSAVE itself,
|
||||
// since only by not executing FXSAVE is the crash avoided. (note: crash happens later
|
||||
// in SysDetect). Using a #pragma optimize("",off) also fixes it.
|
||||
//
|
||||
// Workaround: We assume the MXCSR mask from the settings of the CPU. SSE2 CPUs have
|
||||
// a full mask available. SSE and earlier CPUs have a few bits reserved (must be zero).
|
||||
|
||||
EstablishMXCSRmask();
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Core Counting!
|
||||
|
||||
if( !x86caps.hasMultiThreading || LogicalCoresPerPhysicalCPU == 0 )
|
||||
LogicalCoresPerPhysicalCPU = 1;
|
||||
|
||||
// This will assign values into x86caps.LogicalCores and PhysicalCores
|
||||
CountLogicalCores( LogicalCoresPerPhysicalCPU, PhysicalCoresPerPhysicalCPU );
|
||||
SIMD_EstablishMXCSRmask();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -116,6 +116,8 @@ void SysLogMachineCaps()
|
|||
|
||||
Console.WriteLn( Color_StrongBlack, "x86-32 Init:" );
|
||||
|
||||
u32 speed = x86caps.CalculateMHz();
|
||||
|
||||
Console.Indent().WriteLn(
|
||||
L"CPU vendor name = %s\n"
|
||||
L"FamilyID = %x\n"
|
||||
|
|
@ -127,9 +129,9 @@ void SysLogMachineCaps()
|
|||
L"x86EFlags = %8.8x",
|
||||
fromUTF8( x86caps.VendorName ).c_str(), x86caps.StepID,
|
||||
fromUTF8( x86caps.FamilyName ).Trim().Trim(false).c_str(),
|
||||
x86caps.Speed / 1000, x86caps.Speed % 1000,
|
||||
speed / 1000, speed % 1000,
|
||||
x86caps.PhysicalCores, x86caps.LogicalCores,
|
||||
fromUTF8( x86caps.TypeName ).c_str(),
|
||||
x86caps.GetTypeName().c_str(),
|
||||
x86caps.Flags, x86caps.Flags2,
|
||||
x86caps.EFlags
|
||||
);
|
||||
|
|
|
|||
|
|
@ -189,9 +189,9 @@ void Pcsx2App::ReadUserModeSettings()
|
|||
|
||||
void Pcsx2App::DetectCpuAndUserMode()
|
||||
{
|
||||
cpudetectInit();
|
||||
//x86caps.Identify();
|
||||
//x86caps.SIMD_EstablishMXCSRmask();
|
||||
x86caps.Identify();
|
||||
x86caps.CountCores();
|
||||
x86caps.SIMD_EstablishMXCSRmask();
|
||||
|
||||
if( !x86caps.hasMultimediaExtensions )
|
||||
{
|
||||
|
|
@ -413,6 +413,8 @@ typedef void (wxEvtHandler::*pxStuckThreadEventHandler)(pxMessageBoxEvent&);
|
|||
|
||||
bool Pcsx2App::OnInit()
|
||||
{
|
||||
InitCPUTicks();
|
||||
|
||||
#define pxAppMethodEventHandler(func) \
|
||||
(wxObjectEventFunction)(wxEventFunction)wxStaticCastEvent(pxInvokeAppMethodEventFunction, &func )
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue