mirror of https://github.com/PCSX2/pcsx2.git
fixed some bad VU1 opcodes (some opcodes didn't even return the correct register, so the correct result would end up in the wrong reg lol) also cleaned up some DMA code a tiny bit, and added FreezeXMMRegs() where it was needed.
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@194 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
cottonvibes
Gregory Hainaut
parent
d69dc9a554
commit
2356f75396
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@ -191,10 +191,12 @@ void psxDma10(u32 madr, u32 bcr, u32 chcr) {
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iopsifbusy[1] = 1;
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psHu32(0x1000F240) |= 0x4000;
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if (eesifbusy[1] == 1 && iopsifbusy[1] == 1) {
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FreezeXMMRegs(1);
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SIF1Dma();
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psHu32(0x1000F240) &= ~0x40;
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psHu32(0x1000F240) &= ~0x100;
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psHu32(0x1000F240) &= ~0x4000;
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FreezeXMMRegs(0);
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}
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}
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38
pcsx2/Sif.c
38
pcsx2/Sif.c
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@ -368,13 +368,10 @@ _inline void SIF1Dma()
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notDone = 1;
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do
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{
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if(eesifbusy[1] == 1) // If EE SIF1 is enabled
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{
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if ((psHu32(DMAC_CTRL) & 0xC0) == 0xC0) { // STS == fromSIF1
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SysPrintf("SIF1 stall control\n");
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}
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if ((psHu32(DMAC_CTRL) & 0xC0) == 0xC0) SysPrintf("SIF1 stall control\n"); // STS == fromSIF1
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if(sif1dma->qwc == 0) // If there's no more to transfer
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{
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@ -383,9 +380,7 @@ _inline void SIF1Dma()
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// Stop & signal interrupts on EE
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//sif1dma->chcr &= ~0x100;
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//hwDmacIrq(6);
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#ifdef SIF_LOG
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SIF_LOG("EE SIF1 End %x\n", sif1.end);
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#endif
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eesifbusy[1] = 0;
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notDone = 0;
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INT(6, cycles*BIAS);
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@ -406,48 +401,38 @@ _inline void SIF1Dma()
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}
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sif1.chain = 1;
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id = (ptag[0] >> 28) & 0x7;
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id = (ptag[0] >> 28) & 0x7;
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switch(id)
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{
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case 0: // refe
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#ifdef SIF_LOG
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SIF_LOG(" REFE %08X\n", ptag[1]);
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#endif
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sif1.end = 1;
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sif1dma->madr = ptag[1];
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sif1dma->tadr += 16;
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break;
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case 1: // cnt
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#ifdef SIF_LOG
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SIF_LOG(" CNT\n");
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#endif
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sif1dma->madr = sif1dma->tadr + 16;
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sif1dma->tadr = sif1dma->madr + (sif1dma->qwc << 4);
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break;
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case 2: // next
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#ifdef SIF_LOG
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SIF_LOG(" NEXT %08X\n", ptag[1]);
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#endif
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sif1dma->madr = sif1dma->tadr + 16;
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sif1dma->tadr = ptag[1];
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break;
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case 3: // ref
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case 4: // refs
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#ifdef SIF_LOG
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SIF_LOG(" REF %08X\n", ptag[1]);
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#endif
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sif1dma->madr = ptag[1];
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sif1dma->tadr += 16;
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break;
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case 7: // end
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#ifdef SIF_LOG
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SIF_LOG(" END\n");
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#endif
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sif1.end = 1;
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sif1dma->madr = sif1dma->tadr + 16;
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sif1dma->tadr = sif1dma->madr + (sif1dma->qwc << 4);
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@ -468,7 +453,6 @@ _inline void SIF1Dma()
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u32 *data;
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//notDone = 1;
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_dmaGetAddr(sif1dma, data, sif1dma->madr, 6);
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if(qwTransfer > (FIFO_SIF1_W-sif1.fifoSize)/4) // Copy part of sif1dma into FIFO
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@ -492,12 +476,9 @@ _inline void SIF1Dma()
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{*/
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int readSize = size;
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if(readSize > sif1.fifoSize)
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readSize = sif1.fifoSize;
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if(readSize > sif1.fifoSize) readSize = sif1.fifoSize;
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#ifdef SIF_LOG
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SIF_LOG(" IOP SIF doing transfer %04X to %08X\n", readSize, HW_DMA10_MADR);
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#endif
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SIF1read((u32*)PSXM(HW_DMA10_MADR), readSize);
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psxCpu->Clear(HW_DMA10_MADR, readSize);
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@ -513,9 +494,7 @@ _inline void SIF1Dma()
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if(sif1.tagMode & 0x80) // Stop on tag IRQ
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{
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// Tag interrupt
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#ifdef SIF_LOG
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SIF_LOG(" IOP SIF interrupt\n");
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#endif
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//HW_DMA10_CHCR &= ~0x01000000; //reset TR flag
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//psxDmaInterrupt2(3);
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iopsifbusy[1] = 0;
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@ -527,9 +506,7 @@ _inline void SIF1Dma()
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else if(sif1.tagMode & 0x40) // Stop on tag END
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{
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// End tag.
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#ifdef SIF_LOG
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SIF_LOG(" IOP SIF end\n");
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#endif
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//HW_DMA10_CHCR &= ~0x01000000; //reset TR flag
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//psxDmaInterrupt2(3);
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iopsifbusy[1] = 0;
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@ -541,12 +518,8 @@ _inline void SIF1Dma()
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else if(sif1.fifoSize >= 4) // Read a tag
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{
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struct sifData d;
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SIF1read((u32*)&d, 4);
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#ifdef SIF_LOG
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SIF_LOG(" IOP SIF dest chain tag madr:%08X wc:%04X id:%X irq:%d\n", d.data & 0xffffff, d.words, (d.data>>28)&7, (d.data>>31)&1);
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#endif
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HW_DMA10_MADR = d.data & 0xffffff;
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sif1.counter = d.words;
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sif1.tagMode = (d.data >> 24) & 0xFF;
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@ -554,8 +527,7 @@ _inline void SIF1Dma()
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}
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}
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}
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}while(notDone);
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} while (notDone);
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}
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_inline void sif0Interrupt() {
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@ -5228,22 +5228,25 @@ void recVUMI_WAITP(VURegs *VU, int info)
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}
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// in all EFU insts, EEREC_D is a temp reg
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void vuSqSumXYZ(int regd, int regs, int regtemp)
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void vuSqSumXYZ(int regd, int regs, int regtemp) // regd.x = x ^ 2 + y ^ 2 + z ^ 2
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{
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//SysPrintf("VU: SUMXYZ\n");
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if( cpucaps.hasStreamingSIMD4Extensions )
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{
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SSE_MOVAPS_XMM_to_XMM(regd, regs);
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if (CHECK_EXTRA_OVERFLOW) vuFloat2(regd, regtemp, 0x8);
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SSE4_DPPS_XMM_to_XMM(regd, regd, 0x71);
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}
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else
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{
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SSE_MOVAPS_XMM_to_XMM(regtemp, regs);
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if (CHECK_EXTRA_OVERFLOW) vuFloat2(regtemp, regd, 0x8);
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SSE_MULPS_XMM_to_XMM(regtemp, regtemp); // xyzw ^ 2
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if( cpucaps.hasStreamingSIMD3Extensions ) {
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SSE3_HADDPS_XMM_to_XMM(regd, regtemp);
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SSE_ADDPS_XMM_to_XMM(regd, regtemp); // regd.z = x+y+z
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SSE_MOVHLPS_XMM_to_XMM(regd, regd); // move to x
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SSE_ADDPS_XMM_to_XMM(regd, regtemp); // regd.z = x ^ 2 + y ^ 2 + z ^ 2
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SSE_MOVHLPS_XMM_to_XMM(regd, regd); // regd.x = regd.z
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}
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else {
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SSE_MOVSS_XMM_to_XMM(regd, regtemp);
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@ -5252,83 +5255,42 @@ void vuSqSumXYZ(int regd, int regs, int regtemp)
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SSE_SHUFPS_XMM_to_XMM(regtemp, regtemp, 0xD2); // wzxy -> wxyz
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SSE_ADDSS_XMM_to_XMM(regd, regtemp); // x ^ 2 + y ^ 2 + z ^ 2
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//SSE_SHUFPS_XMM_to_XMM(regtemp, regtemp, 0xC6);
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/* TODO: check if this code does the same thing as above code
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SSE_MOVHLPS_XMM_to_XMM(EEREC_D, EEREC_TEMP);
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SSE_ADDSS_XMM_to_XMM(EEREC_D, EEREC_TEMP);
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SSE_SHUFPS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP, 0x55);
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SSE_ADDSS_XMM_to_XMM(EEREC_D, EEREC_TEMP);
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*/
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}
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}
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//SysPrintf("SUMXYZ\n");
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}
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void recVUMI_ESADD( VURegs *VU, int info)
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{
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//SysPrintf("VU: ESADD\n");
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assert( VU == &VU1 );
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//SysPrintf("ESADD\n");
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if( EEREC_TEMP == EEREC_D ) { // special code to reset P (don't know if this is still useful!)
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SysPrintf("ESADD: Resetting P reg!!!\n");
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MOV32ItoM(VU_VI_ADDR(REG_P, 0), 0);
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return;
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}
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if( cpucaps.hasStreamingSIMD4Extensions )
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{
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SSE_MOVAPS_XMM_to_XMM(EEREC_TEMP, EEREC_S);
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SSE4_DPPS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP, 0x71);
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}
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else
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{
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SSE_MOVAPS_XMM_to_XMM(EEREC_TEMP, EEREC_S);
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SSE_MULPS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP);
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if( cpucaps.hasStreamingSIMD3Extensions ) {
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SSE3_HADDPS_XMM_to_XMM(EEREC_D, EEREC_TEMP);
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SSE_ADDPS_XMM_to_XMM(EEREC_D, EEREC_TEMP); // EEREC_D.z = x+y+z
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SSE_MOVHLPS_XMM_to_XMM(EEREC_D, EEREC_D); // move to x
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}
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else {
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SSE_MOVHLPS_XMM_to_XMM(EEREC_D, EEREC_TEMP);
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SSE_ADDSS_XMM_to_XMM(EEREC_D, EEREC_TEMP);
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SSE_SHUFPS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP, 0x55);
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SSE_ADDSS_XMM_to_XMM(EEREC_D, EEREC_TEMP);
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}
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}
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vuFloat2(EEREC_TEMP, EEREC_D, 0x8);
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_P, 0), EEREC_TEMP);
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vuSqSumXYZ(EEREC_D, EEREC_S, EEREC_TEMP);
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if (CHECK_OVERFLOW) SSE_MINSS_M32_to_XMM(EEREC_D, (uptr)g_maxvals); // Only need to do positive clamp since (x ^ 2 + y ^ 2 + z ^ 2) is positive
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_P, 0), EEREC_D);
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}
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const static PCSX2_ALIGNED16(u32 VU_ONE[4]) = {0x3f800000, 0xffffffff, 0xffffffff, 0xffffffff};
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void recVUMI_ERSADD( VURegs *VU, int info )
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{
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//SysPrintf("VU: ERSADD\n");
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assert( VU == &VU1 );
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// almost same as vuSqSumXYZ
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if( cpucaps.hasStreamingSIMD4Extensions )
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{
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SSE_MOVAPS_XMM_to_XMM(EEREC_TEMP, EEREC_S);
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SSE4_DPPS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP, 0x71);
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}
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else
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{
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SSE_MOVAPS_XMM_to_XMM(EEREC_TEMP, EEREC_S);
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SSE_MULPS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP);
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if( cpucaps.hasStreamingSIMD3Extensions ) {
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SSE3_HADDPS_XMM_to_XMM(EEREC_D, EEREC_TEMP);
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SSE_ADDPS_XMM_to_XMM(EEREC_D, EEREC_TEMP); // EEREC_D.z = x+y+z
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SSE_MOVHLPS_XMM_to_XMM(EEREC_D, EEREC_D); // move to x
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}
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else {
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SSE_MOVHLPS_XMM_to_XMM(EEREC_D, EEREC_TEMP);
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SSE_ADDSS_XMM_to_XMM(EEREC_D, EEREC_TEMP);
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SSE_SHUFPS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP, 0x55);
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SSE_ADDSS_XMM_to_XMM(EEREC_D, EEREC_TEMP);
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}
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}
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SSE_MOVSS_M32_to_XMM(EEREC_TEMP, (uptr)&VU->VF[0].UL[3]);
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vuSqSumXYZ(EEREC_D, EEREC_S, EEREC_TEMP);
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// don't use RCPSS (very bad precision)
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SSE_MOVSS_M32_to_XMM(EEREC_TEMP, (uptr)VU_ONE);
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SSE_DIVSS_XMM_to_XMM(EEREC_TEMP, EEREC_D);
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vuFloat2(EEREC_TEMP, EEREC_D, 0x8);
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if (CHECK_OVERFLOW) SSE_MINSS_M32_to_XMM(EEREC_TEMP, (uptr)g_maxvals); // Only need to do positive clamp since (x ^ 2 + y ^ 2 + z ^ 2) is positive
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_P, 0), EEREC_TEMP);
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}
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@ -5338,9 +5300,8 @@ void recVUMI_ELENG( VURegs *VU, int info )
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assert( VU == &VU1 );
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vuSqSumXYZ(EEREC_D, EEREC_S, EEREC_TEMP);
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if (CHECK_OVERFLOW) SSE_MINSS_M32_to_XMM(EEREC_D, (uptr)g_maxvals); // Only need to do positive clamp since (x ^ 2 + y ^ 2 + z ^ 2) is positive
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SSE_SQRTSS_XMM_to_XMM(EEREC_TEMP, EEREC_D);
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_P, 0), EEREC_TEMP);
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SSE_SQRTSS_XMM_to_XMM(EEREC_D, EEREC_D);
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_P, 0), EEREC_D);
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}
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void recVUMI_ERLENG( VURegs *VU, int info )
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@ -5349,9 +5310,8 @@ void recVUMI_ERLENG( VURegs *VU, int info )
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assert( VU == &VU1 );
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vuSqSumXYZ(EEREC_D, EEREC_S, EEREC_TEMP);
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if (CHECK_OVERFLOW) SSE_MINSS_M32_to_XMM(EEREC_D, (uptr)g_maxvals); // Only need to do positive clamp since (x ^ 2 + y ^ 2 + z ^ 2) is positive
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SSE_SQRTSS_XMM_to_XMM(EEREC_TEMP, EEREC_D); // sqrt(x^2 + y^2 + z^2)
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SSE_MOVSS_XMM_to_XMM(EEREC_D, EEREC_TEMP); // d <- sqrt(x^2 + y^2 + z^2)
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SSE_MOVSS_M32_to_XMM(EEREC_TEMP, (uptr)&VU->VF[0].UL[3]); // temp <- 1
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SSE_SQRTSS_XMM_to_XMM(EEREC_D, EEREC_D); // regd <- sqrt(x^2 + y^2 + z^2)
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SSE_MOVSS_M32_to_XMM(EEREC_TEMP, (uptr)VU_ONE); // temp <- 1
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SSE_DIVSS_XMM_to_XMM(EEREC_TEMP, EEREC_D); // temp = 1 / sqrt(x^2 + y^2 + z^2)
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if (CHECK_OVERFLOW) SSE_MINSS_M32_to_XMM(EEREC_TEMP, (uptr)g_maxvals); // Only need to do positive clamp
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_P, 0), EEREC_TEMP);
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