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okay GT4 should work fine now (for real :p) there was a bug in my RSQRT opcode that messed up the game, i just reverted it for now. 

anyways, remember you need to check the Extra Overflow + FPU Clamp Hacks to run GT4

git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@72 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
cottonvibes 2008-08-29 23:43:47 +00:00 committed by Gregory Hainaut
parent d18a21ad37
commit 22a2acba33
1 changed files with 26 additions and 43 deletions
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69
pcsx2/x86/iFPU.c
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@ -1035,63 +1035,46 @@ FPURECOMPILE_CONSTCODE(NEG_S, XMMINFO_WRITED|XMMINFO_READS);
void recRSQRT_S_xmm(int info) void recRSQRT_S_xmm(int info)
{ {
int t0reg = _allocTempXMMreg(XMMT_FPS, -1); int t0reg = _allocTempXMMreg(XMMT_FPS, -1);
SysPrintf("FPU: RSQRT \n");
switch(info & (PROCESS_EE_S|PROCESS_EE_T) ) { switch(info & (PROCESS_EE_S|PROCESS_EE_T) ) {
case PROCESS_EE_S: case PROCESS_EE_S:
if( EEREC_D == EEREC_S ) { if( EEREC_D == EEREC_S ) {
if (CHECK_EXTRA_OVERFLOW) { SSE_SQRTSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
ClampValues(t0reg);
ClampValues(EEREC_D);
SSE_SQRTSS_XMM_to_XMM(t0reg, t0reg);
}
else { SSE_SQRTSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]); }
SSE_DIVSS_XMM_to_XMM(EEREC_D, t0reg); SSE_DIVSS_XMM_to_XMM(EEREC_D, t0reg);
} }
else { else {
SSE_MOVSS_XMM_to_XMM(EEREC_D, EEREC_S); SSE_SQRTSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
if (CHECK_EXTRA_OVERFLOW) { SSE_MOVSS_XMM_to_XMM(EEREC_D, EEREC_S);
SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
ClampValues(t0reg);
ClampValues(EEREC_D);
SSE_SQRTSS_XMM_to_XMM(t0reg, t0reg);
}
else { SSE_SQRTSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]); }
SSE_DIVSS_XMM_to_XMM(EEREC_D, t0reg); SSE_DIVSS_XMM_to_XMM(EEREC_D, t0reg);
} }
break;
case PROCESS_EE_T: break;
SSE_MOVSS_M32_to_XMM(EEREC_D, (uptr)&fpuRegs.fpr[_Fs_]); case PROCESS_EE_T:
if (CHECK_EXTRA_OVERFLOW) { ClampValues(EEREC_T); ClampValues(EEREC_D); } SSE_SQRTSS_XMM_to_XMM(t0reg, EEREC_T);
SSE_SQRTSS_XMM_to_XMM(t0reg, EEREC_T); SSE_MOVSS_M32_to_XMM(EEREC_D, (uptr)&fpuRegs.fpr[_Fs_]);
SSE_DIVSS_XMM_to_XMM(EEREC_D, t0reg); SSE_DIVSS_XMM_to_XMM(EEREC_D, t0reg);
break; break;
default:
case (PROCESS_EE_S | PROCESS_EE_T): if( (info & PROCESS_EE_T) && (info & PROCESS_EE_S) ) {
if( EEREC_D == EEREC_S ) { if( EEREC_D == EEREC_T ){
if (CHECK_EXTRA_OVERFLOW) { ClampValues(EEREC_T); ClampValues(EEREC_D); } SSE_SQRTSS_XMM_to_XMM(t0reg, EEREC_T);
SSE_SQRTSS_XMM_to_XMM(t0reg, EEREC_T); SSE_MOVSS_XMM_to_XMM(EEREC_D, EEREC_S);
SSE_DIVSS_XMM_to_XMM(EEREC_D, t0reg); SSE_DIVSS_XMM_to_XMM(EEREC_D, t0reg);
} }
else { else if( EEREC_D == EEREC_S ){
SSE_SQRTSS_XMM_to_XMM(t0reg, EEREC_T);
SSE_DIVSS_XMM_to_XMM(EEREC_D, t0reg);
} else {
SSE_SQRTSS_XMM_to_XMM(t0reg, EEREC_T);
SSE_MOVSS_XMM_to_XMM(EEREC_D, EEREC_S); SSE_MOVSS_XMM_to_XMM(EEREC_D, EEREC_S);
if (CHECK_EXTRA_OVERFLOW) { ClampValues(EEREC_T); ClampValues(EEREC_D); } SSE_DIVSS_XMM_to_XMM(EEREC_D, t0reg);
SSE_SQRTSS_XMM_to_XMM(t0reg, EEREC_T); }
}else{
SSE_SQRTSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
SSE_MOVSS_M32_to_XMM(EEREC_D, (uptr)&fpuRegs.fpr[_Fs_]);
SSE_DIVSS_XMM_to_XMM(EEREC_D, t0reg); SSE_DIVSS_XMM_to_XMM(EEREC_D, t0reg);
} }
break;
default:
SSE_MOVSS_M32_to_XMM(EEREC_D, (uptr)&fpuRegs.fpr[_Fs_]);
if (CHECK_EXTRA_OVERFLOW) {
SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
ClampValues(t0reg);
ClampValues(EEREC_D);
SSE_SQRTSS_XMM_to_XMM(t0reg, t0reg);
}
else { SSE_SQRTSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]); }
SSE_DIVSS_XMM_to_XMM(EEREC_D, t0reg);
break; break;
} }
_freeXMMreg(t0reg); _freeXMMreg(t0reg);