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microVU: 

- Minor Changes. Shouldn't effect anything.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1315 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes 2009-06-04 00:24:49 +00:00
parent b792d0c50b
commit 21d9615871
3 changed files with 21 additions and 21 deletions
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8
pcsx2/x86/microVU_Alloc.inl
View File

@ -676,10 +676,10 @@ microVUt(void) mVUallocSFLAGc(int reg, int regT, int fInstance) {
u8 *pjmp;
XOR32RtoR(reg, reg);
mVUallocSFLAGa(regT, fInstance);
setBitSFLAG(0x000f, 0x0001); // Z Bit
setBitSFLAG(0x00f0, 0x0002); // S Bit
setBitSFLAG(0x0f00, 0x0040); // ZS Bit
setBitSFLAG(0xf000, 0x0080); // SS Bit
setBitSFLAG(0x0f00, 0x0001); // Z Bit
setBitSFLAG(0xf000, 0x0002); // S Bit
setBitSFLAG(0x000f, 0x0040); // ZS Bit
setBitSFLAG(0x00f0, 0x0080); // SS Bit
AND32ItoR(regT, 0xffff0000); // DS/DI/OS/US/D/I/O/U Bits
SHR32ItoR(regT, 14);
OR32RtoR(reg, regT);

8
pcsx2/x86/microVU_Execute.inl
View File

@ -44,12 +44,12 @@ microVUt(void) mVUdispatcherA(mV) {
MOV32MtoR(gprF0, (uptr)&mVU->regs->VI[REG_STATUS_FLAG].UL);
MOV32RtoR(gprF1, gprF0);
SHL32ItoR(gprF1, 3);
AND32ItoR(gprF1, 0x218);
SHR32ItoR(gprF1, 3);
AND32ItoR(gprF1, 0x18);
MOV32RtoR(gprF2, gprF0);
SHL32ItoR(gprF2, 5);
AND32ItoR(gprF2, 0x1000);
SHL32ItoR(gprF2, 11);
AND32ItoR(gprF2, 0x1800);
OR32RtoR (gprF1, gprF2);
MOV32RtoR(gprF3, gprF0);

26
pcsx2/x86/microVU_Lower.inl
View File

@ -523,7 +523,7 @@ mVUop(mVU_FSAND) {
pass1 { mVUanalyzeSflag(mVU, _It_); }
pass2 {
mVUallocSFLAGc(gprT1, gprT2, sFLAG.read);
AND16ItoR(gprT1, _Imm12_);
AND32ItoR(gprT1, _Imm12_);
mVUallocVIb(mVU, gprT1, _It_);
}
pass3 { mVUlog("FSAND vi%02d, $%x", _Ft_, _Imm12_); }
@ -534,7 +534,7 @@ mVUop(mVU_FSOR) {
pass1 { mVUanalyzeSflag(mVU, _It_); }
pass2 {
mVUallocSFLAGc(gprT1, gprT2, sFLAG.read);
OR16ItoR(gprT1, _Imm12_);
OR32ItoR(gprT1, _Imm12_);
mVUallocVIb(mVU, gprT1, _It_);
}
pass3 { mVUlog("FSOR vi%02d, $%x", _Ft_, _Imm12_); }
@ -546,24 +546,24 @@ mVUop(mVU_FSEQ) {
pass2 {
u8 *pjmp;
int imm = 0;
if (_Imm12_ & 0x0001) imm |= 0x000000f; // Z
if (_Imm12_ & 0x0002) imm |= 0x00000f0; // S
if (_Imm12_ & 0x0001) imm |= 0x0000f00; // Z
if (_Imm12_ & 0x0002) imm |= 0x000f000; // S
if (_Imm12_ & 0x0004) imm |= 0x0010000; // U
if (_Imm12_ & 0x0008) imm |= 0x0020000; // O
if (_Imm12_ & 0x0010) imm |= 0x0040000; // I
if (_Imm12_ & 0x0020) imm |= 0x0080000; // D
if (_Imm12_ & 0x0040) imm |= 0x0000f00; // ZS
if (_Imm12_ & 0x0080) imm |= 0x000f000; // SS
if (_Imm12_ & 0x0040) imm |= 0x000000f; // ZS
if (_Imm12_ & 0x0080) imm |= 0x00000f0; // SS
if (_Imm12_ & 0x0100) imm |= 0x0400000; // US
if (_Imm12_ & 0x0200) imm |= 0x0800000; // OS
if (_Imm12_ & 0x0400) imm |= 0x1000000; // IS
if (_Imm12_ & 0x0800) imm |= 0x2000000; // DS
mVUallocSFLAGa(gprT1, sFLAG.read);
setBitFSEQ(0x000f); // Z bit
setBitFSEQ(0x00f0); // S bit
setBitFSEQ(0x0f00); // ZS bit
setBitFSEQ(0xf000); // SS bit
setBitFSEQ(0x0f00); // Z bit
setBitFSEQ(0xf000); // S bit
setBitFSEQ(0x000f); // ZS bit
setBitFSEQ(0x00f0); // SS bit
XOR32ItoR(gprT1, imm);
SUB32ItoR(gprT1, 1);
SHR32ItoR(gprT1, 31);
@ -577,8 +577,8 @@ mVUop(mVU_FSSET) {
pass1 { mVUanalyzeFSSET(mVU); }
pass2 {
int sReg, imm = 0;
if (_Imm12_ & 0x0040) imm |= 0x0000f00; // ZS
if (_Imm12_ & 0x0080) imm |= 0x000f000; // SS
if (_Imm12_ & 0x0040) imm |= 0x000000f; // ZS
if (_Imm12_ & 0x0080) imm |= 0x00000f0; // SS
if (_Imm12_ & 0x0100) imm |= 0x0400000; // US
if (_Imm12_ & 0x0200) imm |= 0x0800000; // OS
if (_Imm12_ & 0x0400) imm |= 0x1000000; // IS
@ -587,7 +587,7 @@ mVUop(mVU_FSSET) {
if (!(sFLAG.doFlag || mVUinfo.doDivFlag)) {
mVUallocSFLAGa(sReg, sFLAG.lastWrite); // Get Prev Status Flag
}
AND32ItoR(sReg, 0xf00ff); // Keep Non-Sticky Bits
AND32ItoR(sReg, 0xfff00); // Keep Non-Sticky Bits
if (imm) OR32ItoR(sReg, imm);
}
pass3 { mVUlog("FSSET $%x", _Imm12_); }