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Set cpuTestTIMR to be called every branch again, and made some tweaks to the MTGS code. These changes *appear* to fix Final Fantasy crashes in r345. 

git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@346 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
Jake.Stine 2008-11-20 00:16:29 +00:00 committed by Gregory Hainaut
parent f6ecf0bd68
commit 20a69d222e
3 changed files with 22 additions and 19 deletions
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2
pcsx2/GS.cpp
View File

@ -957,8 +957,8 @@ static __forceinline void WRITERING_DMA(u32 *pMem, u32 qwc) {
}
else memcpy_fast(pgsmem, pMem, sizetoread);
GSRINGBUF_DONECOPY(pgsmem, sizetoread);
GSgifTransferDummy(2, pMem, qwc);
GSRINGBUF_DONECOPY(pgsmem, sizetoread);
}
}
else {

35
pcsx2/R5900.c
View File

@ -401,13 +401,22 @@ u32 s_iLastPERFCycle[2] = {0,0};
static __forceinline void _cpuTestTIMR()
{
// The interpreter and recompiler both re-calculate these values whenever they
// are read, so updating them at regular intervals is merely a common courtesy.
// For that reason they're part of the Counters event, since it's garaunteed
// to be called at least 100 times a second.
cpuRegs.CP0.n.Count += cpuRegs.cycle-s_iLastCOP0Cycle;
s_iLastCOP0Cycle = cpuRegs.cycle;
// Updating them more frequently is pointless and, in fact, they could
// just as well be updated 20 times a second if it were convenient to do so.
if ( (cpuRegs.CP0.n.Status.val & 0x8000) &&
cpuRegs.CP0.n.Count >= cpuRegs.CP0.n.Compare && cpuRegs.CP0.n.Count < cpuRegs.CP0.n.Compare+1000 ) {
SysPrintf("timr intr: %x, %x\n", cpuRegs.CP0.n.Count, cpuRegs.CP0.n.Compare);
cpuException(0x808000, cpuRegs.branch);
}
}
static __forceinline void _cpuTestPERF()
{
// fixme - The interpreter and recompiler both re-calculate these values
// whenever they are read, so updating them at regular intervals *should be*
// merely a common courtesy. But when I set them up to be called less
// frequently crashes happened. I'd like to figure out why someday. [Air]
if((cpuRegs.PERF.n.pccr & 0x800003E0) == 0x80000020) {
cpuRegs.PERF.n.pcr0 += cpuRegs.cycle-s_iLastPERFCycle[0];
@ -417,15 +426,6 @@ static __forceinline void _cpuTestTIMR()
cpuRegs.PERF.n.pcr1 += cpuRegs.cycle-s_iLastPERFCycle[1];
s_iLastPERFCycle[1] = cpuRegs.cycle;
}
cpuRegs.CP0.n.Count += cpuRegs.cycle-s_iLastCOP0Cycle;
s_iLastCOP0Cycle = cpuRegs.cycle;
if ( (cpuRegs.CP0.n.Status.val & 0x8000) &&
cpuRegs.CP0.n.Count >= cpuRegs.CP0.n.Compare && cpuRegs.CP0.n.Count < cpuRegs.CP0.n.Compare+1000 ) {
SysPrintf("timr intr: %x, %x\n", cpuRegs.CP0.n.Count, cpuRegs.CP0.n.Compare);
cpuException(0x808000, cpuRegs.branch);
}
}
// Maximum wait between branches. Lower values provide a tighter synchronization between
@ -457,9 +457,12 @@ static __forceinline void _cpuBranchTest_Shared()
if( cpuTestCycle( nextsCounter, nextCounter ) )
{
rcntUpdate();
_cpuTestTIMR();
}
_cpuTestPERF();
_cpuTestTIMR();
//#ifdef CPU_LOG
// cpuTestMissingHwInts();
//#endif

4
pcsx2/VifDma.c
View File

@ -1669,8 +1669,8 @@ static int Vif1TransDirectHL(u32 *data){
FreezeMMXRegs(1);
memcpy_fast(gsmem, (u32*)splittransfer[0], 16);
FreezeMMXRegs(0);
GSRINGBUF_DONECOPY(gsmem, 16);
GSgifTransferDummy(1, (u32*)splittransfer[0], 1);
GSRINGBUF_DONECOPY(gsmem, 16);
}
}
else {
@ -1714,8 +1714,8 @@ static int Vif1TransDirectHL(u32 *data){
FreezeMMXRegs(1);
memcpy_fast(gsmem, data, ret<<2);
FreezeMMXRegs(0);
GSRINGBUF_DONECOPY(gsmem, ret<<2);
GSgifTransferDummy(1, data, ret>>2);
GSRINGBUF_DONECOPY(gsmem, ret<<2);
}
}
else {