mirror of https://github.com/PCSX2/pcsx2.git
Set cpuTestTIMR to be called every branch again, and made some tweaks to the MTGS code. These changes *appear* to fix Final Fantasy crashes in r345.
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@346 a6443dda-0b58-4228-96e9-037be469359c
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@ -957,8 +957,8 @@ static __forceinline void WRITERING_DMA(u32 *pMem, u32 qwc) {
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}
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}
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else memcpy_fast(pgsmem, pMem, sizetoread);
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else memcpy_fast(pgsmem, pMem, sizetoread);
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GSRINGBUF_DONECOPY(pgsmem, sizetoread);
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GSgifTransferDummy(2, pMem, qwc);
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GSgifTransferDummy(2, pMem, qwc);
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GSRINGBUF_DONECOPY(pgsmem, sizetoread);
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}
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}
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}
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}
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else {
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else {
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@ -401,13 +401,22 @@ u32 s_iLastPERFCycle[2] = {0,0};
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static __forceinline void _cpuTestTIMR()
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static __forceinline void _cpuTestTIMR()
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{
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{
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// The interpreter and recompiler both re-calculate these values whenever they
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cpuRegs.CP0.n.Count += cpuRegs.cycle-s_iLastCOP0Cycle;
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// are read, so updating them at regular intervals is merely a common courtesy.
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s_iLastCOP0Cycle = cpuRegs.cycle;
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// For that reason they're part of the Counters event, since it's garaunteed
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// to be called at least 100 times a second.
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// Updating them more frequently is pointless and, in fact, they could
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if ( (cpuRegs.CP0.n.Status.val & 0x8000) &&
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// just as well be updated 20 times a second if it were convenient to do so.
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cpuRegs.CP0.n.Count >= cpuRegs.CP0.n.Compare && cpuRegs.CP0.n.Count < cpuRegs.CP0.n.Compare+1000 ) {
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SysPrintf("timr intr: %x, %x\n", cpuRegs.CP0.n.Count, cpuRegs.CP0.n.Compare);
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cpuException(0x808000, cpuRegs.branch);
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}
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}
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static __forceinline void _cpuTestPERF()
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{
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// fixme - The interpreter and recompiler both re-calculate these values
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// whenever they are read, so updating them at regular intervals *should be*
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// merely a common courtesy. But when I set them up to be called less
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// frequently crashes happened. I'd like to figure out why someday. [Air]
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if((cpuRegs.PERF.n.pccr & 0x800003E0) == 0x80000020) {
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if((cpuRegs.PERF.n.pccr & 0x800003E0) == 0x80000020) {
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cpuRegs.PERF.n.pcr0 += cpuRegs.cycle-s_iLastPERFCycle[0];
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cpuRegs.PERF.n.pcr0 += cpuRegs.cycle-s_iLastPERFCycle[0];
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@ -417,15 +426,6 @@ static __forceinline void _cpuTestTIMR()
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cpuRegs.PERF.n.pcr1 += cpuRegs.cycle-s_iLastPERFCycle[1];
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cpuRegs.PERF.n.pcr1 += cpuRegs.cycle-s_iLastPERFCycle[1];
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s_iLastPERFCycle[1] = cpuRegs.cycle;
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s_iLastPERFCycle[1] = cpuRegs.cycle;
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}
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}
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cpuRegs.CP0.n.Count += cpuRegs.cycle-s_iLastCOP0Cycle;
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s_iLastCOP0Cycle = cpuRegs.cycle;
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if ( (cpuRegs.CP0.n.Status.val & 0x8000) &&
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cpuRegs.CP0.n.Count >= cpuRegs.CP0.n.Compare && cpuRegs.CP0.n.Count < cpuRegs.CP0.n.Compare+1000 ) {
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SysPrintf("timr intr: %x, %x\n", cpuRegs.CP0.n.Count, cpuRegs.CP0.n.Compare);
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cpuException(0x808000, cpuRegs.branch);
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}
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}
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}
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// Maximum wait between branches. Lower values provide a tighter synchronization between
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// Maximum wait between branches. Lower values provide a tighter synchronization between
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@ -457,9 +457,12 @@ static __forceinline void _cpuBranchTest_Shared()
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if( cpuTestCycle( nextsCounter, nextCounter ) )
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if( cpuTestCycle( nextsCounter, nextCounter ) )
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{
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{
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rcntUpdate();
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rcntUpdate();
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_cpuTestTIMR();
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}
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}
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_cpuTestPERF();
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_cpuTestTIMR();
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//#ifdef CPU_LOG
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//#ifdef CPU_LOG
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// cpuTestMissingHwInts();
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// cpuTestMissingHwInts();
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//#endif
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//#endif
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@ -1669,8 +1669,8 @@ static int Vif1TransDirectHL(u32 *data){
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FreezeMMXRegs(1);
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FreezeMMXRegs(1);
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memcpy_fast(gsmem, (u32*)splittransfer[0], 16);
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memcpy_fast(gsmem, (u32*)splittransfer[0], 16);
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FreezeMMXRegs(0);
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FreezeMMXRegs(0);
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GSRINGBUF_DONECOPY(gsmem, 16);
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GSgifTransferDummy(1, (u32*)splittransfer[0], 1);
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GSgifTransferDummy(1, (u32*)splittransfer[0], 1);
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GSRINGBUF_DONECOPY(gsmem, 16);
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}
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}
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}
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}
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else {
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else {
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@ -1714,8 +1714,8 @@ static int Vif1TransDirectHL(u32 *data){
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FreezeMMXRegs(1);
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FreezeMMXRegs(1);
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memcpy_fast(gsmem, data, ret<<2);
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memcpy_fast(gsmem, data, ret<<2);
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FreezeMMXRegs(0);
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FreezeMMXRegs(0);
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GSRINGBUF_DONECOPY(gsmem, ret<<2);
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GSgifTransferDummy(1, data, ret>>2);
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GSgifTransferDummy(1, data, ret>>2);
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GSRINGBUF_DONECOPY(gsmem, ret<<2);
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}
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}
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}
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}
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else {
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else {
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