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VU Int: Some formatting/logging cleanup, optimise some variable placement

This commit is contained in:
refractionpcsx2 2021-09-06 14:58:49 +01:00
parent 83143bd42e
commit 1f50dd7496
5 changed files with 117 additions and 94 deletions
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8
pcsx2/VU.h
View File

@ -108,7 +108,6 @@ struct efuPipe
struct fmacPipe
{
int enable;
u32 regupper;
u32 reglower;
int flagreg;
@ -123,7 +122,6 @@ struct fmacPipe
struct ialuPipe
{
int enable;
int reg;
u32 sCycle;
u32 Cycle;
@ -156,6 +154,7 @@ struct __aligned16 VURegs
u32 branchpc;
u32 delaybranchpc;
bool takedelaybranch;
u32 ebit;
u32 pending_q;
u32 pending_p;
@ -174,13 +173,12 @@ struct __aligned16 VURegs
u8* Mem;
u8* Micro;
u32 xgkickenable;
bool xgkickenable;
bool xgkickendpacket;
u32 xgkickaddr;
u32 xgkickdiff;
u32 xgkicksizeremaining;
u32 xgkicklastcycle;
u32 xgkickendpacket;
u32 ebit;
u8 VIBackupCycles;
u32 VIOldValue;

84
pcsx2/VU0microInterp.cpp
View File

@ -40,26 +40,22 @@ static void _vu0Exec(VURegs* VU)
{
_VURegsNum lregs;
_VURegsNum uregs;
VECTOR _VF;
VECTOR _VFc;
REG_VI _VI;
REG_VI _VIc;
u32 *ptr;
int vfreg;
int vireg;
int discard=0;
ptr = (u32*)&VU->Micro[VU->VI[REG_TPC].UL];
VU->VI[REG_TPC].UL+=8;
if (ptr[1] & 0x40000000) {
if (ptr[1] & 0x40000000) // E flag
{
VU->ebit = 2;
}
if (ptr[1] & 0x20000000) { /* M flag */
if (ptr[1] & 0x20000000) // M flag
{
VU->flags|= VUFLAG_MFLAGSET;
// Console.WriteLn("fixme: M flag set");
}
if (ptr[1] & 0x10000000) { /* D flag */
if (ptr[1] & 0x10000000) // D flag
{
if (VU0.VI[REG_FBRST].UL & 0x4) {
VU0.VI[REG_VPU_STAT].UL|= 0x2;
hwIntcIrq(INTC_VU0);
@ -67,7 +63,8 @@ static void _vu0Exec(VURegs* VU)
}
}
if (ptr[1] & 0x08000000) { /* T flag */
if (ptr[1] & 0x08000000) // T flag
{
if (VU0.VI[REG_FBRST].UL & 0x8) {
VU0.VI[REG_VPU_STAT].UL|= 0x4;
hwIntcIrq(INTC_VU0);
@ -78,7 +75,7 @@ static void _vu0Exec(VURegs* VU)
VU->code = ptr[1];
VU0regs_UPPER_OPCODE[VU->code & 0x3f](&uregs);
lregs.cycles = 0;
u32 cyclesBeforeOp = VU0.cycle-1;
_vuTestUpperStalls(VU, &uregs);
@ -98,8 +95,16 @@ static void _vu0Exec(VURegs* VU)
}
else
{
VU->code = ptr[0];
VECTOR _VF;
VECTOR _VFc;
REG_VI _VI;
REG_VI _VIc;
int vfreg = 0;
int vireg = 0;
int discard = 0;
VU->code = ptr[0];
lregs.cycles = 0;
VU0regs_LOWER_OPCODE[VU->code >> 25](&lregs);
_vuTestLowerStalls(VU, &lregs);
@ -108,25 +113,30 @@ static void _vu0Exec(VURegs* VU)
VU->VIBackupCycles -= std::min((u8)(VU0.cycle - cyclesBeforeOp), VU->VIBackupCycles);
vu0branch = lregs.pipe == VUPIPE_BRANCH;
vfreg = 0; vireg = 0;
if (uregs.VFwrite) {
if (lregs.VFwrite == uregs.VFwrite) {
if (uregs.VFwrite)
{
if (lregs.VFwrite == uregs.VFwrite)
{
// Console.Warning("*PCSX2*: Warning, VF write to the same reg in both lower/upper cycle");
discard = 1;
}
if (lregs.VFread0 == uregs.VFwrite ||
lregs.VFread1 == uregs.VFwrite) {
lregs.VFread1 == uregs.VFwrite)
{
// Console.WriteLn("saving reg %d at pc=%x", i, VU->VI[REG_TPC].UL);
_VF = VU->VF[uregs.VFwrite];
vfreg = uregs.VFwrite;
}
}
if (uregs.VIread & (1 << REG_CLIP_FLAG)) {
if (lregs.VIwrite & (1 << REG_CLIP_FLAG)) {
Console.Warning("*PCSX2*: Warning, VI write to the same reg in both lower/upper cycle");
if (uregs.VIread & (1 << REG_CLIP_FLAG))
{
if (lregs.VIwrite & (1 << REG_CLIP_FLAG))
{
//Console.Warning("*PCSX2*: Warning, VI write to the same reg in both lower/upper cycle");
discard = 1;
}
if (lregs.VIread & (1 << REG_CLIP_FLAG)) {
if (lregs.VIread & (1 << REG_CLIP_FLAG))
{
_VI = VU0.VI[REG_CLIP_FLAG];
vireg = REG_CLIP_FLAG;
}
@ -134,22 +144,27 @@ static void _vu0Exec(VURegs* VU)
_vu0ExecUpper(VU, ptr);
if (discard == 0) {
if (vfreg) {
if (discard == 0)
{
if (vfreg)
{
_VFc = VU->VF[vfreg];
VU->VF[vfreg] = _VF;
}
if (vireg) {
if (vireg)
{
_VIc = VU->VI[vireg];
VU->VI[vireg] = _VI;
}
_vu0ExecLower(VU, ptr);
if (vfreg) {
if (vfreg)
{
VU->VF[vfreg] = _VFc;
}
if (vireg) {
if (vireg)
{
VU->VI[vireg] = _VIc;
}
}
@ -161,23 +176,26 @@ static void _vu0Exec(VURegs* VU)
_vuAddUpperStalls(VU, &uregs);
_vuAddLowerStalls(VU, &lregs);
if (VU->branch > 0) {
if (VU->branch-- == 1) {
if (VU->branch > 0)
{
if (VU->branch-- == 1)
{
VU->VI[REG_TPC].UL = VU->branchpc;
if(VU->takedelaybranch)
{
VU->branch = 1;
{
DevCon.Warning("VU0 - Branch/Jump in Delay Slot");
VU->branch = 1;
VU->branchpc = VU->delaybranchpc;
VU->delaybranchpc = 0;
VU->takedelaybranch = false;
}
}
}
if( VU->ebit > 0 ) {
if( VU->ebit-- == 1 ) {
if(VU->ebit > 0)
{
if(VU->ebit-- == 1)
{
VU->VIBackupCycles = 0;
_vuFlushAll(VU);
VU0.VI[REG_VPU_STAT].UL&= ~0x1; /* E flag */

57
pcsx2/VU1microInterp.cpp
View File

@ -47,24 +47,17 @@ static void _vu1Exec(VURegs* VU)
{
_VURegsNum lregs;
_VURegsNum uregs;
VECTOR _VF;
VECTOR _VFc;
REG_VI _VI;
REG_VI _VIc;
u32* ptr;
int vfreg;
int vireg;
int discard = 0;
ptr = (u32*)&VU->Micro[VU->VI[REG_TPC].UL];
VU->VI[REG_TPC].UL += 8;
if (ptr[1] & 0x40000000)
{ /* E flag */
if (ptr[1] & 0x40000000) // E flag
{
VU->ebit = 2;
}
if (ptr[1] & 0x10000000)
{ /* D flag */
if (ptr[1] & 0x10000000) // D flag
{
if (VU0.VI[REG_FBRST].UL & 0x400)
{
VU0.VI[REG_VPU_STAT].UL |= 0x200;
@ -72,8 +65,8 @@ static void _vu1Exec(VURegs* VU)
VU->ebit = 1;
}
}
if (ptr[1] & 0x08000000)
{ /* T flag */
if (ptr[1] & 0x08000000) // T flag
{
if (VU0.VI[REG_FBRST].UL & 0x800)
{
VU0.VI[REG_VPU_STAT].UL |= 0x400;
@ -88,7 +81,7 @@ static void _vu1Exec(VURegs* VU)
VU1regs_UPPER_OPCODE[VU->code & 0x3f](&uregs);
u32 cyclesBeforeOp = VU1.cycle-1;
lregs.cycles = 0;
_vuTestUpperStalls(VU, &uregs);
/* check upper flags */
@ -108,7 +101,16 @@ static void _vu1Exec(VURegs* VU)
}
else
{
VECTOR _VF;
VECTOR _VFc;
REG_VI _VI;
REG_VI _VIc;
int vfreg = 0;
int vireg = 0;
int discard = 0;
VU->code = ptr[0];
lregs.cycles = 0;
VU1regs_LOWER_OPCODE[VU->code >> 25](&lregs);
_vuTestLowerStalls(VU, &lregs);
@ -117,8 +119,6 @@ static void _vu1Exec(VURegs* VU)
if (VU->VIBackupCycles > 0)
VU->VIBackupCycles-= std::min((u8)(VU1.cycle- cyclesBeforeOp), VU->VIBackupCycles);
vfreg = 0;
vireg = 0;
if (uregs.VFwrite)
{
if (lregs.VFwrite == uregs.VFwrite)
@ -176,6 +176,7 @@ static void _vu1Exec(VURegs* VU)
}
}
}
// Clear an FMAC read for use
if (uregs.pipe == VUPIPE_FMAC || lregs.pipe == VUPIPE_FMAC)
_vuClearFMAC(VU);
@ -190,10 +191,9 @@ static void _vu1Exec(VURegs* VU)
if (VU->takedelaybranch)
{
VU->branch = 1;
//DevCon.Warning("VU1 - Branch/Jump in Delay Slot");
VU->branch = 1;
VU->branchpc = VU->delaybranchpc;
VU->delaybranchpc = 0;
VU->takedelaybranch = false;
}
}
@ -209,24 +209,29 @@ static void _vu1Exec(VURegs* VU)
vif1Regs.stat.VEW = false;
}
}
if (VU->xgkickenable && (VU1.cycle - VU->xgkicklastcycle) >= 2)
{
if (VU->xgkicksizeremaining == 0)
{
IPU_LOG("Banana Reading next packet from %x", VU->xgkickaddr);
u32 size = gifUnit.GetGSPacketSize(GIF_PATH_1, VU->Mem, VU->xgkickaddr);
VU->xgkicksizeremaining = size & 0xFFFF;
VU->xgkickendpacket = size >> 31;
if (VU->xgkicksizeremaining == 0)
VU->xgkickenable = 0;
IPU_LOG("Banana New packet size %x", VU->xgkicksizeremaining);
{
VUM_LOG("Invalid GS packet size returned, cancelling XGKick");
VU->xgkickenable = false;
}
else
VUM_LOG("XGKICK New tag size %d bytes EOP %d", VU->xgkicksizeremaining, VU->xgkickendpacket);
}
u32 transfersize = std::min(VU->xgkicksizeremaining / 0x10, (VU1.cycle - VU->xgkicklastcycle) / 2);
transfersize = std::min(transfersize, VU->xgkickdiff / 0x10);
if (transfersize)
{
IPU_LOG("Banana Transferring %x bytes from %x size left %x", transfersize * 0x10, VU->xgkickaddr, VU->xgkicksizeremaining);
VUM_LOG("XGKICK Transferring %x bytes from %x size left %x", transfersize * 0x10, VU->xgkickaddr, VU->xgkicksizeremaining);
if ((transfersize * 0x10) > VU->xgkicksizeremaining)
gifUnit.gifPath[GIF_PATH_1].CopyGSPacketData(&VU->Mem[VU->xgkickaddr], transfersize * 0x10, true);
else
@ -235,16 +240,14 @@ static void _vu1Exec(VURegs* VU)
VU->xgkickaddr = (VU->xgkickaddr + (transfersize * 0x10)) & 0x3FFF;
VU->xgkicksizeremaining -= (transfersize * 0x10);
VU->xgkickdiff = 0x4000 - VU->xgkickaddr;
IPU_LOG("Banana next addr %x left size %x EOP %d", VU->xgkickaddr, VU->xgkicksizeremaining, VU->xgkickendpacket);
VU->xgkicklastcycle += std::max(transfersize * 2, 2U);
if (VU->xgkicksizeremaining || !VU->xgkickendpacket)
VU->xgkickenable = 1;
VUM_LOG("XGKICK next addr %x left size %x", VU->xgkickaddr, VU->xgkicksizeremaining);
else
{
VU->xgkickenable = 0;
IPU_LOG("Banana transfer finished");
VUM_LOG("XGKICK transfer finished");
VU->xgkickenable = false;
}
}
}

22
pcsx2/VUmicro.cpp
View File

@ -41,18 +41,24 @@ void BaseVUmicroCPU::ExecuteBlock(bool startUp)
{
if (VU1.xgkicksizeremaining == 0)
{
IPU_LOG("Banana Reading next packet from %x", VU1.xgkickaddr);
u32 size = gifUnit.GetGSPacketSize(GIF_PATH_1, VU1.Mem, VU1.xgkickaddr);
VU1.xgkicksizeremaining = size & 0xFFFF;
VU1.xgkickendpacket = size >> 31;
IPU_LOG("Banana New packet size %x", VU1.xgkicksizeremaining);
VUM_LOG("XGKICK New packet size %x", VU1.xgkicksizeremaining);
if (VU1.xgkicksizeremaining == 0)
{
VUM_LOG("Invalid GS packet size returned, cancelling XGKick");
VU1.xgkickenable = false;
return;
}
}
u32 transfersize = std::min(VU1.xgkicksizeremaining / 0x10, (cpuRegs.cycle - VU1.xgkicklastcycle) / 2);
transfersize = std::min(transfersize, VU1.xgkickdiff / 0x10);
if (transfersize)
{
IPU_LOG("Banana Transferring %x bytes from %x size left %x", transfersize * 0x10, VU1.xgkickaddr, VU1.xgkicksizeremaining);
VUM_LOG("XGKICK Transferring %x bytes from %x size left %x", transfersize * 0x10, VU1.xgkickaddr, VU1.xgkicksizeremaining);
if ((transfersize * 0x10) > VU1.xgkicksizeremaining)
gifUnit.gifPath[GIF_PATH_1].CopyGSPacketData(&VU1.Mem[VU1.xgkickaddr], transfersize * 0x10, true);
else
@ -61,20 +67,16 @@ void BaseVUmicroCPU::ExecuteBlock(bool startUp)
VU1.xgkickaddr = (VU1.xgkickaddr + (transfersize * 0x10)) & 0x3FFF;
VU1.xgkicksizeremaining -= (transfersize * 0x10);
VU1.xgkickdiff = 0x4000 - VU1.xgkickaddr;
IPU_LOG("Banana next addr %x left size %x EOP %d", VU1.xgkickaddr, VU1.xgkicksizeremaining, VU1.xgkickendpacket);
VU1.xgkicklastcycle += std::max(transfersize * 2, 2U);
if (VU1.xgkicksizeremaining || !VU1.xgkickendpacket)
VU1.xgkickenable = 1;
VUM_LOG("XGKICK next addr %x left size %x", VU1.xgkickaddr, VU1.xgkicksizeremaining);
else
{
VU1.xgkickenable = 0;
IPU_LOG("Banana transfer finished");
VU1.xgkickenable = false;
VUM_LOG("XGKICK transfer finished");
}
}
else
VU1.xgkickenable = 1;
}
}
return;

40
pcsx2/VUops.cpp
View File

@ -324,15 +324,8 @@ __fi void _vuTestLowerStalls(VURegs* VU, _VURegsNum* VUregsn)
__fi void _vuClearFMAC(VURegs* VU)
{
int i = VU->fmacwritepos;
VU->fmac[i].regupper =0;
VU->fmac[i].xyzwupper = 0;
VU->fmac[i].flagreg = 0;
VU->fmac[i].reglower = 0;
VU->fmac[i].xyzwlower = 0;
VU->fmac[i].macflag = 0;
VU->fmac[i].statusflag = 0;
VU->fmac[i].clipflag = 0;
memset(&VU->fmac[i], 0, sizeof(fmacPipe));
VU->fmaccount++;
}
@ -2317,17 +2310,25 @@ void _vuXGKICKFlush(VURegs* VU)
{
if (VU->xgkicksizeremaining == 0)
{
IPU_LOG("Banana Reading next packet");
u32 size = gifUnit.GetGSPacketSize(GIF_PATH_1, VU->Mem, VU->xgkickaddr);
VU->xgkicksizeremaining = size & 0xFFFF;
VU->xgkickendpacket = size >> 31;
VU->xgkickdiff = 0x4000 - VU->xgkickaddr;
if (VU->xgkicksizeremaining == 0)
{
VUM_LOG("Invalid GS packet size returned, cancelling XGKick");
VU->xgkickenable = false;
break;
}
else
VUM_LOG("XGKICK New tag size %d bytes EOP %d", VU->xgkicksizeremaining, VU->xgkickendpacket);
}
IPU_LOG("Banana Force Transferring %x bytes from %x size left %x", VU->xgkicksizeremaining, VU->xgkickaddr, VU->xgkicksizeremaining);
VUM_LOG("XGKICK Force Transferring %x bytes from %x size left %x", VU->xgkicksizeremaining, VU->xgkickaddr, VU->xgkicksizeremaining);
if (VU->xgkicksizeremaining > VU->xgkickdiff) {
IPU_LOG( "VU1 Int: XGkick Wrap!");
//VUM_LOG( "VU1 Int: XGkick Wrap!");
gifUnit.gifPath[GIF_PATH_1].CopyGSPacketData(&VU->Mem[VU->xgkickaddr], VU->xgkickdiff, true);
gifUnit.TransferGSPacketData(GIF_TRANS_XGKICK, &VU->Mem[0], VU->xgkicksizeremaining - VU->xgkickdiff, true);
}
@ -2341,11 +2342,14 @@ void _vuXGKICKFlush(VURegs* VU)
VU->cycle += VU->xgkicksizeremaining / 2;
VU->xgkicksizeremaining = 0;
IPU_LOG("Banana next addr %x left size %x EOP %d", VU->xgkickaddr, VU->xgkicksizeremaining, VU->xgkickendpacket);
if (!VU->xgkickendpacket)
VUM_LOG("XGKICK next addr %x left size %x EOP %d", VU->xgkickaddr, VU->xgkicksizeremaining, VU->xgkickendpacket);
else
VUM_LOG("XGKICK transfer finished");
}
VU->xgkickenable = 0;
VU->xgkickenable = false;
_vuTestPipes(VU);
}
@ -2359,15 +2363,13 @@ static __ri void _vuXGKICK(VURegs * VU)
u32 addr = (VU->VI[_Is_].US[0] & 0x3ff) * 16;
u32 diff = 0x4000 - addr;
VU->xgkickenable = 1;
VU->xgkickenable = true;
VU->xgkickaddr = addr;
VU->xgkickdiff = diff;
VU->xgkicksizeremaining = 0;
VU->xgkickendpacket = 0;
VU->xgkickendpacket = false;
VU->xgkicklastcycle = VU->cycle;
IPU_LOG("Banana XGKick size %x EOP %d addr %x", VU->xgkicksizeremaining, VU->xgkickendpacket, addr);
//_vuXGKICKFlush(VU);
//VU->cycle = oldcycle;
VUM_LOG("XGKICK size %x EOP %d addr %x", VU->xgkicksizeremaining, VU->xgkickendpacket, addr);
}
static __ri void _vuXTOP(VURegs * VU) {