mirror of https://github.com/PCSX2/pcsx2.git
microVU: Implemented some undocumented stuff which lets Champions Return to Arms get in-game.
The game still looks ugly, I'm not sure if its problems are gsdx or pcsx2. zeroGS just renders a black screen which it no help xD Note: I still need to optimize this fix. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1630 96395faa-99c1-11dd-bbfe-3dabce05a288
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@ -83,11 +83,12 @@ public:
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}
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else { // Can do Simple Search (Only Matches the Important Pipeline Stuff)
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for (int i = 0; i <= listI; i++) {
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if ((linkI->block->pState.q == pState->q)
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&& (linkI->block->pState.p == pState->p)
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&& (linkI->block->pState.vi15 == pState->vi15)
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&& (linkI->block->pState.flags == pState->flags)
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&& (linkI->block->pState.xgkick == pState->xgkick)
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if ((linkI->block->pState.q == pState->q)
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&& (linkI->block->pState.p == pState->p)
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&& (linkI->block->pState.vi15 == pState->vi15)
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&& (linkI->block->pState.flags == pState->flags)
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&& (linkI->block->pState.xgkick == pState->xgkick)
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&& (linkI->block->pState.viBackUp == pState->viBackUp)
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&& !(linkI->block->pState.needExactMatch & 5)) { return linkI->block; }
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linkI = linkI->next;
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}
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@ -356,10 +356,14 @@ microVUt(void) mVUanalyzeXGkick(mV, int Fs, int xCycles) {
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microVUt(void) analyzeBranchVI(mV, int xReg, bool &infoVar) {
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if (!xReg) return;
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int i;
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int iEnd = aMin(5, mVUcount);
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int iEnd = aMin(5, (mVUcount+1));
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int bPC = iPC;
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incPC2(-2);
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for (i = 0; i < iEnd; i++) {
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if (i == mVUcount) {
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if (mVUpBlock->pState.viBackUp == xReg) infoVar = 1;
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break;
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}
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if ((mVUlow.VI_write.reg == xReg) && mVUlow.VI_write.used) {
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if (mVUlow.readFlags || i == 5) break;
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if (i == 0) { incPC2(-2); continue; }
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@ -371,7 +375,7 @@ microVUt(void) analyzeBranchVI(mV, int xReg, bool &infoVar) {
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}
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if (i) {
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incPC2(2);
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mVUlow.backupVI = 1;
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if (!infoVar) mVUlow.backupVI = 1;
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iPC = bPC;
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infoVar = 1;
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DevCon::Status("microVU%d: Branch VI-Delay (%d) [%04x]", params getIndex, i, xPC);
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@ -162,6 +162,12 @@ microVUt(void) branchWarning(mV) {
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Console::Error("microVU%d Warning: Branch in E-bit/Branch delay slot! [%04x]", params mVU->index, xPC);
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mVUlow.isNOP = 1;
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}
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if (mVUinfo.isBdelay) { // Check if VI Reg Written to on Branch Delay
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if (mVUlow.VI_write.reg && mVUlow.VI_write.used) {
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mVUlow.backupVI = 1;
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mVUregs.viBackUp = mVUlow.VI_write.reg;
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}
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}
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}
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// Optimizes the End Pipeline State Removing Unnecessary Info
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@ -294,6 +300,7 @@ microVUt(void) mVUinitFirstPass(microVU* mVU, microBlock* &pBlock, uptr pState,
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mVUblock.x86ptrStart = thisPtr;
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pBlock = mVUblocks[mVUstartPC/2]->add(&mVUblock); // Add this block to block manager
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mVUpBlock = pBlock;
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mVUregs.viBackUp= 0;
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mVUregs.flags = 0;
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mVUflagInfo = 0;
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mVUsFlagHack = CHECK_VU_FLAGHACK;
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@ -40,6 +40,7 @@ __declspec(align(16)) struct microRegInfo { // Ordered for Faster Compares
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u8 p;
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u8 r;
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u8 xgkick;
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u8 viBackUp;
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u8 VI[16];
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regInfo VF[32];
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u8 flags; // clip x2 :: status x2
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