mirror of https://github.com/PCSX2/pcsx2.git
Emitter :Implemented Packed logical operations (PAND/POR/ANDxx/ORxx/etc), ADDxx/SUBxx/MULxx/DIVxx, and iRCPPS/iRCPSS.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1021 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
d91eb6d1c8
commit
1bc6795200
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@ -3859,7 +3859,6 @@ void recVUMI_JR( VURegs* vuu, s32 info )
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{
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int fsreg = _allocX86reg(-1, X86TYPE_VI|(s_vu?X86TYPE_VU1:0), _Fs_, MODE_READ);
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LEA32RStoR(EAX, fsreg, 3);
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CWDE();
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if( (s_pCurBlock->type & BLOCKTYPE_HASEOP) || s_vu == 0 ) MOV32RtoM(SuperVUGetVIAddr(REG_TPC, 0), EAX);
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@ -3876,7 +3875,6 @@ void recVUMI_JALR( VURegs* vuu, s32 info )
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int fsreg = _allocX86reg(-1, X86TYPE_VI|(s_vu?X86TYPE_VU1:0), _Fs_, MODE_READ);
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LEA32RStoR(EAX, fsreg, 3);
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CWDE(); // necessary, charlie and chocolate factory gives bad addrs, but graphics are ok
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if ( _Ft_ ) {
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_deleteX86reg(X86TYPE_VI|(s_vu?X86TYPE_VU1:0), _Ft_, 2);
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@ -87,9 +87,9 @@ __emitinline void writeXMMop( u8 opcode, const iRegister<T>& reg, const void* da
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}
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//////////////////////////////////////////////////////////////////////////////////////////
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//
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// Moves to/from high/low portions of an xmm register.
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// These instructions cannot be used in reg/reg form.
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//
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template< u8 Prefix, u8 Opcode >
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class MovhlImplAll
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{
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@ -114,3 +114,46 @@ public:
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MovapsImplAll() {} //GCC.
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};
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//////////////////////////////////////////////////////////////////////////////////////////
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// PLogicImplAll - Implements logic forms for MMX/SSE instructions, and can be used for
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// a few other various instruction too (anything which comes in simdreg,simdreg/ModRM forms).
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//
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template< u8 Opcode >
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class PLogicImplAll
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{
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public:
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template< typename T >
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__forceinline void operator()( const iRegisterSIMD<T>& to, const iRegisterSIMD<T>& from ) const
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{
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writeXMMop( 0x66, Opcode, to, from );
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}
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template< typename T >
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__forceinline void operator()( const iRegisterSIMD<T>& to, const void* from ) const
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{
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writeXMMop( 0x66, Opcode, to, from );
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}
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template< typename T >
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__noinline void operator()( const iRegisterSIMD<T>&, const ModSibBase& from ) const { writeXMMop( 0x66, Opcode, to, from ); }
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PLogicImplAll() {} //GCWho?
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};
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// ------------------------------------------------------------------------
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// For implementing SSE-only logic operations, like ANDPS/ANDPD
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template< u8 Prefix, u8 Opcode >
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class PLogicImplSSE
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{
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public:
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__forceinline void operator()( const iRegisterSSE& to, const iRegisterSSE& from ) const
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{
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writeXMMop( Prefix, Opcode, to, from );
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}
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__forceinline void operator()( const iRegisterSSE& to, const void* from ) const
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{
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writeXMMop( Prefix, Opcode, to, from );
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}
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__noinline void operator()( const iRegisterSSE&, const ModSibBase& from ) const { writeXMMop( Prefix, Opcode, to, from ); }
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PLogicImplSSE() {} //GCWho?
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};
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@ -753,6 +753,46 @@ const MovhlImplAll< 0, 0x12 > iMOVLPS;
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const MovhlImplAll< 0x66, 0x16 > iMOVHPD;
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const MovhlImplAll< 0x66, 0x12 > iMOVLPD;
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const PLogicImplAll<0xdb> iPAND;
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const PLogicImplAll<0xdf> iPANDN;
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const PLogicImplAll<0xeb> iPOR;
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const PLogicImplAll<0xef> iPXOR;
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const PLogicImplSSE<0x00,0x54> iANDPS;
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const PLogicImplSSE<0x66,0x54> iANDPD;
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const PLogicImplSSE<0x00,0x55> iANDNPS;
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const PLogicImplSSE<0x66,0x55> iANDNPD;
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const PLogicImplSSE<0x00,0x56> iORPS;
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const PLogicImplSSE<0x66,0x56> iORPD;
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const PLogicImplSSE<0x00,0x57> iXORPS;
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const PLogicImplSSE<0x66,0x57> iXORPD;
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const PLogicImplSSE<0x00,0x5c> iSUBPS;
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const PLogicImplSSE<0x66,0x5c> iSUBPD;
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const PLogicImplSSE<0xf3,0x5c> iSUBSS;
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const PLogicImplSSE<0xf2,0x5c> iSUBSD;
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const PLogicImplSSE<0x00,0x58> iADDPS;
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const PLogicImplSSE<0x66,0x58> iADDPD;
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const PLogicImplSSE<0xf3,0x58> iADDSS;
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const PLogicImplSSE<0xf2,0x58> iADDSD;
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const PLogicImplSSE<0x00,0x59> iMULPS;
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const PLogicImplSSE<0x66,0x59> iMULPD;
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const PLogicImplSSE<0xf3,0x59> iMULSS;
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const PLogicImplSSE<0xf2,0x59> iMULSD;
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const PLogicImplSSE<0x00,0x5e> iDIVPS;
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const PLogicImplSSE<0x66,0x5e> iDIVPD;
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const PLogicImplSSE<0xf3,0x5e> iDIVSS;
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const PLogicImplSSE<0xf2,0x5e> iDIVSD;
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// Compute Reciprocal Packed Single-Precision Floating-Point Values
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const PLogicImplSSE<0,0x53> iRCPPS;
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// Compute Reciprocal of Scalar Single-Precision Floating-Point Value
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const PLogicImplSSE<0xf3,0x53> iRCPSS;
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// Moves from XMM to XMM, with the *upper 64 bits* of the destination register
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// being cleared to zero.
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@ -40,42 +40,20 @@ emitterT void MOVD32RmtoMMX( x86MMXRegType to, x86IntRegType from, int offset )
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emitterT void MOVD32MMXtoR( x86IntRegType to, x86MMXRegType from ) { iMOVD( iRegister32(to), iRegisterMMX(from) ); }
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emitterT void MOVD32MMXtoRm( x86IntRegType to, x86MMXRegType from, int offset ) { iMOVD( ptr[iAddressReg(to)+offset], iRegisterMMX(from) ); }
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emitterT void PMOVMSKBMMXtoR(x86IntRegType to, x86MMXRegType from)
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{
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iPMOVMSKB( iRegister32(to), iRegisterMMX(from) );
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}
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emitterT void PMOVMSKBMMXtoR(x86IntRegType to, x86MMXRegType from) { iPMOVMSKB( iRegister32(to), iRegisterMMX(from) ); }
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#define DEFINE_LEGACY_LOGIC_OPCODE( mod ) \
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emitterT void P##mod##RtoR( x86MMXRegType to, x86MMXRegType from ) { iP##mod( iRegisterMMX(to), iRegisterMMX(from) ); } \
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emitterT void P##mod##MtoR( x86MMXRegType to, uptr from ) { iP##mod( iRegisterMMX(to), (void*)from ); } \
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emitterT void SSE2_P##mod##_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { iP##mod( iRegisterSSE(to), iRegisterSSE(from) ); } \
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emitterT void SSE2_P##mod##_M128_to_XMM( x86SSERegType to, uptr from ) { iP##mod( iRegisterSSE(to), (void*)from ); }
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DEFINE_LEGACY_LOGIC_OPCODE( AND )
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DEFINE_LEGACY_LOGIC_OPCODE( ANDN )
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DEFINE_LEGACY_LOGIC_OPCODE( OR )
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DEFINE_LEGACY_LOGIC_OPCODE( XOR )
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/* pand r64 to r64 */
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emitterT void PANDRtoR( x86MMXRegType to, x86MMXRegType from )
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{
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write16( 0xDB0F );
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ModRM( 3, to, from );
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}
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emitterT void PANDNRtoR( x86MMXRegType to, x86MMXRegType from )
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{
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write16( 0xDF0F );
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ModRM( 3, to, from );
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}
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/* por r64 to r64 */
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emitterT void PORRtoR( x86MMXRegType to, x86MMXRegType from )
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{
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write16( 0xEB0F );
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ModRM( 3, to, from );
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}
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/* pxor r64 to r64 */
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emitterT void PXORRtoR( x86MMXRegType to, x86MMXRegType from )
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{
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write16( 0xEF0F );
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ModRM( 3, to, from );
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}
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/* psllq r64 to r64 */
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emitterT void PSLLQRtoR( x86MMXRegType to, x86MMXRegType from )
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{
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@ -420,38 +398,6 @@ emitterT void PSRADRtoR( x86MMXRegType to, x86MMXRegType from )
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ModRM( 3, to, from );
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}
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/* por m64 to r64 */
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emitterT void PORMtoR( x86MMXRegType to, uptr from )
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{
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write16( 0xEB0F );
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ModRM( 0, to, DISP32 );
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write32( MEMADDR(from, 4) );
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}
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/* pxor m64 to r64 */
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emitterT void PXORMtoR( x86MMXRegType to, uptr from )
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{
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write16( 0xEF0F );
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ModRM( 0, to, DISP32 );
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write32( MEMADDR(from, 4) );
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}
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/* pand m64 to r64 */
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emitterT void PANDMtoR( x86MMXRegType to, uptr from )
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{
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//u64 rip = (u64)x86Ptr + 7;
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write16( 0xDB0F );
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ModRM( 0, to, DISP32 );
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write32( MEMADDR(from, 4) );
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}
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emitterT void PANDNMtoR( x86MMXRegType to, uptr from )
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{
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write16( 0xDF0F );
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ModRM( 0, to, DISP32 );
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write32( MEMADDR(from, 4) );
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}
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emitterT void PUNPCKHDQRtoR( x86MMXRegType to, x86MMXRegType from )
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{
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write16( 0x6A0F );
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@ -215,108 +215,34 @@ emitterT void SSE_MOVHLPS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { i
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emitterT void SSE2_PMOVMSKB_XMM_to_R32(x86IntRegType to, x86SSERegType from) { iPMOVMSKB( iRegister32(to), iRegisterSSE(from) ); }
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#define DEFINE_LEGACY_PSD_OPCODE( mod ) \
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emitterT void SSE_##mod##PS_M128_to_XMM( x86SSERegType to, uptr from ) { i##mod##PS( iRegisterSSE(to), (void*)from ); } \
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emitterT void SSE_##mod##PS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { i##mod##PS( iRegisterSSE(to), iRegisterSSE(from) ); } \
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emitterT void SSE2_##mod##PD_M128_to_XMM( x86SSERegType to, uptr from ) { i##mod##PD( iRegisterSSE(to), (void*)from ); } \
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emitterT void SSE2_##mod##PD_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { i##mod##PD( iRegisterSSE(to), iRegisterSSE(from) ); }
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#define DEFINE_LEGACY_PSSD_OPCODE( mod ) \
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DEFINE_LEGACY_PSD_OPCODE( mod ) \
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emitterT void SSE_##mod##SS_M32_to_XMM( x86SSERegType to, uptr from ) { i##mod##SS( iRegisterSSE(to), (void*)from ); } \
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emitterT void SSE_##mod##SS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { i##mod##SS( iRegisterSSE(to), iRegisterSSE(from) ); } \
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emitterT void SSE2_##mod##SD_M32_to_XMM( x86SSERegType to, uptr from ) { i##mod##SD( iRegisterSSE(to), (void*)from ); } \
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emitterT void SSE2_##mod##SD_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { i##mod##SD( iRegisterSSE(to), iRegisterSSE(from) ); }
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///////////////////////////////////////////////////////////////////////////////////
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//**********************************************************************************/
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//ANDPS: Logical Bit-wise AND for Single FP *
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//**********************************************************************************
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emitterT void SSE_ANDPS_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR( 0x540f, 0 ); }
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emitterT void SSE_ANDPS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSERtoR( 0x540f ); }
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DEFINE_LEGACY_PSD_OPCODE( AND )
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DEFINE_LEGACY_PSD_OPCODE( ANDN )
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DEFINE_LEGACY_PSD_OPCODE( OR )
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DEFINE_LEGACY_PSD_OPCODE( XOR )
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emitterT void SSE2_ANDPD_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR66( 0x540f ); }
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emitterT void SSE2_ANDPD_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSERtoR66( 0x540f ); }
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DEFINE_LEGACY_PSSD_OPCODE( SUB )
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DEFINE_LEGACY_PSSD_OPCODE( ADD )
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DEFINE_LEGACY_PSSD_OPCODE( MUL )
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DEFINE_LEGACY_PSSD_OPCODE( DIV )
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///////////////////////////////////////////////////////////////////////////////////////
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//**********************************************************************************/
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//ANDNPS : Logical Bit-wise AND NOT of Single-precision FP values *
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//**********************************************************************************
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emitterT void SSE_ANDNPS_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR( 0x550f, 0 ); }
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emitterT void SSE_ANDNPS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ){ SSERtoR( 0x550f ); }
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emitterT void SSE_RCPPS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { iRCPPS( iRegisterSSE(to), iRegisterSSE(from) ); }
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emitterT void SSE_RCPPS_M128_to_XMM( x86SSERegType to, uptr from ) { iRCPPS( iRegisterSSE(to), (void*)from ); }
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emitterT void SSE2_ANDNPD_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR66( 0x550f ); }
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emitterT void SSE2_ANDNPD_XMM_to_XMM( x86SSERegType to, x86SSERegType from ){ SSERtoR66( 0x550f ); }
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/////////////////////////////////////////////////////////////////////////////////////
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//**********************************************************************************/
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//RCPPS : Packed Single-Precision FP Reciprocal *
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//**********************************************************************************
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emitterT void SSE_RCPPS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSERtoR( 0x530f ); }
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emitterT void SSE_RCPPS_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR( 0x530f, 0 ); }
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emitterT void SSE_RCPSS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSE_SS_RtoR(0x530f); }
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emitterT void SSE_RCPSS_M32_to_XMM( x86SSERegType to, uptr from ) { SSE_SS_MtoR(0x530f, 0); }
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//////////////////////////////////////////////////////////////////////////////////////
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//**********************************************************************************/
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//ORPS : Bit-wise Logical OR of Single-Precision FP Data *
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//**********************************************************************************
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emitterT void SSE_ORPS_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR( 0x560f, 0 ); }
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emitterT void SSE_ORPS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSERtoR( 0x560f ); }
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emitterT void SSE2_ORPD_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR66( 0x560f ); }
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emitterT void SSE2_ORPD_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSERtoR66( 0x560f ); }
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/////////////////////////////////////////////////////////////////////////////////////
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//**********************************************************************************/
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//XORPS : Bitwise Logical XOR of Single-Precision FP Values *
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//**********************************************************************************
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emitterT void SSE_XORPS_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR( 0x570f, 0 ); }
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emitterT void SSE_XORPS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSERtoR( 0x570f ); }
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emitterT void SSE2_XORPD_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR66( 0x570f ); }
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emitterT void SSE2_XORPD_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSERtoR66( 0x570f ); }
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///////////////////////////////////////////////////////////////////////////////////////
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//**********************************************************************************/
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//ADDPS : ADD Packed Single-Precision FP Values *
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//**********************************************************************************
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emitterT void SSE_ADDPS_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR( 0x580f, 0 ); }
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emitterT void SSE_ADDPS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSERtoR( 0x580f ); }
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////////////////////////////////////////////////////////////////////////////////////
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//**********************************************************************************/
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//ADDSS : ADD Scalar Single-Precision FP Values *
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//**********************************************************************************
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emitterT void SSE_ADDSS_M32_to_XMM( x86SSERegType to, uptr from ) { SSE_SS_MtoR( 0x580f, 0 ); }
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emitterT void SSE_ADDSS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSE_SS_RtoR( 0x580f ); }
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emitterT void SSE2_ADDSD_M64_to_XMM( x86SSERegType to, uptr from ) { SSE_SD_MtoR( 0x580f, 0 ); }
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emitterT void SSE2_ADDSD_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSE_SD_RtoR( 0x580f ); }
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/////////////////////////////////////////////////////////////////////////////////////////
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//**********************************************************************************/
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//SUBPS: Packed Single-Precision FP Subtract *
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//**********************************************************************************
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emitterT void SSE_SUBPS_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR( 0x5c0f, 0 ); }
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emitterT void SSE_SUBPS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSERtoR( 0x5c0f ); }
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///////////////////////////////////////////////////////////////////////////////////////
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//**********************************************************************************/
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//SUBSS : Scalar Single-Precision FP Subtract *
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//**********************************************************************************
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emitterT void SSE_SUBSS_M32_to_XMM( x86SSERegType to, uptr from ) { SSE_SS_MtoR( 0x5c0f, 0 ); }
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emitterT void SSE_SUBSS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSE_SS_RtoR( 0x5c0f ); }
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emitterT void SSE2_SUBSD_M64_to_XMM( x86SSERegType to, uptr from ) { SSE_SD_MtoR( 0x5c0f, 0 ); }
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emitterT void SSE2_SUBSD_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSE_SD_RtoR( 0x5c0f ); }
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////
|
||||
//**********************************************************************************/
|
||||
//MULPS : Packed Single-Precision FP Multiply *
|
||||
//**********************************************************************************
|
||||
emitterT void SSE_MULPS_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR( 0x590f, 0 ); }
|
||||
emitterT void SSE_MULPS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSERtoR( 0x590f ); }
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
//**********************************************************************************/
|
||||
//MULSS : Scalar Single-Precision FP Multiply *
|
||||
//**********************************************************************************
|
||||
emitterT void SSE_MULSS_M32_to_XMM( x86SSERegType to, uptr from ) { SSE_SS_MtoR( 0x590f, 0 ); }
|
||||
emitterT void SSE_MULSS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSE_SS_RtoR( 0x590f ); }
|
||||
|
||||
emitterT void SSE2_MULSD_M64_to_XMM( x86SSERegType to, uptr from ) { SSE_SD_MtoR( 0x590f, 0 ); }
|
||||
emitterT void SSE2_MULSD_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSE_SD_RtoR( 0x590f ); }
|
||||
emitterT void SSE_RCPSS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { iRCPSS( iRegisterSSE(to), iRegisterSSE(from) ); }
|
||||
emitterT void SSE_RCPSS_M32_to_XMM( x86SSERegType to, uptr from ) { iRCPSS( iRegisterSSE(to), (void*)from ); }
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//**********************************************************************************/
|
||||
|
|
@ -610,23 +536,6 @@ emitterT void SSE_UNPCKLPS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) {
|
|||
emitterT void SSE_UNPCKHPS_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR(0x150f, 0); }
|
||||
emitterT void SSE_UNPCKHPS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSERtoR( 0x150F ); }
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////
|
||||
//**********************************************************************************/
|
||||
//DIVPS : Packed Single-Precision FP Divide *
|
||||
//**********************************************************************************
|
||||
emitterT void SSE_DIVPS_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR( 0x5e0F, 0 ); }
|
||||
emitterT void SSE_DIVPS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSERtoR( 0x5e0F ); }
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////
|
||||
//**********************************************************************************/
|
||||
//DIVSS : Scalar Single-Precision FP Divide *
|
||||
//**********************************************************************************
|
||||
emitterT void SSE_DIVSS_M32_to_XMM( x86SSERegType to, uptr from ) { SSE_SS_MtoR( 0x5e0F, 0 ); }
|
||||
emitterT void SSE_DIVSS_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSE_SS_RtoR( 0x5e0F ); }
|
||||
|
||||
emitterT void SSE2_DIVSD_M64_to_XMM( x86SSERegType to, uptr from ) { SSE_SD_MtoR( 0x5e0F, 0 ); }
|
||||
emitterT void SSE2_DIVSD_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSE_SD_RtoR( 0x5e0F ); }
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////////
|
||||
//**********************************************************************************/
|
||||
//STMXCSR : Store Streaming SIMD Extension Control/Status *
|
||||
|
|
@ -731,30 +640,9 @@ emitterT void SSE2_MOVD_XMM_to_Rm( x86IntRegType to, x86SSERegType from, int off
|
|||
WriteRmOffsetFrom(from, to, offset);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
//**********************************************************************************/
|
||||
//POR : SSE Bitwise OR *
|
||||
//**********************************************************************************
|
||||
emitterT void SSE2_POR_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSERtoR66( 0xEB0F ); }
|
||||
emitterT void SSE2_POR_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR66( 0xEB0F ); }
|
||||
|
||||
// logical and to &= from
|
||||
emitterT void SSE2_PAND_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSERtoR66( 0xDB0F ); }
|
||||
emitterT void SSE2_PAND_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR66( 0xDB0F ); }
|
||||
|
||||
// to = (~to) & from
|
||||
emitterT void SSE2_PANDN_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSERtoR66( 0xDF0F ); }
|
||||
emitterT void SSE2_PANDN_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR66( 0xDF0F ); }
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////////////
|
||||
//**********************************************************************************/
|
||||
//PXOR : SSE Bitwise XOR *
|
||||
//**********************************************************************************
|
||||
emitterT void SSE2_PXOR_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) { SSERtoR66( 0xEF0F ); }
|
||||
emitterT void SSE2_PXOR_M128_to_XMM( x86SSERegType to, uptr from ) { SSEMtoR66( 0xEF0F ); }
|
||||
///////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
emitterT void SSE2_MOVDQA_XMM_to_XMM( x86SSERegType to, x86SSERegType from) { if( AlwaysUseMovaps ) SSE_MOVAPS_XMM_to_XMM( to, from ); else if( to != from ) SSERtoR66(0x6F0F); }
|
||||
emitterT void SSE2_MOVDQA_XMM_to_XMM( x86SSERegType to, x86SSERegType from) { iMOVDQA( iRegisterSSE(to), iRegisterSSE(from) ); }
|
||||
|
||||
|
||||
// shift right logical
|
||||
|
|
|
|||
|
|
@ -690,24 +690,63 @@ namespace x86Emitter
|
|||
static const bool AlwaysUseMovaps = false;
|
||||
#endif
|
||||
|
||||
extern const Internal::MovapsImplAll< 0, 0x28, 0x29 > iMOVAPS;
|
||||
extern const Internal::MovapsImplAll< 0, 0x10, 0x11 > iMOVUPS;
|
||||
extern const Internal::MovapsImplAll<0, 0x28, 0x29> iMOVAPS;
|
||||
extern const Internal::MovapsImplAll<0, 0x10, 0x11> iMOVUPS;
|
||||
|
||||
extern const Internal::MovapsImplAll< 0x66, 0x28, 0x29 > iMOVAPD;
|
||||
extern const Internal::MovapsImplAll< 0x66, 0x10, 0x11 > iMOVUPD;
|
||||
extern const Internal::MovapsImplAll<0x66, 0x28, 0x29> iMOVAPD;
|
||||
extern const Internal::MovapsImplAll<0x66, 0x10, 0x11> iMOVUPD;
|
||||
|
||||
#ifdef ALWAYS_USE_MOVAPS
|
||||
extern const Internal::MovapsImplAll< 0x66, 0x6f, 0x7f > iMOVDQA;
|
||||
extern const Internal::MovapsImplAll< 0xf3, 0x6f, 0x7f > iMOVDQU;
|
||||
extern const Internal::MovapsImplAll<0x66, 0x6f, 0x7f> iMOVDQA;
|
||||
extern const Internal::MovapsImplAll<0xf3, 0x6f, 0x7f> iMOVDQU;
|
||||
#else
|
||||
extern const Internal::MovapsImplAll< 0, 0x28, 0x29 > iMOVDQA;
|
||||
extern const Internal::MovapsImplAll< 0, 0x10, 0x11 > iMOVDQU;
|
||||
extern const Internal::MovapsImplAll<0, 0x28, 0x29> iMOVDQA;
|
||||
extern const Internal::MovapsImplAll<0, 0x10, 0x11> iMOVDQU;
|
||||
#endif
|
||||
|
||||
extern const Internal::MovhlImplAll< 0, 0x16 > iMOVHPS;
|
||||
extern const Internal::MovhlImplAll< 0, 0x12 > iMOVLPS;
|
||||
extern const Internal::MovhlImplAll< 0x66, 0x16 > iMOVHPD;
|
||||
extern const Internal::MovhlImplAll< 0x66, 0x12 > iMOVLPD;
|
||||
extern const Internal::MovhlImplAll<0, 0x16> iMOVHPS;
|
||||
extern const Internal::MovhlImplAll<0, 0x12> iMOVLPS;
|
||||
extern const Internal::MovhlImplAll<0x66, 0x16> iMOVHPD;
|
||||
extern const Internal::MovhlImplAll<0x66, 0x12> iMOVLPD;
|
||||
|
||||
extern const Internal::PLogicImplAll<0xdb> iPAND;
|
||||
extern const Internal::PLogicImplAll<0xdf> iPANDN;
|
||||
extern const Internal::PLogicImplAll<0xeb> iPOR;
|
||||
extern const Internal::PLogicImplAll<0xef> iPXOR;
|
||||
|
||||
extern const Internal::PLogicImplSSE<0x00,0x54> iANDPS;
|
||||
extern const Internal::PLogicImplSSE<0x66,0x54> iANDPD;
|
||||
extern const Internal::PLogicImplSSE<0x00,0x55> iANDNPS;
|
||||
extern const Internal::PLogicImplSSE<0x66,0x55> iANDNPD;
|
||||
extern const Internal::PLogicImplSSE<0x00,0x56> iORPS;
|
||||
extern const Internal::PLogicImplSSE<0x66,0x56> iORPD;
|
||||
extern const Internal::PLogicImplSSE<0x00,0x57> iXORPS;
|
||||
extern const Internal::PLogicImplSSE<0x66,0x57> iXORPD;
|
||||
|
||||
extern const Internal::PLogicImplSSE<0x00,0x5c> iSUBPS;
|
||||
extern const Internal::PLogicImplSSE<0x66,0x5c> iSUBPD;
|
||||
extern const Internal::PLogicImplSSE<0xf3,0x5c> iSUBSS;
|
||||
extern const Internal::PLogicImplSSE<0xf2,0x5c> iSUBSD;
|
||||
|
||||
extern const Internal::PLogicImplSSE<0x00,0x58> iADDPS;
|
||||
extern const Internal::PLogicImplSSE<0x66,0x58> iADDPD;
|
||||
extern const Internal::PLogicImplSSE<0xf3,0x58> iADDSS;
|
||||
extern const Internal::PLogicImplSSE<0xf2,0x58> iADDSD;
|
||||
|
||||
extern const Internal::PLogicImplSSE<0x00,0x59> iMULPS;
|
||||
extern const Internal::PLogicImplSSE<0x66,0x59> iMULPD;
|
||||
extern const Internal::PLogicImplSSE<0xf3,0x59> iMULSS;
|
||||
extern const Internal::PLogicImplSSE<0xf2,0x59> iMULSD;
|
||||
|
||||
extern const Internal::PLogicImplSSE<0x00,0x5e> iDIVPS;
|
||||
extern const Internal::PLogicImplSSE<0x66,0x5e> iDIVPD;
|
||||
extern const Internal::PLogicImplSSE<0xf3,0x5e> iDIVSS;
|
||||
extern const Internal::PLogicImplSSE<0xf2,0x5e> iDIVSD;
|
||||
|
||||
|
||||
|
||||
extern const Internal::PLogicImplSSE<0,0x53> iRCPPS;
|
||||
extern const Internal::PLogicImplSSE<0xf3,0x53> iRCPSS;
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue