diff --git a/pcsx2/x86/microVU_Alloc.inl b/pcsx2/x86/microVU_Alloc.inl
index 9bc2ea2dd5..5e2472d8d1 100644
--- a/pcsx2/x86/microVU_Alloc.inl
+++ b/pcsx2/x86/microVU_Alloc.inl
@@ -71,37 +71,20 @@ __ri void mVUallocSFLAGc(const x32& reg, const x32& regT, int fInstance)
 }
 
 // Denormalizes Status Flag
-// If setAllflags is false, then returns result in eax (gprT1)
-// else all microVU flag regs (gprF0..F3) get the result.
-__ri void mVUallocSFLAGd(u32* memAddr, bool setAllflags) {
+__ri void mVUallocSFLAGd(u32* memAddr) {
+	xMOV(edx, ptr32[memAddr]);
+	xMOV(eax, edx);
+	xSHR(eax, 3);
+	xAND(eax, 0x18);
 
-	// When this function is used by mVU0 macro the EErec
-	// needs EBP (gprF1) and ESI (gprF2) to be preserved.
-	const xAddressReg& t0 = setAllflags ? gprT1 : gprF3;
-	const xAddressReg& t1 = setAllflags ? gprT2 : gprF2;
-	const xAddressReg& t2 = setAllflags ? gprT3 : gprF0;
+	xMOV(ecx, edx);
+	xSHL(ecx, 11);
+	xAND(ecx, 0x1800);
+	xOR (eax, ecx);
 
-	xMOV(t2, ptr32[memAddr]);
-	xMOV(t0, t2);
-	xSHR(t0, 3);
-	xAND(t0, 0x18);
-
-	xMOV(t1, t2);
-	xSHL(t1, 11);
-	xAND(t1, 0x1800);
-	xOR (t0, t1);
-
-	xSHL(t2, 14);
-	xAND(t2, 0x3cf0000);
-	xOR (t0, t2);
-
-	if (setAllflags) {
-		// this code should be run in mVU micro mode only, so writing to
-		// EBP (gprF1) and ESI (gprF2) is ok (and needed for vuMicro).
-		xMOV(gprF0, gprF3); // gprF3 is t0
-		xMOV(gprF1, gprF3);
-		xMOV(gprF2, gprF3);
-	}
+	xSHL(edx, 14);
+	xAND(edx, 0x3cf0000);
+	xOR (eax, edx);
 }
 
 __fi void mVUallocMFLAGa(mV, const x32& reg, int fInstance)
diff --git a/pcsx2/x86/microVU_Branch.inl b/pcsx2/x86/microVU_Branch.inl
index 02eb27484c..f784d01f8e 100644
--- a/pcsx2/x86/microVU_Branch.inl
+++ b/pcsx2/x86/microVU_Branch.inl
@@ -65,12 +65,7 @@ void mVUendProgram(mV, microFlagCycles* mFC, int isEbit) {
 	}
 
 	// Save Flag Instances
-#if 1 // CHECK_MACROVU0 - Always on now
 	xMOV(ptr32[&mVU.regs().VI[REG_STATUS_FLAG].UL],	getFlagReg(fStatus));
-#else
-	mVUallocSFLAGc(gprT1, gprT2, fStatus);
-	xMOV(ptr32[&mVU.regs().VI[REG_STATUS_FLAG].UL],	gprT1);
-#endif
 	mVUallocMFLAGa(mVU, gprT1, fMac);
 	mVUallocCFLAGa(mVU, gprT2, fClip);
 	xMOV(ptr32[&mVU.regs().VI[REG_MAC_FLAG].UL],	gprT1);
diff --git a/pcsx2/x86/microVU_Execute.inl b/pcsx2/x86/microVU_Execute.inl
index e65dc9f8f4..d7a910e848 100644
--- a/pcsx2/x86/microVU_Execute.inl
+++ b/pcsx2/x86/microVU_Execute.inl
@@ -42,14 +42,10 @@ void mVUdispatcherA(mV) {
 	xLDMXCSR(g_sseVUMXCSR);
 
 	// Load Regs
-#if 1 // CHECK_MACROVU0 - Always on now
 	xMOV(gprF0, ptr32[&mVU.regs().VI[REG_STATUS_FLAG].UL]);
 	xMOV(gprF1, gprF0);
 	xMOV(gprF2, gprF0);
 	xMOV(gprF3, gprF0);
-#else
-	mVUallocSFLAGd((uptr)&mVU.regs().VI[REG_STATUS_FLAG].UL, 1);
-#endif
 
 	xMOVAPS (xmmT1, ptr128[&mVU.regs().VI[REG_MAC_FLAG].UL]);
 	xSHUF.PS(xmmT1, xmmT1, 0);
diff --git a/pcsx2/x86/microVU_Macro.inl b/pcsx2/x86/microVU_Macro.inl
index 48d5756e37..225c98b0ea 100644
--- a/pcsx2/x86/microVU_Macro.inl
+++ b/pcsx2/x86/microVU_Macro.inl
@@ -306,7 +306,7 @@ static void recCTC2() {
 			break;
 		case REG_STATUS_FLAG:
 			if (_Rt_) { // Denormalizes flag into eax (gprT1)
-				mVUallocSFLAGd(&cpuRegs.GPR.r[_Rt_].UL[0], 0);
+				mVUallocSFLAGd(&cpuRegs.GPR.r[_Rt_].UL[0]);
 				xMOV(ptr32[&vu0Regs.VI[_Rd_].UL], eax);
 			}
 			else xMOV(ptr32[&vu0Regs.VI[_Rd_].UL], 0);