mirror of https://github.com/PCSX2/pcsx2.git
psxmode: Spu2x: more native SPU2 reghandlers. first "working" reverb! (everything before was just random data)
This commit is contained in:
Robert Neumann
Robert
parent
ee05137415
commit
19a8ed8b25
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@ -268,7 +268,9 @@ void V_Core::UpdateEffectsBufferSize()
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//printf("too big, returning\n");
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//return;
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}
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if (newbufsize == EffectsBufferSize && EffectsStartA == EffectsBufferStart) return;
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// bad optimization?
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//if (newbufsize == EffectsBufferSize && EffectsStartA == EffectsBufferStart) return;
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//printf("Rvb Area change: ESA = %x, EEA = %x, Size(dec) = %d, Size(hex) = %x FxEnable = %d\n", EffectsStartA, EffectsEndA, newbufsize * 2, newbufsize * 2, FxEnable);
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@ -623,54 +625,51 @@ void V_Core::WriteRegPS1( u32 mem, u16 value )
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break;
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case 0x1d88:// Voice ON (0-15)
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StartVoices(0, (u32)value);
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SPU2_FastWrite(REG_S_KON, value);
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break;
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case 0x1d8a:// Voice ON (16-23)
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StartVoices(0, ((u32)value) << 16);
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SPU2_FastWrite(REG_S_KON + 2, value);
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break;
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case 0x1d8c:// Voice OFF (0-15)
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StopVoices(0, (u32)value);
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SPU2_FastWrite(REG_S_KOFF, value);
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break;
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case 0x1d8e:// Voice OFF (16-23)
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StopVoices(0, ((u32)value) << 16);
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SPU2_FastWrite(REG_S_KOFF + 2, value);
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break;
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case 0x1d90:// Channel FM (pitch lfo) mode (0-15)
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Regs.PMON = value & 0xFFFF;
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for (int vc = 1; vc<16; ++vc)
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Voices[vc].Modulated = (value >> vc) & 1;
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if (value != 0) ConLog("spu2x warning: wants to set Pitch Modulation reg1 to %x \n", value);
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SPU2_FastWrite(REG_S_PMON, value);
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if (value!=0)ConLog("spu2x warning: wants to set Pitch Modulation reg1 to %x \n", value);
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break;
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case 0x1d92:// Channel FM (pitch lfo) mode (16-23)
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Regs.PMON = value << 16;
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for (int vc = 0; vc<8; ++vc)
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Voices[vc + 16].Modulated = (value >> vc) & 1;
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SPU2_FastWrite(REG_S_PMON + 2, value);
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if (value != 0)ConLog("spu2x warning: wants to set Pitch Modulation reg2 to %x \n", value);
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break;
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case 0x1d94:// Channel Noise mode (0-15)
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SetLoWord(Regs.NON, value);
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for (int vc = 0; vc<16; ++vc)
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Voices[vc].Noise = (value >> vc) & 1;
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SPU2_FastWrite(REG_S_NON, value);
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if (value != 0) ConLog("spu2x warning: wants to set Channel Noise mode reg1 to %x\n", value);
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break;
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case 0x1d96:// Channel Noise mode (16-23)
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SetHiWord(Regs.NON, value);
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for (int vc = 0; vc<8; ++vc)
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Voices[vc + 16].Noise = (value >> vc) & 1;
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//ConLog("spu2x warning: wants to set Channel Noise mode reg2 to %x (ignored)\n", value);
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SPU2_FastWrite(REG_S_NON + 2, value);
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if (value != 0) ConLog("spu2x warning: wants to set Channel Noise mode reg2 to %x\n", value);
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break;
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case 0x1d98:// 1F801D98h - Voice 0..23 Reverb mode aka Echo On (EON) (R/W)
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Regs.VMIXEL = value & 0xFFFF;
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//Regs.VMIXEL = value & 0xFFFF;
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SPU2_FastWrite(REG_S_VMIXEL, value);
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SPU2_FastWrite(REG_S_VMIXER, value);
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//ConLog("spu2x warning: setting reverb mode reg1 to %x \n", Regs.VMIXEL);
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break;
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case 0x1d9a:// 1F801D98h + 2 - Voice 0..23 Reverb mode aka Echo On (EON) (R/W)
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Regs.VMIXEL = value << 16;
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//Regs.VMIXEL = value << 16;
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SPU2_FastWrite(REG_S_VMIXEL + 2, value);
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SPU2_FastWrite(REG_S_VMIXER + 2, value);
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//ConLog("spu2x warning: setting reverb mode reg2 to %x \n", Regs.VMIXEL);
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break;
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@ -685,20 +684,21 @@ void V_Core::WriteRegPS1( u32 mem, u16 value )
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// SPU2_FastWrite(REG_S_VMIXR+2,value);
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//break;
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case 0x1d9c: // Voice 0..15 ON/OFF (status) (ENDX) (R) // writeable but hw overrides it shortly after
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Regs.ENDX &= 0xff0000;
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//Regs.ENDX &= 0xff0000;
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ConLog("spu2x warning: wants to set ENDX reg1 to %x \n", value);
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break;
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case 0x1d9e:// // Voice 15..23 ON/OFF (status) (ENDX) (R) // writeable but hw overrides it shortly after
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Regs.ENDX &= 0xffff;
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//Regs.ENDX &= 0xffff;
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ConLog("spu2x warning: wants to set ENDX reg2 to %x \n", value);
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break;
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case 0x1da2:// Reverb work area start
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{
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EffectsStartA = map_spu1to2(value);
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EffectsEndA = 0xFFFFF; // fixed EndA in psx mode
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//EffectsEndA = 0xFFFFF; // fixed EndA in psx mode
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Cores[0].RevBuffers.NeedsUpdated = true;
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ReverbX = 0;
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}
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break;
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@ -724,74 +724,19 @@ void V_Core::WriteRegPS1( u32 mem, u16 value )
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break;
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case 0x1daa:
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{
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V_Core& thiscore = Cores[0];
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bool irqe = thiscore.IRQEnable;
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int bit0 = thiscore.AttrBit0;
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bool fxenable = thiscore.FxEnable;
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u8 oldDmaMode = thiscore.DmaMode;
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thiscore.AttrBit0 = (value >> 0) & 0x01; //1 bit
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thiscore.DMABits = (value >> 1) & 0x07; //3 bits
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thiscore.DmaMode = (value >> 4) & 0x03; //2 bit (not necessary, we get the direction from the iop)
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thiscore.IRQEnable = (value >> 6) & 0x01; //1 bit
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thiscore.FxEnable = (value >> 7) & 0x01; //1 bit
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thiscore.NoiseClk = (value >> 8) & 0x3f; //6 bits
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//thiscore.Mute =(value>>14) & 0x01; //1 bit
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thiscore.Mute = 0;
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//thiscore.CoreEnabled=(value>>15) & 0x01; //1 bit
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// no clue
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if (value >> 15)
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thiscore.Regs.STATX = 0;
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thiscore.Regs.ATTR = value & 0x7fff;
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if (fxenable && !thiscore.FxEnable
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&& (thiscore.EffectsStartA != thiscore.ExtEffectsStartA
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|| thiscore.EffectsEndA != thiscore.ExtEffectsEndA))
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{
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thiscore.EffectsStartA = thiscore.ExtEffectsStartA;
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thiscore.EffectsEndA = thiscore.ExtEffectsEndA;
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thiscore.ReverbX = 0;
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thiscore.RevBuffers.NeedsUpdated = true;
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ConLog("fx toggle!\n");
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}
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if (oldDmaMode != thiscore.DmaMode)
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{
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// FIXME... maybe: if this mode was cleared in the middle of a DMA, should we interrupt it?
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thiscore.Regs.STATX &= ~0x400; // ready to transfer
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}
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if (value & 0x000E)
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{
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if (MsgToConsole()) ConLog("* SPU2-X: Core 0 ATTR unknown bits SET! value=%04x\n", value);
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}
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if (thiscore.AttrBit0 != bit0)
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{
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if (MsgToConsole()) ConLog("* SPU2-X: ATTR bit 0 set to %d\n", thiscore.AttrBit0);
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}
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if (thiscore.IRQEnable != irqe)
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{
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//ConLog("* SPU2-X: Core%d IRQ %s at cycle %d. Current IRQA = %x Current EffectA = %x\n",
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// core, ((thiscore.IRQEnable==0)?"disabled":"enabled"), Cycles, thiscore.IRQA, thiscore.EffectsStartA);
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if (!thiscore.IRQEnable)
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Spdif.Info &= ~(4 << thiscore.Index);
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}
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}
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SPU2_FastWrite(REG_C_ATTR, value);
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break;
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case 0x1dac: // 1F801DACh - Sound RAM Data Transfer Control (should be 0004h)
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ConLog("SPU Sound RAM Data Transfer Control (should be 0004h) : value = %x \n", value);
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ConLog("SPU Sound RAM Data Transfer Control (should be 4) : value = %x \n", value);
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psxSoundDataTransferControl = value;
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break;
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break;
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case 0x1dae: // 1F801DAEh - SPU Status Register (SPUSTAT) (R)
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// The SPUSTAT register should be treated read-only (writing is possible in so far that the written
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// value can be read-back for a short moment, however, thereafter the hardware is overwriting that value).
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//Regs.STATX = value;
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break;
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break;
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case 0x1DB0: // 1F801DB0h 4 CD Volume Left/Right
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break; // cd left?
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@ -810,8 +755,8 @@ void V_Core::WriteRegPS1( u32 mem, u16 value )
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case 0x1DBE:
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break;
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case 0x1DC0: Revb.FB_SRC_A = value; break;
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case 0x1DC2: Revb.FB_SRC_B = value; break;
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case 0x1DC0: Revb.FB_SRC_A = value * 4; break;
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case 0x1DC2: Revb.FB_SRC_B = value * 4; break;
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case 0x1DC4: Revb.IIR_ALPHA = value; break;
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case 0x1DC6: Revb.ACC_COEF_A = value; break;
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case 0x1DC8: Revb.ACC_COEF_B = value; break;
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@ -820,26 +765,26 @@ void V_Core::WriteRegPS1( u32 mem, u16 value )
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case 0x1DCE: Revb.IIR_COEF = value; break;
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case 0x1DD0: Revb.FB_ALPHA = value; break;
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case 0x1DD2: Revb.FB_X = value; break;
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case 0x1DD4: Revb.IIR_DEST_A0 = value; break;
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case 0x1DD6: Revb.IIR_DEST_A1 = value; break;
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case 0x1DD8: Revb.ACC_SRC_A0 = value; break;
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case 0x1DDA: Revb.ACC_SRC_A1 = value; break;
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case 0x1DDC: Revb.ACC_SRC_B0 = value; break;
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case 0x1DDE: Revb.ACC_SRC_B1 = value; break;
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case 0x1DE0: Revb.IIR_SRC_A0 = value; break;
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case 0x1DE2: Revb.IIR_SRC_A1 = value; break;
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case 0x1DE4: Revb.IIR_DEST_B0 = value; break;
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case 0x1DE6: Revb.IIR_DEST_B1 = value; break;
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case 0x1DE8: Revb.ACC_SRC_C0 = value; break;
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case 0x1DEA: Revb.ACC_SRC_C1 = value; break;
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case 0x1DEC: Revb.ACC_SRC_D0 = value; break;
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case 0x1DEE: Revb.ACC_SRC_D1 = value; break;
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case 0x1DF0: Revb.IIR_SRC_B1 = value; break;
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case 0x1DF2: Revb.IIR_SRC_B0 = value; break;
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case 0x1DF4: Revb.MIX_DEST_A0 = value; break;
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case 0x1DF6: Revb.MIX_DEST_A1 = value; break;
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case 0x1DF8: Revb.MIX_DEST_B0 = value; break;
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case 0x1DFA: Revb.MIX_DEST_B1 = value; break;
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case 0x1DD4: Revb.IIR_DEST_A0 = value * 4; break;
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case 0x1DD6: Revb.IIR_DEST_A1 = value * 4; break;
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case 0x1DD8: Revb.ACC_SRC_A0 = value * 4; break;
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case 0x1DDA: Revb.ACC_SRC_A1 = value * 4; break;
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case 0x1DDC: Revb.ACC_SRC_B0 = value * 4; break;
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case 0x1DDE: Revb.ACC_SRC_B1 = value * 4; break;
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case 0x1DE0: Revb.IIR_SRC_A0 = value * 4; break;
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case 0x1DE2: Revb.IIR_SRC_A1 = value * 4; break;
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case 0x1DE4: Revb.IIR_DEST_B0 = value * 4; break;
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case 0x1DE6: Revb.IIR_DEST_B1 = value * 4; break;
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case 0x1DE8: Revb.ACC_SRC_C0 = value * 4; break;
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case 0x1DEA: Revb.ACC_SRC_C1 = value * 4; break;
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case 0x1DEC: Revb.ACC_SRC_D0 = value * 4; break;
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case 0x1DEE: Revb.ACC_SRC_D1 = value * 4; break;
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case 0x1DF0: Revb.IIR_SRC_B0 = value * 4; break; // IIR_SRC_B0 and IIR_SRC_B1 supposedly swapped on SPU2
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case 0x1DF2: Revb.IIR_SRC_B1 = value * 4; break; // but I don't believe it! (games in psxmode sound better unswapped)
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case 0x1DF4: Revb.MIX_DEST_A0 = value * 4; break;
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case 0x1DF6: Revb.MIX_DEST_A1 = value * 4; break;
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case 0x1DF8: Revb.MIX_DEST_B0 = value * 4; break;
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case 0x1DFA: Revb.MIX_DEST_B1 = value * 4; break;
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case 0x1DFC: Revb.IN_COEF_L = value; break;
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case 0x1DFE: Revb.IN_COEF_R = value; break;
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