From 18c4765d31001e40d07932423a33c243dcfe2a84 Mon Sep 17 00:00:00 2001 From: "Jake.Stine" Date: Mon, 20 Apr 2009 03:10:05 +0000 Subject: [PATCH] Emitter: Changed a lot of 'i's into 'x's, because... sudonim says he likes xMOV better than iMOV as an emitter prefix. I'm wondering if I should go ahead and change it. I tend to favor logic, but everyone else just thinks it looks like iMac and iPod I just don't want to have to change it more than once. well 'x' is like the algebraic variable, which can be anything so it does kindoff make sense cuz like you have xSOMETHING, where SOMETHING is all the different emitter functions ... I'm sold. :p git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1030 96395faa-99c1-11dd-bbfe-3dabce05a288 --- pcsx2/x86/iVUmicroLower.cpp | 10 +- pcsx2/x86/ix86-32/recVTLB.cpp | 32 +- pcsx2/x86/ix86/implement/bittest.h | 74 ++--- pcsx2/x86/ix86/implement/dwshift.h | 42 +-- pcsx2/x86/ix86/implement/group1.h | 106 +++--- pcsx2/x86/ix86/implement/group2.h | 28 +- pcsx2/x86/ix86/implement/group3.h | 70 ++-- pcsx2/x86/ix86/implement/incdec.h | 12 +- pcsx2/x86/ix86/implement/jmpcall.h | 16 +- pcsx2/x86/ix86/implement/movs.h | 130 ++++---- pcsx2/x86/ix86/implement/test.h | 22 +- pcsx2/x86/ix86/implement/xmm/movqss.h | 130 ++++---- pcsx2/x86/ix86/ix86.cpp | 394 +++++++++++----------- pcsx2/x86/ix86/ix86_inlines.inl | 42 +-- pcsx2/x86/ix86/ix86_instructions.h | 458 ++++++++++++-------------- pcsx2/x86/ix86/ix86_jmp.cpp | 22 +- pcsx2/x86/ix86/ix86_legacy.cpp | 192 +++++------ pcsx2/x86/ix86/ix86_legacy_mmx.cpp | 34 +- pcsx2/x86/ix86/ix86_legacy_sse.cpp | 172 ++++------ pcsx2/x86/ix86/ix86_types.h | 229 +++++++------ 20 files changed, 1105 insertions(+), 1110 deletions(-) diff --git a/pcsx2/x86/iVUmicroLower.cpp b/pcsx2/x86/iVUmicroLower.cpp index 0a7a73117a..f98ed4549c 100644 --- a/pcsx2/x86/iVUmicroLower.cpp +++ b/pcsx2/x86/iVUmicroLower.cpp @@ -802,12 +802,12 @@ void _saveEAX(VURegs *VU, int x86reg, uptr offset, int info) // (this is one of my test cases for the new emitter --air) using namespace x86Emitter; - iAddressReg thisreg( x86reg ); + xAddressReg thisreg( x86reg ); - if ( _X ) iMOV(ptr32[thisreg+offset], 0x00000000); - if ( _Y ) iMOV(ptr32[thisreg+offset+4], 0x00000000); - if ( _Z ) iMOV(ptr32[thisreg+offset+8], 0x00000000); - if ( _W ) iMOV(ptr32[thisreg+offset+12], 0x3f800000); + if ( _X ) xMOV(ptr32[thisreg+offset], 0x00000000); + if ( _Y ) xMOV(ptr32[thisreg+offset+4], 0x00000000); + if ( _Z ) xMOV(ptr32[thisreg+offset+8], 0x00000000); + if ( _W ) xMOV(ptr32[thisreg+offset+12], 0x3f800000); } return; } diff --git a/pcsx2/x86/ix86-32/recVTLB.cpp b/pcsx2/x86/ix86-32/recVTLB.cpp index a518b04388..1f1960eb5d 100644 --- a/pcsx2/x86/ix86-32/recVTLB.cpp +++ b/pcsx2/x86/ix86-32/recVTLB.cpp @@ -34,20 +34,20 @@ void MOV128_MtoM( x86IntRegType destRm, x86IntRegType srcRm ) { // (this is one of my test cases for the new emitter --air) - iAddressReg src( srcRm ); - iAddressReg dest( destRm ); + xAddressReg src( srcRm ); + xAddressReg dest( destRm ); - iMOV( eax, ptr[src] ); - iMOV( ptr[dest], eax ); + xMOV( eax, ptr[src] ); + xMOV( ptr[dest], eax ); - iMOV( eax, ptr[src+4] ); - iMOV( ptr[dest+4], eax ); + xMOV( eax, ptr[src+4] ); + xMOV( ptr[dest+4], eax ); - iMOV( eax, ptr[src+8] ); - iMOV( ptr[dest+8], eax ); + xMOV( eax, ptr[src+8] ); + xMOV( ptr[dest+8], eax ); - iMOV( eax, ptr[src+12] ); - iMOV( ptr[dest+12], eax ); + xMOV( eax, ptr[src+12] ); + xMOV( ptr[dest+12], eax ); } /* @@ -200,10 +200,10 @@ void vtlb_DynGenRead64(u32 bits) SHR32ItoR(EAX,VTLB_PAGE_BITS); MOV32RmSOffsettoR(EAX,EAX,(int)vtlbdata.vmap,2); ADD32RtoR(ECX,EAX); - iForwardJS8 _fullread; + xForwardJS8 _fullread; _vtlb_DynGen_DirectRead( bits, false ); - iForwardJump8 cont; + xForwardJump8 cont; _fullread.SetTarget(); @@ -223,10 +223,10 @@ void vtlb_DynGenRead32(u32 bits, bool sign) SHR32ItoR(EAX,VTLB_PAGE_BITS); MOV32RmSOffsettoR(EAX,EAX,(int)vtlbdata.vmap,2); ADD32RtoR(ECX,EAX); - iForwardJS8 _fullread; + xForwardJS8 _fullread; _vtlb_DynGen_DirectRead( bits, sign ); - iForwardJump8 cont; + xForwardJump8 cont; _fullread.SetTarget(); _vtlb_DynGen_IndirectRead( bits ); @@ -478,10 +478,10 @@ void vtlb_DynGenWrite(u32 sz) SHR32ItoR(EAX,VTLB_PAGE_BITS); MOV32RmSOffsettoR(EAX,EAX,(int)vtlbdata.vmap,2); ADD32RtoR(ECX,EAX); - iForwardJS8 _full; + xForwardJS8 _full; _vtlb_DynGen_DirectWrite( sz ); - iForwardJump8 cont; + xForwardJump8 cont; _full.SetTarget(); _vtlb_DynGen_IndirectWrite( sz ); diff --git a/pcsx2/x86/ix86/implement/bittest.h b/pcsx2/x86/ix86/implement/bittest.h index dd3d8fcc73..5ad091667d 100644 --- a/pcsx2/x86/ix86/implement/bittest.h +++ b/pcsx2/x86/ix86/implement/bittest.h @@ -41,54 +41,54 @@ class Group8Impl protected: static const uint OperandSize = sizeof(ImmType); - static void prefix16() { if( OperandSize == 2 ) iWrite( 0x66 ); } + static void prefix16() { if( OperandSize == 2 ) xWrite( 0x66 ); } public: Group8Impl() {} // For the love of GCC. // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& bitbase, const iRegister& bitoffset ) + static __emitinline void Emit( const xRegister& bitbase, const xRegister& bitoffset ) { prefix16(); - iWrite( 0x0f ); - iWrite( 0xa3 | (InstType << 2) ); + xWrite( 0x0f ); + xWrite( 0xa3 | (InstType << 2) ); ModRM_Direct( bitoffset.Id, bitbase.Id ); } // ------------------------------------------------------------------------ - static __emitinline void Emit( void* bitbase, const iRegister& bitoffset ) + static __emitinline void Emit( void* bitbase, const xRegister& bitoffset ) { prefix16(); - iWrite( 0x0f ); - iWrite( 0xa3 | (InstType << 2) ); - iWriteDisp( bitoffset.Id, bitbase ); + xWrite( 0x0f ); + xWrite( 0xa3 | (InstType << 2) ); + xWriteDisp( bitoffset.Id, bitbase ); } // ------------------------------------------------------------------------ - static __emitinline void Emit( const ModSibBase& bitbase, const iRegister& bitoffset ) + static __emitinline void Emit( const ModSibBase& bitbase, const xRegister& bitoffset ) { prefix16(); - iWrite( 0x0f ); - iWrite( 0xa3 | (InstType << 2) ); + xWrite( 0x0f ); + xWrite( 0xa3 | (InstType << 2) ); EmitSibMagic( bitoffset.Id, bitbase ); } // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& bitbase, u8 immoffset ) + static __emitinline void Emit( const xRegister& bitbase, u8 immoffset ) { prefix16(); - iWrite( 0xba0f ); + xWrite( 0xba0f ); ModRM_Direct( InstType, bitbase.Id ); - iWrite( immoffset ); + xWrite( immoffset ); } // ------------------------------------------------------------------------ static __emitinline void Emit( const ModSibStrict& bitbase, u8 immoffset ) { prefix16(); - iWrite( 0xba0f ); + xWrite( 0xba0f ); EmitSibMagic( InstType, bitbase ); - iWrite( immoffset ); + xWrite( immoffset ); } }; @@ -102,12 +102,12 @@ protected: typedef Group8Impl m_16; public: - __forceinline void operator()( const iRegister32& bitbase, const iRegister32& bitoffset ) const { m_32::Emit( bitbase, bitoffset ); } - __forceinline void operator()( const iRegister16& bitbase, const iRegister16& bitoffset ) const { m_16::Emit( bitbase, bitoffset ); } - __forceinline void operator()( void* bitbase, const iRegister32& bitoffset ) const { m_32::Emit( bitbase, bitoffset ); } - __forceinline void operator()( void* bitbase, const iRegister16& bitoffset ) const { m_16::Emit( bitbase, bitoffset ); } - __noinline void operator()( const ModSibBase& bitbase, const iRegister32& bitoffset ) const { m_32::Emit( bitbase, bitoffset ); } - __noinline void operator()( const ModSibBase& bitbase, const iRegister16& bitoffset ) const { m_16::Emit( bitbase, bitoffset ); } + __forceinline void operator()( const xRegister32& bitbase, const xRegister32& bitoffset ) const { m_32::Emit( bitbase, bitoffset ); } + __forceinline void operator()( const xRegister16& bitbase, const xRegister16& bitoffset ) const { m_16::Emit( bitbase, bitoffset ); } + __forceinline void operator()( void* bitbase, const xRegister32& bitoffset ) const { m_32::Emit( bitbase, bitoffset ); } + __forceinline void operator()( void* bitbase, const xRegister16& bitoffset ) const { m_16::Emit( bitbase, bitoffset ); } + __noinline void operator()( const ModSibBase& bitbase, const xRegister32& bitoffset ) const { m_32::Emit( bitbase, bitoffset ); } + __noinline void operator()( const ModSibBase& bitbase, const xRegister16& bitoffset ) const { m_16::Emit( bitbase, bitoffset ); } // Note on Imm forms : use int as the source operand since it's "reasonably inert" from a compiler // perspective. (using uint tends to make the compiler try and fail to match signed immediates with @@ -115,8 +115,8 @@ public: __noinline void operator()( const ModSibStrict& bitbase, u8 immoffset ) const { m_32::Emit( bitbase, immoffset ); } __noinline void operator()( const ModSibStrict& bitbase, u8 immoffset ) const { m_16::Emit( bitbase, immoffset ); } - void operator()( const iRegister& bitbase, u8 immoffset ) const { m_32::Emit( bitbase, immoffset ); } - void operator()( const iRegister& bitbase, u8 immoffset ) const { m_16::Emit( bitbase, immoffset ); } + void operator()( const xRegister& bitbase, u8 immoffset ) const { m_32::Emit( bitbase, immoffset ); } + void operator()( const xRegister& bitbase, u8 immoffset ) const { m_16::Emit( bitbase, immoffset ); } Group8ImplAll() {} }; @@ -130,33 +130,33 @@ class BitScanImpl { protected: static const uint OperandSize = sizeof(ImmType); - static void prefix16() { if( OperandSize == 2 ) iWrite( 0x66 ); } + static void prefix16() { if( OperandSize == 2 ) xWrite( 0x66 ); } static void emitbase() { prefix16(); - iWrite( 0x0f ); - iWrite( isReverse ? 0xbd : 0xbc ); + xWrite( 0x0f ); + xWrite( isReverse ? 0xbd : 0xbc ); } public: BitScanImpl() {} // For the love of GCC. // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, const iRegister& from ) + static __emitinline void Emit( const xRegister& to, const xRegister& from ) { emitbase(); ModRM_Direct( to.Id, from.Id ); } // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, const void* src ) + static __emitinline void Emit( const xRegister& to, const void* src ) { emitbase(); - iWriteDisp( to.Id, src ); + xWriteDisp( to.Id, src ); } // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, const ModSibBase& sibsrc ) + static __emitinline void Emit( const xRegister& to, const ModSibBase& sibsrc ) { emitbase(); EmitSibMagic( to.Id, sibsrc ); @@ -175,12 +175,12 @@ protected: typedef BitScanImpl m_16; public: - __forceinline void operator()( const iRegister32& to, const iRegister32& from ) const { m_32::Emit( to, from ); } - __forceinline void operator()( const iRegister16& to, const iRegister16& from ) const { m_16::Emit( to, from ); } - __forceinline void operator()( const iRegister32& to, const void* src ) const { m_32::Emit( to, src ); } - __forceinline void operator()( const iRegister16& to, const void* src ) const { m_16::Emit( to, src ); } - __noinline void operator()( const iRegister32& to, const ModSibBase& sibsrc ) const { m_32::Emit( to, sibsrc ); } - __noinline void operator()( const iRegister16& to, const ModSibBase& sibsrc ) const { m_16::Emit( to, sibsrc ); } + __forceinline void operator()( const xRegister32& to, const xRegister32& from ) const { m_32::Emit( to, from ); } + __forceinline void operator()( const xRegister16& to, const xRegister16& from ) const { m_16::Emit( to, from ); } + __forceinline void operator()( const xRegister32& to, const void* src ) const { m_32::Emit( to, src ); } + __forceinline void operator()( const xRegister16& to, const void* src ) const { m_16::Emit( to, src ); } + __noinline void operator()( const xRegister32& to, const ModSibBase& sibsrc ) const { m_32::Emit( to, sibsrc ); } + __noinline void operator()( const xRegister16& to, const ModSibBase& sibsrc ) const { m_16::Emit( to, sibsrc ); } BitScanImplAll() {} }; diff --git a/pcsx2/x86/ix86/implement/dwshift.h b/pcsx2/x86/ix86/implement/dwshift.h index 7fb64f4b7a..390577ae20 100644 --- a/pcsx2/x86/ix86/implement/dwshift.h +++ b/pcsx2/x86/ix86/implement/dwshift.h @@ -33,7 +33,7 @@ protected: static const uint OperandSize = sizeof(ImmType); static bool Is8BitOperand() { return OperandSize == 1; } - static void prefix16() { if( OperandSize == 2 ) iWrite( 0x66 ); } + static void prefix16() { if( OperandSize == 2 ) xWrite( 0x66 ); } static void basesibform( bool isCL ) { @@ -46,7 +46,7 @@ public: DwordShiftImpl() {} // because GCC doesn't like static classes // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, const iRegister& from ) + static __emitinline void Emit( const xRegister& to, const xRegister& from ) { prefix16(); write16( 0xa50f | (isShiftRight ? 0x800 : 0) ); @@ -54,7 +54,7 @@ public: } // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, const iRegister& from, u8 imm ) + static __emitinline void Emit( const xRegister& to, const xRegister& from, u8 imm ) { if( imm == 0 ) return; prefix16(); @@ -64,14 +64,14 @@ public: } // ------------------------------------------------------------------------ - static __emitinline void Emit( const ModSibBase& sibdest, const iRegister& from, __unused const iRegisterCL& clreg ) + static __emitinline void Emit( const ModSibBase& sibdest, const xRegister& from, __unused const xRegisterCL& clreg ) { basesibform(); EmitSibMagic( from.Id, sibdest ); } // ------------------------------------------------------------------------ - static __emitinline void Emit( const ModSibBase& sibdest, const iRegister& from, u8 imm ) + static __emitinline void Emit( const ModSibBase& sibdest, const xRegister& from, u8 imm ) { basesibform(); EmitSibMagic( from.Id, sibdest ); @@ -80,18 +80,18 @@ public: // ------------------------------------------------------------------------ // dest data type is inferred from the 'from' register, so we can do void* resolution :) - static __emitinline void Emit( void* dest, const iRegister& from, __unused const iRegisterCL& clreg ) + static __emitinline void Emit( void* dest, const xRegister& from, __unused const xRegisterCL& clreg ) { basesibform(); - iWriteDisp( from.Id, dest ); + xWriteDisp( from.Id, dest ); } // ------------------------------------------------------------------------ // dest data type is inferred from the 'from' register, so we can do void* resolution :) - static __emitinline void Emit( void* dest, const iRegister& from, u8 imm ) + static __emitinline void Emit( void* dest, const xRegister& from, u8 imm ) { basesibform(); - iWriteDisp( from.Id, dest ); + xWriteDisp( from.Id, dest ); write8( imm ); } }; @@ -110,20 +110,20 @@ protected: public: // ---------- 32 Bit Interface ----------- - __forceinline void operator()( const iRegister32& to, const iRegister32& from, __unused const iRegisterCL& clreg ) const { m_32::Emit( to, from ); } - __forceinline void operator()( void* dest, const iRegister32& from, __unused const iRegisterCL& clreg ) const { m_32::Emit( dest, from ); } - __noinline void operator()( const ModSibBase& sibdest, const iRegister32& from, __unused const iRegisterCL& clreg ) const { m_32::Emit( sibdest, from ); } - __forceinline void operator()( const iRegister32& to, const iRegister32& from, u8 imm ) const { m_32::Emit( to, from, imm ); } - __forceinline void operator()( void* dest, const iRegister32& from, u8 imm ) const { m_32::Emit( dest, from, imm ); } - __noinline void operator()( const ModSibBase& sibdest, const iRegister32& from, u8 imm ) const { m_32::Emit( sibdest, from ); } + __forceinline void operator()( const xRegister32& to, const xRegister32& from, __unused const xRegisterCL& clreg ) const { m_32::Emit( to, from ); } + __forceinline void operator()( void* dest, const xRegister32& from, __unused const xRegisterCL& clreg ) const { m_32::Emit( dest, from ); } + __noinline void operator()( const ModSibBase& sibdest, const xRegister32& from, __unused const xRegisterCL& clreg ) const { m_32::Emit( sibdest, from ); } + __forceinline void operator()( const xRegister32& to, const xRegister32& from, u8 imm ) const { m_32::Emit( to, from, imm ); } + __forceinline void operator()( void* dest, const xRegister32& from, u8 imm ) const { m_32::Emit( dest, from, imm ); } + __noinline void operator()( const ModSibBase& sibdest, const xRegister32& from, u8 imm ) const { m_32::Emit( sibdest, from ); } // ---------- 16 Bit Interface ----------- - __forceinline void operator()( const iRegister16& to, const iRegister16& from, __unused const iRegisterCL& clreg ) const { m_16::Emit( to, from ); } - __forceinline void operator()( void* dest, const iRegister16& from, __unused const iRegisterCL& clreg ) const { m_16::Emit( dest, from ); } - __noinline void operator()( const ModSibBase& sibdest, const iRegister16& from, __unused const iRegisterCL& clreg ) const { m_16::Emit( sibdest, from ); } - __forceinline void operator()( const iRegister16& to, const iRegister16& from, u8 imm ) const { m_16::Emit( to, from, imm ); } - __forceinline void operator()( void* dest, const iRegister16& from, u8 imm ) const { m_16::Emit( dest, from, imm ); } - __noinline void operator()( const ModSibBase& sibdest, const iRegister16& from, u8 imm ) const { m_16::Emit( sibdest, from ); } + __forceinline void operator()( const xRegister16& to, const xRegister16& from, __unused const xRegisterCL& clreg ) const { m_16::Emit( to, from ); } + __forceinline void operator()( void* dest, const xRegister16& from, __unused const xRegisterCL& clreg ) const { m_16::Emit( dest, from ); } + __noinline void operator()( const ModSibBase& sibdest, const xRegister16& from, __unused const xRegisterCL& clreg ) const { m_16::Emit( sibdest, from ); } + __forceinline void operator()( const xRegister16& to, const xRegister16& from, u8 imm ) const { m_16::Emit( to, from, imm ); } + __forceinline void operator()( void* dest, const xRegister16& from, u8 imm ) const { m_16::Emit( dest, from, imm ); } + __noinline void operator()( const ModSibBase& sibdest, const xRegister16& from, u8 imm ) const { m_16::Emit( sibdest, from ); } DwordShiftImplAll() {} // Why does GCC need these? }; diff --git a/pcsx2/x86/ix86/implement/group1.h b/pcsx2/x86/ix86/implement/group1.h index 8089593cc3..3979e2cff4 100644 --- a/pcsx2/x86/ix86/implement/group1.h +++ b/pcsx2/x86/ix86/implement/group1.h @@ -41,65 +41,65 @@ protected: static const uint OperandSize = sizeof(ImmType); static bool Is8BitOperand() { return OperandSize == 1; } - static void prefix16() { if( OperandSize == 2 ) iWrite( 0x66 ); } + static void prefix16() { if( OperandSize == 2 ) xWrite( 0x66 ); } public: Group1Impl() {} // because GCC doesn't like static classes - static __emitinline void Emit( G1Type InstType, const iRegister& to, const iRegister& from ) + static __emitinline void Emit( G1Type InstType, const xRegister& to, const xRegister& from ) { prefix16(); - iWrite( (Is8BitOperand() ? 0 : 1) | (InstType<<3) ); + xWrite( (Is8BitOperand() ? 0 : 1) | (InstType<<3) ); ModRM_Direct( from.Id, to.Id ); } - static __emitinline void Emit( G1Type InstType, const ModSibBase& sibdest, const iRegister& from ) + static __emitinline void Emit( G1Type InstType, const ModSibBase& sibdest, const xRegister& from ) { prefix16(); - iWrite( (Is8BitOperand() ? 0 : 1) | (InstType<<3) ); + xWrite( (Is8BitOperand() ? 0 : 1) | (InstType<<3) ); EmitSibMagic( from.Id, sibdest ); } - static __emitinline void Emit( G1Type InstType, const iRegister& to, const ModSibBase& sibsrc ) + static __emitinline void Emit( G1Type InstType, const xRegister& to, const ModSibBase& sibsrc ) { prefix16(); - iWrite( (Is8BitOperand() ? 2 : 3) | (InstType<<3) ); + xWrite( (Is8BitOperand() ? 2 : 3) | (InstType<<3) ); EmitSibMagic( to.Id, sibsrc ); } - static __emitinline void Emit( G1Type InstType, void* dest, const iRegister& from ) + static __emitinline void Emit( G1Type InstType, void* dest, const xRegister& from ) { prefix16(); - iWrite( (Is8BitOperand() ? 0 : 1) | (InstType<<3) ); - iWriteDisp( from.Id, dest ); + xWrite( (Is8BitOperand() ? 0 : 1) | (InstType<<3) ); + xWriteDisp( from.Id, dest ); } - static __emitinline void Emit( G1Type InstType, const iRegister& to, const void* src ) + static __emitinline void Emit( G1Type InstType, const xRegister& to, const void* src ) { prefix16(); - iWrite( (Is8BitOperand() ? 2 : 3) | (InstType<<3) ); - iWriteDisp( to.Id, src ); + xWrite( (Is8BitOperand() ? 2 : 3) | (InstType<<3) ); + xWriteDisp( to.Id, src ); } - static __emitinline void Emit( G1Type InstType, const iRegister& to, int imm ) + static __emitinline void Emit( G1Type InstType, const xRegister& to, int imm ) { prefix16(); if( !Is8BitOperand() && is_s8( imm ) ) { - iWrite( 0x83 ); + xWrite( 0x83 ); ModRM_Direct( InstType, to.Id ); - iWrite( imm ); + xWrite( imm ); } else { if( to.IsAccumulator() ) - iWrite( (Is8BitOperand() ? 4 : 5) | (InstType<<3) ); + xWrite( (Is8BitOperand() ? 4 : 5) | (InstType<<3) ); else { - iWrite( Is8BitOperand() ? 0x80 : 0x81 ); + xWrite( Is8BitOperand() ? 0x80 : 0x81 ); ModRM_Direct( InstType, to.Id ); } - iWrite( imm ); + xWrite( imm ); } } @@ -107,19 +107,19 @@ public: { if( Is8BitOperand() ) { - iWrite( 0x80 ); + xWrite( 0x80 ); EmitSibMagic( InstType, sibdest ); - iWrite( imm ); + xWrite( imm ); } else { prefix16(); - iWrite( is_s8( imm ) ? 0x83 : 0x81 ); + xWrite( is_s8( imm ) ? 0x83 : 0x81 ); EmitSibMagic( InstType, sibdest ); if( is_s8( imm ) ) - iWrite( imm ); + xWrite( imm ); else - iWrite( imm ); + xWrite( imm ); } } }; @@ -132,15 +132,15 @@ class Group1ImplAll { public: template< typename T > - __forceinline void operator()( const iRegister& to, const iRegister& from ) const { Group1Impl::Emit( InstType, to, from ); } + __forceinline void operator()( const xRegister& to, const xRegister& from ) const { Group1Impl::Emit( InstType, to, from ); } template< typename T > - __forceinline void operator()( const iRegister& to, const void* src ) const { Group1Impl::Emit( InstType, to, src ); } + __forceinline void operator()( const xRegister& to, const void* src ) const { Group1Impl::Emit( InstType, to, src ); } template< typename T > - __forceinline void operator()( void* dest, const iRegister& from ) const { Group1Impl::Emit( InstType, dest, from ); } + __forceinline void operator()( void* dest, const xRegister& from ) const { Group1Impl::Emit( InstType, dest, from ); } template< typename T > - __noinline void operator()( const ModSibBase& sibdest, const iRegister& from ) const { Group1Impl::Emit( InstType, sibdest, from ); } + __noinline void operator()( const ModSibBase& sibdest, const xRegister& from ) const { Group1Impl::Emit( InstType, sibdest, from ); } template< typename T > - __noinline void operator()( const iRegister& to, const ModSibBase& sibsrc ) const { Group1Impl::Emit( InstType, to, sibsrc ); } + __noinline void operator()( const xRegister& to, const ModSibBase& sibsrc ) const { Group1Impl::Emit( InstType, to, sibsrc ); } // Note on Imm forms : use int as the source operand since it's "reasonably inert" from a compiler // perspective. (using uint tends to make the compiler try and fail to match signed immediates with @@ -149,38 +149,60 @@ public: template< typename T > __noinline void operator()( const ModSibStrict& sibdest, int imm ) const { Group1Impl::Emit( InstType, sibdest, imm ); } template< typename T > - __forceinline void operator()( const iRegister& to, int imm ) const { Group1Impl::Emit( InstType, to, imm ); } + __forceinline void operator()( const xRegister& to, int imm ) const { Group1Impl::Emit( InstType, to, imm ); } Group1ImplAll() {} // Why does GCC need these? }; +// ------------------------------------------------------------------------ +// This class combines x86 with SSE/SSE2 logic operations (ADD, OR, and NOT). +// Note: ANDN [AndNot] is handled below separately. +// template< G1Type InstType, u8 OpcodeSSE > -class G1LogicImpl : public Group1ImplAll +class G1LogicImpl_PlusSSE : public Group1ImplAll { public: + using Group1ImplAll::operator(); + const SSELogicImpl<0x00,OpcodeSSE> PS; const SSELogicImpl<0x66,OpcodeSSE> PD; - G1LogicImpl() {} + G1LogicImpl_PlusSSE() {} }; +// ------------------------------------------------------------------------ +// This calss combines x86 with SSE/SSE2 arithmetic operations (ADD/SUB). +// template< G1Type InstType, u8 OpcodeSSE > -class G1ArithmeticImpl : public G1LogicImpl +class G1ArithmeticImpl_PlusSSE : public G1LogicImpl_PlusSSE { public: + using Group1ImplAll::operator(); + const SSELogicImpl<0xf3,OpcodeSSE> SS; const SSELogicImpl<0xf2,OpcodeSSE> SD; - G1ArithmeticImpl() {} + G1ArithmeticImpl_PlusSSE() {} }; - -template< u8 OpcodeSSE > -class SSEAndNotImpl +// ------------------------------------------------------------------------ +class G1CompareImpl_PlusSSE : Group1ImplAll< G1Type_CMP > { -public: - const SSELogicImpl<0x00,OpcodeSSE> PS; - const SSELogicImpl<0x66,OpcodeSSE> PD; +protected: + template< u8 Prefix > struct Woot + { + __forceinline void operator()( const xRegisterSSE& to, const xRegisterSSE& from, SSE2_ComparisonType cmptype ) const { writeXMMop( Prefix, 0xc2, to, from ); xWrite( cmptype ); } + __forceinline void operator()( const xRegisterSSE& to, const void* from, SSE2_ComparisonType cmptype ) const { writeXMMop( Prefix, 0xc2, to, from ); xWrite( cmptype ); } + __noinline void operator()( const xRegisterSSE& to, const ModSibBase& from, SSE2_ComparisonType cmptype ) const { writeXMMop( Prefix, 0xc2, to, from ); xWrite( cmptype ); } + }; - SSEAndNotImpl() {} -}; \ No newline at end of file +public: + using Group1ImplAll< G1Type_CMP >::operator(); + + Woot<0x00> PS; + Woot<0x66> PD; + Woot<0xf3> SS; + Woot<0xf2> SD; + + G1CompareImpl_PlusSSE() {} //GCWhat? +}; diff --git a/pcsx2/x86/ix86/implement/group2.h b/pcsx2/x86/ix86/implement/group2.h index a694263008..45a5430d90 100644 --- a/pcsx2/x86/ix86/implement/group2.h +++ b/pcsx2/x86/ix86/implement/group2.h @@ -45,21 +45,21 @@ protected: static const uint OperandSize = sizeof(ImmType); static bool Is8BitOperand() { return OperandSize == 1; } - static void prefix16() { if( OperandSize == 2 ) iWrite( 0x66 ); } + static void prefix16() { if( OperandSize == 2 ) xWrite( 0x66 ); } public: Group2Impl() {} // For the love of GCC. // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to ) + static __emitinline void Emit( const xRegister& to ) { prefix16(); - iWrite( Is8BitOperand() ? 0xd2 : 0xd3 ); + xWrite( Is8BitOperand() ? 0xd2 : 0xd3 ); ModRM_Direct( InstType, to.Id ); } // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, u8 imm ) + static __emitinline void Emit( const xRegister& to, u8 imm ) { if( imm == 0 ) return; @@ -67,14 +67,14 @@ public: if( imm == 1 ) { // special encoding of 1's - iWrite( Is8BitOperand() ? 0xd0 : 0xd1 ); + xWrite( Is8BitOperand() ? 0xd0 : 0xd1 ); ModRM_Direct( InstType, to.Id ); } else { - iWrite( Is8BitOperand() ? 0xc0 : 0xc1 ); + xWrite( Is8BitOperand() ? 0xc0 : 0xc1 ); ModRM_Direct( InstType, to.Id ); - iWrite( imm ); + xWrite( imm ); } } @@ -82,7 +82,7 @@ public: static __emitinline void Emit( const ModSibStrict& sibdest ) { prefix16(); - iWrite( Is8BitOperand() ? 0xd2 : 0xd3 ); + xWrite( Is8BitOperand() ? 0xd2 : 0xd3 ); EmitSibMagic( InstType, sibdest ); } @@ -95,14 +95,14 @@ public: if( imm == 1 ) { // special encoding of 1's - iWrite( Is8BitOperand() ? 0xd0 : 0xd1 ); + xWrite( Is8BitOperand() ? 0xd0 : 0xd1 ); EmitSibMagic( InstType, sibdest ); } else { - iWrite( Is8BitOperand() ? 0xc0 : 0xc1 ); + xWrite( Is8BitOperand() ? 0xc0 : 0xc1 ); EmitSibMagic( InstType, sibdest ); - iWrite( imm ); + xWrite( imm ); } } }; @@ -113,16 +113,16 @@ template< G2Type InstType > class Group2ImplAll { public: - template< typename T > __forceinline void operator()( const iRegister& to, __unused const iRegisterCL& from ) const + template< typename T > __forceinline void operator()( const xRegister& to, __unused const xRegisterCL& from ) const { Group2Impl::Emit( to ); } - template< typename T > __noinline void operator()( const ModSibStrict& sibdest, __unused const iRegisterCL& from ) const + template< typename T > __noinline void operator()( const ModSibStrict& sibdest, __unused const xRegisterCL& from ) const { Group2Impl::Emit( sibdest ); } template< typename T > __noinline void operator()( const ModSibStrict& sibdest, u8 imm ) const { Group2Impl::Emit( sibdest, imm ); } - template< typename T > __forceinline void operator()( const iRegister& to, u8 imm ) const + template< typename T > __forceinline void operator()( const xRegister& to, u8 imm ) const { Group2Impl::Emit( to, imm ); } Group2ImplAll() {} // I am a class with no members, so I need an explicit constructor! Sense abounds. diff --git a/pcsx2/x86/ix86/implement/group3.h b/pcsx2/x86/ix86/implement/group3.h index a614e4b09d..aae0d77652 100644 --- a/pcsx2/x86/ix86/implement/group3.h +++ b/pcsx2/x86/ix86/implement/group3.h @@ -31,6 +31,7 @@ enum G3Type G3Type_iDIV = 7 }; +// ------------------------------------------------------------------------ template< typename ImmType > class Group3Impl { @@ -38,22 +39,22 @@ protected: static const uint OperandSize = sizeof(ImmType); static bool Is8BitOperand() { return OperandSize == 1; } - static void prefix16() { if( OperandSize == 2 ) iWrite( 0x66 ); } + static void prefix16() { if( OperandSize == 2 ) xWrite( 0x66 ); } public: Group3Impl() {} // For the love of GCC. - static __emitinline void Emit( G3Type InstType, const iRegister& from ) + static __emitinline void Emit( G3Type InstType, const xRegister& from ) { prefix16(); - iWrite(Is8BitOperand() ? 0xf6 : 0xf7 ); + xWrite(Is8BitOperand() ? 0xf6 : 0xf7 ); ModRM_Direct( InstType, from.Id ); } static __emitinline void Emit( G3Type InstType, const ModSibStrict& sibsrc ) { prefix16(); - iWrite( Is8BitOperand() ? 0xf6 : 0xf7 ); + xWrite( Is8BitOperand() ? 0xf6 : 0xf7 ); EmitSibMagic( InstType, sibsrc ); } }; @@ -65,7 +66,7 @@ class Group3ImplAll { public: template< typename T > - __forceinline void operator()( const iRegister& from ) const { Group3Impl::Emit( InstType, from ); } + __forceinline void operator()( const xRegister& from ) const { Group3Impl::Emit( InstType, from ); } template< typename T > __noinline void operator()( const ModSibStrict& from ) const { Group3Impl::Emit( InstType, from ); } @@ -73,7 +74,9 @@ public: Group3ImplAll() {} }; - +// ------------------------------------------------------------------------ +// This class combines x86 and SSE/SSE2 instructions for iMUL and iDIV. +// template< G3Type InstType, u8 OpcodeSSE > class G3Impl_PlusSSE : public Group3ImplAll { @@ -94,11 +97,11 @@ class iMulImpl { protected: static const uint OperandSize = sizeof(ImmType); - static void prefix16() { if( OperandSize == 2 ) iWrite( 0x66 ); } + static void prefix16() { if( OperandSize == 2 ) xWrite( 0x66 ); } public: // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, const iRegister& from ) + static __emitinline void Emit( const xRegister& to, const xRegister& from ) { prefix16(); write16( 0xaf0f ); @@ -106,15 +109,15 @@ public: } // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, const void* src ) + static __emitinline void Emit( const xRegister& to, const void* src ) { prefix16(); write16( 0xaf0f ); - iWriteDisp( to.Id, src ); + xWriteDisp( to.Id, src ); } // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, const ModSibBase& src ) + static __emitinline void Emit( const xRegister& to, const ModSibBase& src ) { prefix16(); write16( 0xaf0f ); @@ -122,7 +125,7 @@ public: } // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, const iRegister& from, ImmType imm ) + static __emitinline void Emit( const xRegister& to, const xRegister& from, ImmType imm ) { prefix16(); write16( is_s8( imm ) ? 0x6b : 0x69 ); @@ -130,23 +133,23 @@ public: if( is_s8( imm ) ) write8( imm ); else - iWrite( imm ); + xWrite( imm ); } // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, const void* src, ImmType imm ) + static __emitinline void Emit( const xRegister& to, const void* src, ImmType imm ) { prefix16(); write16( is_s8( imm ) ? 0x6b : 0x69 ); - iWriteDisp( to.Id, src ); + xWriteDisp( to.Id, src ); if( is_s8( imm ) ) write8( imm ); else - iWrite( imm ); + xWrite( imm ); } // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, const ModSibBase& src, ImmType imm ) + static __emitinline void Emit( const xRegister& to, const ModSibBase& src, ImmType imm ) { prefix16(); write16( is_s8( imm ) ? 0x6b : 0x69 ); @@ -154,11 +157,11 @@ public: if( is_s8( imm ) ) write8( imm ); else - iWrite( imm ); + xWrite( imm ); } }; - +// ------------------------------------------------------------------------ class iMul_PlusSSE : public G3Impl_PlusSSE { protected: @@ -166,24 +169,19 @@ protected: typedef iMulImpl iMUL16; public: + using G3Impl_PlusSSE::operator(); + + __forceinline void operator()( const xRegister32& to, const xRegister32& from ) const { iMUL32::Emit( to, from ); } + __forceinline void operator()( const xRegister32& to, const void* src ) const { iMUL32::Emit( to, src ); } + __forceinline void operator()( const xRegister32& to, const xRegister32& from, s32 imm ) const{ iMUL32::Emit( to, from, imm ); } + __noinline void operator()( const xRegister32& to, const ModSibBase& src ) const { iMUL32::Emit( to, src ); } + __noinline void operator()( const xRegister32& to, const ModSibBase& from, s32 imm ) const { iMUL32::Emit( to, from, imm ); } - template< typename T > - __forceinline void operator()( const iRegister& from ) const { Group3Impl::Emit( G3Type_iMUL, from ); } - - template< typename T > - __noinline void operator()( const ModSibStrict& from ) const { Group3Impl::Emit( G3Type_iMUL, from ); } - - __forceinline void operator()( const iRegister32& to, const iRegister32& from ) const { iMUL32::Emit( to, from ); } - __forceinline void operator()( const iRegister32& to, const void* src ) const { iMUL32::Emit( to, src ); } - __forceinline void operator()( const iRegister32& to, const iRegister32& from, s32 imm ) const{ iMUL32::Emit( to, from, imm ); } - __noinline void operator()( const iRegister32& to, const ModSibBase& src ) const { iMUL32::Emit( to, src ); } - __noinline void operator()( const iRegister32& to, const ModSibBase& from, s32 imm ) const { iMUL32::Emit( to, from, imm ); } - - __forceinline void operator()( const iRegister16& to, const iRegister16& from ) const { iMUL16::Emit( to, from ); } - __forceinline void operator()( const iRegister16& to, const void* src ) const { iMUL16::Emit( to, src ); } - __forceinline void operator()( const iRegister16& to, const iRegister16& from, s16 imm ) const{ iMUL16::Emit( to, from, imm ); } - __noinline void operator()( const iRegister16& to, const ModSibBase& src ) const { iMUL16::Emit( to, src ); } - __noinline void operator()( const iRegister16& to, const ModSibBase& from, s16 imm ) const { iMUL16::Emit( to, from, imm ); } + __forceinline void operator()( const xRegister16& to, const xRegister16& from ) const { iMUL16::Emit( to, from ); } + __forceinline void operator()( const xRegister16& to, const void* src ) const { iMUL16::Emit( to, src ); } + __forceinline void operator()( const xRegister16& to, const xRegister16& from, s16 imm ) const{ iMUL16::Emit( to, from, imm ); } + __noinline void operator()( const xRegister16& to, const ModSibBase& src ) const { iMUL16::Emit( to, src ); } + __noinline void operator()( const xRegister16& to, const ModSibBase& from, s16 imm ) const { iMUL16::Emit( to, from, imm ); } iMul_PlusSSE() {} }; diff --git a/pcsx2/x86/ix86/implement/incdec.h b/pcsx2/x86/ix86/implement/incdec.h index 4aacb81beb..76f5a87b9a 100644 --- a/pcsx2/x86/ix86/implement/incdec.h +++ b/pcsx2/x86/ix86/implement/incdec.h @@ -21,6 +21,8 @@ // Implementations found here: Increment and Decrement Instructions! // Note: This header is meant to be included from within the x86Emitter::Internal namespace. +// ------------------------------------------------------------------------ +// template< typename ImmType > class IncDecImpl { @@ -28,12 +30,12 @@ protected: static const uint OperandSize = sizeof(ImmType); static bool Is8BitOperand() { return OperandSize == 1; } - static void prefix16() { if( OperandSize == 2 ) iWrite( 0x66 ); } + static void prefix16() { if( OperandSize == 2 ) xWrite( 0x66 ); } public: IncDecImpl() {} // For the love of GCC. - static __emitinline void Emit( bool isDec, const iRegister& to ) + static __emitinline void Emit( bool isDec, const xRegister& to ) { // There is no valid 8-bit form of direct register inc/dec, so fall // back on Mod/RM format instead: @@ -67,13 +69,13 @@ protected: typedef IncDecImpl m_8; public: - __forceinline void operator()( const iRegister32& to ) const { m_32::Emit( isDec, to ); } + __forceinline void operator()( const xRegister32& to ) const { m_32::Emit( isDec, to ); } __noinline void operator()( const ModSibStrict& sibdest ) const{ m_32::Emit( isDec, sibdest ); } - __forceinline void operator()( const iRegister16& to ) const { m_16::Emit( isDec, to ); } + __forceinline void operator()( const xRegister16& to ) const { m_16::Emit( isDec, to ); } __noinline void operator()( const ModSibStrict& sibdest ) const{ m_16::Emit( isDec, sibdest ); } - __forceinline void operator()( const iRegister8& to ) const { m_8::Emit( isDec, to ); } + __forceinline void operator()( const xRegister8& to ) const { m_8::Emit( isDec, to ); } __noinline void operator()( const ModSibStrict& sibdest ) const { m_8::Emit( isDec, sibdest ); } IncDecImplAll() {} // don't ask. diff --git a/pcsx2/x86/ix86/implement/jmpcall.h b/pcsx2/x86/ix86/implement/jmpcall.h index bf375432d5..453f2d4e14 100644 --- a/pcsx2/x86/ix86/implement/jmpcall.h +++ b/pcsx2/x86/ix86/implement/jmpcall.h @@ -27,22 +27,22 @@ class JmpCallImpl protected: static const uint OperandSize = sizeof(ImmType); - static void prefix16() { if( OperandSize == 2 ) iWrite( 0x66 ); } + static void prefix16() { if( OperandSize == 2 ) xWrite( 0x66 ); } public: JmpCallImpl() {} // For the love of GCC. - static __emitinline void Emit( bool isJmp, const iRegister& absreg ) + static __emitinline void Emit( bool isJmp, const xRegister& absreg ) { prefix16(); - iWrite( 0xff ); + xWrite( 0xff ); ModRM_Direct( isJmp ? 4 : 2, absreg.Id ); } static __emitinline void Emit( bool isJmp, const ModSibStrict& src ) { prefix16(); - iWrite( 0xff ); + xWrite( 0xff ); EmitSibMagic( isJmp ? 4 : 2, src ); } }; @@ -58,10 +58,10 @@ protected: public: JmpCallImplAll() {} - __forceinline void operator()( const iRegister32& absreg ) const { m_32::Emit( isJmp, absreg ); } + __forceinline void operator()( const xRegister32& absreg ) const { m_32::Emit( isJmp, absreg ); } __forceinline void operator()( const ModSibStrict& src ) const { m_32::Emit( isJmp, src ); } - __forceinline void operator()( const iRegister16& absreg ) const { m_16::Emit( isJmp, absreg ); } + __forceinline void operator()( const xRegister16& absreg ) const { m_16::Emit( isJmp, absreg ); } __forceinline void operator()( const ModSibStrict& src ) const { m_16::Emit( isJmp, src ); } // Special form for calling functions. This form automatically resolves the @@ -77,8 +77,8 @@ public: // always 5 bytes (16 bit calls are bad mojo, so no bother to do special logic). sptr dest = (sptr)func - ((sptr)iGetPtr() + 5); - iWrite( 0xe8 ); - iWrite( dest ); + xWrite( 0xe8 ); + xWrite( dest ); } } diff --git a/pcsx2/x86/ix86/implement/movs.h b/pcsx2/x86/ix86/implement/movs.h index de469a7c10..577df29be3 100644 --- a/pcsx2/x86/ix86/implement/movs.h +++ b/pcsx2/x86/ix86/implement/movs.h @@ -32,23 +32,23 @@ class MovImpl protected: static const uint OperandSize = sizeof(ImmType); static bool Is8BitOperand() { return OperandSize == 1; } - static void prefix16() { if( OperandSize == 2 ) iWrite( 0x66 ); } + static void prefix16() { if( OperandSize == 2 ) xWrite( 0x66 ); } public: MovImpl() {} // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, const iRegister& from ) + static __emitinline void Emit( const xRegister& to, const xRegister& from ) { if( to == from ) return; // ignore redundant MOVs. prefix16(); - iWrite( Is8BitOperand() ? 0x88 : 0x89 ); + xWrite( Is8BitOperand() ? 0x88 : 0x89 ); ModRM_Direct( from.Id, to.Id ); } // ------------------------------------------------------------------------ - static __emitinline void Emit( const ModSibBase& dest, const iRegister& from ) + static __emitinline void Emit( const ModSibBase& dest, const xRegister& from ) { prefix16(); @@ -57,18 +57,18 @@ public: if( from.IsAccumulator() && dest.Index.IsEmpty() && dest.Base.IsEmpty() ) { - iWrite( Is8BitOperand() ? 0xa2 : 0xa3 ); - iWrite( dest.Displacement ); + xWrite( Is8BitOperand() ? 0xa2 : 0xa3 ); + xWrite( dest.Displacement ); } else { - iWrite( Is8BitOperand() ? 0x88 : 0x89 ); + xWrite( Is8BitOperand() ? 0x88 : 0x89 ); EmitSibMagic( from.Id, dest ); } } // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, const ModSibBase& src ) + static __emitinline void Emit( const xRegister& to, const ModSibBase& src ) { prefix16(); @@ -77,18 +77,18 @@ public: if( to.IsAccumulator() && src.Index.IsEmpty() && src.Base.IsEmpty() ) { - iWrite( Is8BitOperand() ? 0xa0 : 0xa1 ); - iWrite( src.Displacement ); + xWrite( Is8BitOperand() ? 0xa0 : 0xa1 ); + xWrite( src.Displacement ); } else { - iWrite( Is8BitOperand() ? 0x8a : 0x8b ); + xWrite( Is8BitOperand() ? 0x8a : 0x8b ); EmitSibMagic( to.Id, src ); } } // ------------------------------------------------------------------------ - static __emitinline void Emit( void* dest, const iRegister& from ) + static __emitinline void Emit( void* dest, const xRegister& from ) { prefix16(); @@ -96,18 +96,18 @@ public: if( from.IsAccumulator() ) { - iWrite( Is8BitOperand() ? 0xa2 : 0xa3 ); - iWrite( (s32)dest ); + xWrite( Is8BitOperand() ? 0xa2 : 0xa3 ); + xWrite( (s32)dest ); } else { - iWrite( Is8BitOperand() ? 0x88 : 0x89 ); - iWriteDisp( from.Id, dest ); + xWrite( Is8BitOperand() ? 0x88 : 0x89 ); + xWriteDisp( from.Id, dest ); } } // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, const void* src ) + static __emitinline void Emit( const xRegister& to, const void* src ) { prefix16(); @@ -115,33 +115,33 @@ public: if( to.IsAccumulator() ) { - iWrite( Is8BitOperand() ? 0xa0 : 0xa1 ); - iWrite( (s32)src ); + xWrite( Is8BitOperand() ? 0xa0 : 0xa1 ); + xWrite( (s32)src ); } else { - iWrite( Is8BitOperand() ? 0x8a : 0x8b ); - iWriteDisp( to.Id, src ); + xWrite( Is8BitOperand() ? 0x8a : 0x8b ); + xWriteDisp( to.Id, src ); } } // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, ImmType imm ) + static __emitinline void Emit( const xRegister& to, ImmType imm ) { // Note: MOV does not have (reg16/32,imm8) forms. prefix16(); - iWrite( (Is8BitOperand() ? 0xb0 : 0xb8) | to.Id ); - iWrite( imm ); + xWrite( (Is8BitOperand() ? 0xb0 : 0xb8) | to.Id ); + xWrite( imm ); } // ------------------------------------------------------------------------ static __emitinline void Emit( ModSibStrict dest, ImmType imm ) { prefix16(); - iWrite( Is8BitOperand() ? 0xc6 : 0xc7 ); + xWrite( Is8BitOperand() ? 0xc6 : 0xc7 ); EmitSibMagic( 0, dest ); - iWrite( imm ); + xWrite( imm ); } }; @@ -150,15 +150,15 @@ class MovImplAll { public: template< typename T > - __forceinline void operator()( const iRegister& to, const iRegister& from ) const { MovImpl::Emit( to, from ); } + __forceinline void operator()( const xRegister& to, const xRegister& from ) const { MovImpl::Emit( to, from ); } template< typename T > - __forceinline void operator()( const iRegister& to, const void* src ) const { MovImpl::Emit( to, src ); } + __forceinline void operator()( const xRegister& to, const void* src ) const { MovImpl::Emit( to, src ); } template< typename T > - __forceinline void operator()( void* dest, const iRegister& from ) const { MovImpl::Emit( dest, from ); } + __forceinline void operator()( void* dest, const xRegister& from ) const { MovImpl::Emit( dest, from ); } template< typename T > - __noinline void operator()( const ModSibBase& sibdest, const iRegister& from ) const { MovImpl::Emit( sibdest, from ); } + __noinline void operator()( const ModSibBase& sibdest, const xRegister& from ) const { MovImpl::Emit( sibdest, from ); } template< typename T > - __noinline void operator()( const iRegister& to, const ModSibBase& sibsrc ) const { MovImpl::Emit( to, sibsrc ); } + __noinline void operator()( const xRegister& to, const ModSibBase& sibsrc ) const { MovImpl::Emit( to, sibsrc ); } template< typename T > __noinline void operator()( const ModSibStrict& sibdest, int imm ) const { MovImpl::Emit( sibdest, imm ); } @@ -167,10 +167,10 @@ public: // the flags (namely replacing mov reg,0 with xor). template< typename T > - __emitinline void operator()( const iRegister& to, int imm, bool preserve_flags=false ) const + __emitinline void operator()( const xRegister& to, int imm, bool preserve_flags=false ) const { if( !preserve_flags && (imm == 0) ) - iXOR( to, to ); + xXOR( to, to ); else MovImpl::Emit( to, imm ); } @@ -193,7 +193,7 @@ protected: static const uint OperandSize = sizeof(ImmType); static bool Is8BitOperand() { return OperandSize == 1; } - static void prefix16() { if( OperandSize == 2 ) iWrite( 0x66 ); } + static void prefix16() { if( OperandSize == 2 ) xWrite( 0x66 ); } static __forceinline void emit_base( JccComparisonType cc ) { @@ -206,27 +206,27 @@ protected: public: CMovSetImpl() {} - static __emitinline void Emit( JccComparisonType cc, const iRegister& to, const iRegister& from ) + static __emitinline void Emit( JccComparisonType cc, const xRegister& to, const xRegister& from ) { if( to == from ) return; emit_base( cc ); ModRM_Direct( to.Id, from.Id ); } - static __emitinline void Emit( JccComparisonType cc, const iRegister& to, const void* src ) + static __emitinline void Emit( JccComparisonType cc, const xRegister& to, const void* src ) { emit_base( cc ); - iWriteDisp( to.Id, src ); + xWriteDisp( to.Id, src ); } - static __emitinline void Emit( JccComparisonType cc, const iRegister& to, const ModSibBase& sibsrc ) + static __emitinline void Emit( JccComparisonType cc, const xRegister& to, const ModSibBase& sibsrc ) { emit_base( cc ); EmitSibMagic( to.Id, sibsrc ); } // This form is provided for SETcc only (not available in CMOV) - static __emitinline void EmitSet( JccComparisonType cc, const iRegister& to ) + static __emitinline void EmitSet( JccComparisonType cc, const xRegister& to ) { emit_base( cc ); ModRM_Direct( 0, to.Id ); @@ -236,7 +236,7 @@ public: static __emitinline void EmitSet( JccComparisonType cc, const void* src ) { emit_base( cc ); - iWriteDisp( 0, src ); + xWriteDisp( 0, src ); } // This form is provided for SETcc only (not available in CMOV) @@ -258,13 +258,13 @@ protected: typedef CMovSetImpl m_16; // 0x40 is the cmov base instruction id public: - __forceinline void operator()( JccComparisonType ccType, const iRegister32& to, const iRegister32& from ) const { m_32::Emit( ccType, to, from ); } - __forceinline void operator()( JccComparisonType ccType, const iRegister32& to, const void* src ) const { m_32::Emit( ccType, to, src ); } - __noinline void operator()( JccComparisonType ccType, const iRegister32& to, const ModSibBase& sibsrc ) const { m_32::Emit( ccType, to, sibsrc ); } + __forceinline void operator()( JccComparisonType ccType, const xRegister32& to, const xRegister32& from ) const { m_32::Emit( ccType, to, from ); } + __forceinline void operator()( JccComparisonType ccType, const xRegister32& to, const void* src ) const { m_32::Emit( ccType, to, src ); } + __noinline void operator()( JccComparisonType ccType, const xRegister32& to, const ModSibBase& sibsrc ) const { m_32::Emit( ccType, to, sibsrc ); } - __forceinline void operator()( JccComparisonType ccType, const iRegister16& to, const iRegister16& from ) const { m_16::Emit( ccType, to, from ); } - __forceinline void operator()( JccComparisonType ccType, const iRegister16& to, const void* src ) const { m_16::Emit( ccType, to, src ); } - __noinline void operator()( JccComparisonType ccType, const iRegister16& to, const ModSibBase& sibsrc ) const { m_16::Emit( ccType, to, sibsrc ); } + __forceinline void operator()( JccComparisonType ccType, const xRegister16& to, const xRegister16& from ) const { m_16::Emit( ccType, to, from ); } + __forceinline void operator()( JccComparisonType ccType, const xRegister16& to, const void* src ) const { m_16::Emit( ccType, to, src ); } + __noinline void operator()( JccComparisonType ccType, const xRegister16& to, const ModSibBase& sibsrc ) const { m_16::Emit( ccType, to, sibsrc ); } CMovImplGeneric() {} // don't ask. }; @@ -278,13 +278,13 @@ protected: typedef CMovSetImpl m_16; public: - __forceinline void operator()( const iRegister32& to, const iRegister32& from ) const { m_32::Emit( ccType, to, from ); } - __forceinline void operator()( const iRegister32& to, const void* src ) const { m_32::Emit( ccType, to, src ); } - __noinline void operator()( const iRegister32& to, const ModSibBase& sibsrc ) const { m_32::Emit( ccType, to, sibsrc ); } + __forceinline void operator()( const xRegister32& to, const xRegister32& from ) const { m_32::Emit( ccType, to, from ); } + __forceinline void operator()( const xRegister32& to, const void* src ) const { m_32::Emit( ccType, to, src ); } + __noinline void operator()( const xRegister32& to, const ModSibBase& sibsrc ) const { m_32::Emit( ccType, to, sibsrc ); } - __forceinline void operator()( const iRegister16& to, const iRegister16& from ) const { m_16::Emit( ccType, to, from ); } - __forceinline void operator()( const iRegister16& to, const void* src ) const { m_16::Emit( ccType, to, src ); } - __noinline void operator()( const iRegister16& to, const ModSibBase& sibsrc ) const { m_16::Emit( ccType, to, sibsrc ); } + __forceinline void operator()( const xRegister16& to, const xRegister16& from ) const { m_16::Emit( ccType, to, from ); } + __forceinline void operator()( const xRegister16& to, const void* src ) const { m_16::Emit( ccType, to, src ); } + __noinline void operator()( const xRegister16& to, const ModSibBase& sibsrc ) const { m_16::Emit( ccType, to, sibsrc ); } CMovImplAll() {} // don't ask. }; @@ -296,7 +296,7 @@ protected: typedef CMovSetImpl Impl; // 0x90 is the SETcc base instruction id public: - __forceinline void operator()( JccComparisonType cc, const iRegister8& to ) const { Impl::EmitSet( cc, to ); } + __forceinline void operator()( JccComparisonType cc, const xRegister8& to ) const { Impl::EmitSet( cc, to ); } __forceinline void operator()( JccComparisonType cc, void* dest ) const { Impl::EmitSet( cc, dest ); } __noinline void operator()( JccComparisonType cc, const ModSibStrict& dest ) const { Impl::EmitSet( cc, dest ); } @@ -311,7 +311,7 @@ protected: typedef CMovSetImpl Impl; // 0x90 is the SETcc base instruction id public: - __forceinline void operator()( const iRegister8& to ) const { Impl::EmitSet( ccType, to ); } + __forceinline void operator()( const xRegister8& to ) const { Impl::EmitSet( ccType, to ); } __forceinline void operator()( void* dest ) const { Impl::EmitSet( ccType, dest ); } __noinline void operator()( const ModSibStrict& dest ) const { Impl::EmitSet( ccType, dest ); } @@ -330,24 +330,24 @@ protected: static const uint SrcOperandSize = sizeof( SrcImmType ); static bool Is8BitOperand() { return SrcOperandSize == 1; } - static void prefix16() { if( DestOperandSize == 2 ) iWrite( 0x66 ); } + static void prefix16() { if( DestOperandSize == 2 ) xWrite( 0x66 ); } static __forceinline void emit_base( bool SignExtend ) { prefix16(); - iWrite( 0x0f ); - iWrite( 0xb6 | (Is8BitOperand() ? 0 : 1) | (SignExtend ? 8 : 0 ) ); + xWrite( 0x0f ); + xWrite( 0xb6 | (Is8BitOperand() ? 0 : 1) | (SignExtend ? 8 : 0 ) ); } public: MovExtendImpl() {} // For the love of GCC. - static __emitinline void Emit( const iRegister& to, const iRegister& from, bool SignExtend ) + static __emitinline void Emit( const xRegister& to, const xRegister& from, bool SignExtend ) { emit_base( SignExtend ); ModRM_Direct( to.Id, from.Id ); } - static __emitinline void Emit( const iRegister& to, const ModSibStrict& sibsrc, bool SignExtend ) + static __emitinline void Emit( const xRegister& to, const ModSibStrict& sibsrc, bool SignExtend ) { emit_base( SignExtend ); EmitSibMagic( to.Id, sibsrc ); @@ -364,14 +364,14 @@ protected: typedef MovExtendImpl m_8to16; public: - __forceinline void operator()( const iRegister32& to, const iRegister16& from ) const { m_16to32::Emit( to, from, SignExtend ); } - __noinline void operator()( const iRegister32& to, const ModSibStrict& sibsrc ) const { m_16to32::Emit( to, sibsrc, SignExtend ); } + __forceinline void operator()( const xRegister32& to, const xRegister16& from ) const { m_16to32::Emit( to, from, SignExtend ); } + __noinline void operator()( const xRegister32& to, const ModSibStrict& sibsrc ) const { m_16to32::Emit( to, sibsrc, SignExtend ); } - __forceinline void operator()( const iRegister32& to, const iRegister8& from ) const { m_8to32::Emit( to, from, SignExtend ); } - __noinline void operator()( const iRegister32& to, const ModSibStrict& sibsrc ) const { m_8to32::Emit( to, sibsrc, SignExtend ); } + __forceinline void operator()( const xRegister32& to, const xRegister8& from ) const { m_8to32::Emit( to, from, SignExtend ); } + __noinline void operator()( const xRegister32& to, const ModSibStrict& sibsrc ) const { m_8to32::Emit( to, sibsrc, SignExtend ); } - __forceinline void operator()( const iRegister16& to, const iRegister8& from ) const { m_8to16::Emit( to, from, SignExtend ); } - __noinline void operator()( const iRegister16& to, const ModSibStrict& sibsrc ) const { m_8to16::Emit( to, sibsrc, SignExtend ); } + __forceinline void operator()( const xRegister16& to, const xRegister8& from ) const { m_8to16::Emit( to, from, SignExtend ); } + __noinline void operator()( const xRegister16& to, const ModSibStrict& sibsrc ) const { m_8to16::Emit( to, sibsrc, SignExtend ); } MovExtendImplAll() {} // don't ask. }; diff --git a/pcsx2/x86/ix86/implement/test.h b/pcsx2/x86/ix86/implement/test.h index 55ecdbcaf0..0c66b0203f 100644 --- a/pcsx2/x86/ix86/implement/test.h +++ b/pcsx2/x86/ix86/implement/test.h @@ -27,41 +27,41 @@ class TestImpl protected: static const uint OperandSize = sizeof(ImmType); static bool Is8BitOperand() { return OperandSize == 1; } - static void prefix16() { if( OperandSize == 2 ) iWrite( 0x66 ); } + static void prefix16() { if( OperandSize == 2 ) xWrite( 0x66 ); } public: TestImpl() {} // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, const iRegister& from ) + static __emitinline void Emit( const xRegister& to, const xRegister& from ) { prefix16(); - iWrite( Is8BitOperand() ? 0x84 : 0x85 ); + xWrite( Is8BitOperand() ? 0x84 : 0x85 ); ModRM_Direct( from.Id, to.Id ); } // ------------------------------------------------------------------------ - static __emitinline void Emit( const iRegister& to, ImmType imm ) + static __emitinline void Emit( const xRegister& to, ImmType imm ) { prefix16(); if( to.IsAccumulator() ) - iWrite( Is8BitOperand() ? 0xa8 : 0xa9 ); + xWrite( Is8BitOperand() ? 0xa8 : 0xa9 ); else { - iWrite( Is8BitOperand() ? 0xf6 : 0xf7 ); + xWrite( Is8BitOperand() ? 0xf6 : 0xf7 ); ModRM_Direct( 0, to.Id ); } - iWrite( imm ); + xWrite( imm ); } // ------------------------------------------------------------------------ static __emitinline void Emit( ModSibStrict dest, ImmType imm ) { prefix16(); - iWrite( Is8BitOperand() ? 0xf6 : 0xf7 ); + xWrite( Is8BitOperand() ? 0xf6 : 0xf7 ); EmitSibMagic( 0, dest ); - iWrite( imm ); + xWrite( imm ); } }; @@ -71,12 +71,12 @@ class TestImplAll { public: template< typename T > - __forceinline void operator()( const iRegister& to, const iRegister& from ) const { TestImpl::Emit( to, from ); } + __forceinline void operator()( const xRegister& to, const xRegister& from ) const { TestImpl::Emit( to, from ); } template< typename T > __noinline void operator()( const ModSibStrict& sibdest, T imm ) const { TestImpl::Emit( sibdest, imm ); } template< typename T > - void operator()( const iRegister& to, T imm ) const { TestImpl::Emit( to, imm ); } + void operator()( const xRegister& to, T imm ) const { TestImpl::Emit( to, imm ); } TestImplAll() {} // Why does GCC need these? }; diff --git a/pcsx2/x86/ix86/implement/xmm/movqss.h b/pcsx2/x86/ix86/implement/xmm/movqss.h index 41f2b3071a..99c3cbb912 100644 --- a/pcsx2/x86/ix86/implement/xmm/movqss.h +++ b/pcsx2/x86/ix86/implement/xmm/movqss.h @@ -26,11 +26,11 @@ __emitinline void SimdPrefix( u8 opcode, u8 prefix=0 ) { if( sizeof( T ) == 16 && prefix != 0 ) { - iWrite( 0x0f00 | prefix ); - iWrite( opcode ); + xWrite( 0x0f00 | prefix ); + xWrite( opcode ); } else - iWrite( (opcode<<8) | 0x0f ); + xWrite( (opcode<<8) | 0x0f ); } // ------------------------------------------------------------------------ @@ -40,24 +40,24 @@ __emitinline void SimdPrefix( u8 opcode, u8 prefix=0 ) // instructions violate this "guideline.") // template< typename T, typename T2 > -__emitinline void writeXMMop( u8 prefix, u8 opcode, const iRegister& to, const iRegister& from ) +__emitinline void writeXMMop( u8 prefix, u8 opcode, const xRegister& to, const xRegister& from ) { SimdPrefix( opcode, prefix ); ModRM_Direct( to.Id, from.Id ); } template< typename T > -void writeXMMop( u8 prefix, u8 opcode, const iRegister& reg, const ModSibBase& sib ) +void writeXMMop( u8 prefix, u8 opcode, const xRegister& reg, const ModSibBase& sib ) { SimdPrefix( opcode, prefix ); EmitSibMagic( reg.Id, sib ); } template< typename T > -__emitinline void writeXMMop( u8 prefix, u8 opcode, const iRegister& reg, const void* data ) +__emitinline void writeXMMop( u8 prefix, u8 opcode, const xRegister& reg, const void* data ) { SimdPrefix( opcode, prefix ); - iWriteDisp( reg.Id, data ); + xWriteDisp( reg.Id, data ); } // ------------------------------------------------------------------------ @@ -66,51 +66,74 @@ __emitinline void writeXMMop( u8 prefix, u8 opcode, const iRegister& reg, con // some special forms of sse/xmm mov instructions also use them due to prefixing inconsistencies. // template< typename T, typename T2 > -__emitinline void writeXMMop( u8 opcode, const iRegister& to, const iRegister& from ) +__emitinline void writeXMMop( u8 opcode, const xRegister& to, const xRegister& from ) { SimdPrefix( opcode ); ModRM_Direct( to.Id, from.Id ); } template< typename T > -void writeXMMop( u8 opcode, const iRegister& reg, const ModSibBase& sib ) +void writeXMMop( u8 opcode, const xRegister& reg, const ModSibBase& sib ) { SimdPrefix( opcode ); EmitSibMagic( reg.Id, sib ); } template< typename T > -__emitinline void writeXMMop( u8 opcode, const iRegister& reg, const void* data ) +__emitinline void writeXMMop( u8 opcode, const xRegister& reg, const void* data ) { SimdPrefix( opcode ); - iWriteDisp( reg.Id, data ); + xWriteDisp( reg.Id, data ); } ////////////////////////////////////////////////////////////////////////////////////////// // Moves to/from high/low portions of an xmm register. // These instructions cannot be used in reg/reg form. // -template< u8 Prefix, u8 Opcode > +template< u8 Opcode > class MovhlImplAll { +protected: + template< u8 Prefix > + struct Woot + { + __forceinline void operator()( const xRegisterSSE& to, const void* from ) const { writeXMMop( Prefix, Opcode, to, from ); } + __forceinline void operator()( const void* to, const xRegisterSSE& from ) const { writeXMMop( Prefix, Opcode+1, from, to ); } + __noinline void operator()( const xRegisterSSE& to, const ModSibBase& from ) const { writeXMMop( Prefix, Opcode, to, from ); } + __noinline void operator()( const ModSibBase& to, const xRegisterSSE& from ) const { writeXMMop( Prefix, Opcode+1, from, to ); } + }; + public: - __forceinline void operator()( const iRegisterSSE& to, const void* from ) const { writeXMMop( Prefix, Opcode, to, from ); } - __forceinline void operator()( const void* to, const iRegisterSSE& from ) const { writeXMMop( Prefix, Opcode+1, from, to ); } - __noinline void operator()( const iRegisterSSE& to, const ModSibBase& from ) const { writeXMMop( Prefix, Opcode, to, from ); } - __noinline void operator()( const ModSibBase& to, const iRegisterSSE& from ) const { writeXMMop( Prefix, Opcode+1, from, to ); } + Woot<0x00> PS; + Woot<0x66> PD; MovhlImplAll() {} //GCC. }; +// ------------------------------------------------------------------------ +// RegtoReg forms of MOVHL/MOVLH -- these are the same opcodes as MOVH/MOVL but +// do something kinda different! Fun! +// +template< u8 Opcode > +class MovhlImpl_RtoR +{ +public: + __forceinline void PS( const xRegisterSSE& to, const xRegisterSSE& from ) const { writeXMMop( Opcode, to, from ); } + __forceinline void PD( const xRegisterSSE& to, const xRegisterSSE& from ) const { writeXMMop( 0x66, Opcode, to, from ); } + + MovhlImpl_RtoR() {} //GCC. +}; + +// ------------------------------------------------------------------------ template< u8 Prefix, u8 Opcode, u8 OpcodeAlt > class MovapsImplAll { public: - __forceinline void operator()( const iRegisterSSE& to, const iRegisterSSE& from ) const { if( to != from ) writeXMMop( Prefix, Opcode, to, from ); } - __forceinline void operator()( const iRegisterSSE& to, const void* from ) const { writeXMMop( Prefix, Opcode, to, from ); } - __forceinline void operator()( const void* to, const iRegisterSSE& from ) const { writeXMMop( Prefix, OpcodeAlt, from, to ); } - __noinline void operator()( const iRegisterSSE& to, const ModSibBase& from ) const { writeXMMop( Prefix, Opcode, to, from ); } - __noinline void operator()( const ModSibBase& to, const iRegisterSSE& from ) const { writeXMMop( Prefix, OpcodeAlt, from, to ); } + __forceinline void operator()( const xRegisterSSE& to, const xRegisterSSE& from ) const { if( to != from ) writeXMMop( Prefix, Opcode, to, from ); } + __forceinline void operator()( const xRegisterSSE& to, const void* from ) const { writeXMMop( Prefix, Opcode, to, from ); } + __forceinline void operator()( const void* to, const xRegisterSSE& from ) const { writeXMMop( Prefix, OpcodeAlt, from, to ); } + __noinline void operator()( const xRegisterSSE& to, const ModSibBase& from ) const { writeXMMop( Prefix, Opcode, to, from ); } + __noinline void operator()( const ModSibBase& to, const xRegisterSSE& from ) const { writeXMMop( Prefix, OpcodeAlt, from, to ); } MovapsImplAll() {} //GCC. }; @@ -124,11 +147,11 @@ class PLogicImplAll { public: template< typename T > - __forceinline void operator()( const iRegisterSIMD& to, const iRegisterSIMD& from ) const { writeXMMop( 0x66, Opcode, to, from ); } + __forceinline void operator()( const xRegisterSIMD& to, const xRegisterSIMD& from ) const { writeXMMop( 0x66, Opcode, to, from ); } template< typename T > - __forceinline void operator()( const iRegisterSIMD& to, const void* from ) const { writeXMMop( 0x66, Opcode, to, from ); } + __forceinline void operator()( const xRegisterSIMD& to, const void* from ) const { writeXMMop( 0x66, Opcode, to, from ); } template< typename T > - __noinline void operator()( const iRegisterSIMD& to, const ModSibBase& from ) const { writeXMMop( 0x66, Opcode, to, from ); } + __noinline void operator()( const xRegisterSIMD& to, const ModSibBase& from ) const { writeXMMop( 0x66, Opcode, to, from ); } PLogicImplAll() {} //GCWho? }; @@ -140,47 +163,42 @@ template< u8 Prefix, u8 Opcode > class SSELogicImpl { public: - __forceinline void operator()( const iRegisterSSE& to, const iRegisterSSE& from ) const { writeXMMop( Prefix, Opcode, to, from ); } - __forceinline void operator()( const iRegisterSSE& to, const void* from ) const { writeXMMop( Prefix, Opcode, to, from ); } - __noinline void operator()( const iRegisterSSE& to, const ModSibBase& from ) const { writeXMMop( Prefix, Opcode, to, from ); } + __forceinline void operator()( const xRegisterSSE& to, const xRegisterSSE& from ) const { writeXMMop( Prefix, Opcode, to, from ); } + __forceinline void operator()( const xRegisterSSE& to, const void* from ) const { writeXMMop( Prefix, Opcode, to, from ); } + __noinline void operator()( const xRegisterSSE& to, const ModSibBase& from ) const { writeXMMop( Prefix, Opcode, to, from ); } SSELogicImpl() {} //GCWho? }; +// ------------------------------------------------------------------------ +// +template< u8 OpcodeSSE > +class SSEAndNotImpl +{ +public: + const SSELogicImpl<0x00,OpcodeSSE> PS; + const SSELogicImpl<0x66,OpcodeSSE> PD; + + SSEAndNotImpl() {} +}; // ------------------------------------------------------------------------ -// For implementing SSE-only comparison operations, like CMPEQPS. -// -enum SSE2_ComparisonType -{ - SSE2_Equal = 0, - SSE2_Less, - SSE2_LessOrEqual, - SSE2_Unordered, - SSE2_NotEqual, - SSE2_NotLess, - SSE2_NotLessOrEqual, - SSE2_Ordered -}; - -template< u8 Prefix > -class SSECompareImplGeneric -{ -public: - __forceinline void operator()( const iRegisterSSE& to, const iRegisterSSE& from, u8 cmptype ) const { writeXMMop( Prefix, 0xc2, to, from ); iWrite( cmptype ); } - __forceinline void operator()( const iRegisterSSE& to, const void* from, u8 cmptype ) const { writeXMMop( Prefix, 0xc2, to, from ); iWrite( cmptype ); } - __noinline void operator()( const iRegisterSSE& to, const ModSibBase& from, u8 cmptype ) const { writeXMMop( Prefix, 0xc2, to, from ); iWrite( cmptype ); } - - SSECompareImplGeneric() {} //GCWhat? -}; - -template< u8 Prefix, u8 Opcode, SSE2_ComparisonType CType > +template< SSE2_ComparisonType CType > class SSECompareImpl { +protected: + template< u8 Prefix > struct Woot + { + __forceinline void operator()( const xRegisterSSE& to, const xRegisterSSE& from ) const { writeXMMop( Prefix, 0xc2, to, from ); xWrite( CType ); } + __forceinline void operator()( const xRegisterSSE& to, const void* from ) const { writeXMMop( Prefix, 0xc2, to, from ); xWrite( CType ); } + __noinline void operator()( const xRegisterSSE& to, const ModSibBase& from ) const { writeXMMop( Prefix, 0xc2, to, from ); xWrite( CType ); } + }; + public: - __forceinline void operator()( const iRegisterSSE& to, const iRegisterSSE& from ) const { writeXMMop( Prefix, 0xc2, to, from ); iWrite( CType ); } - __forceinline void operator()( const iRegisterSSE& to, const void* from ) const { writeXMMop( Prefix, 0xc2, to, from ); iWrite( CType ); } - __noinline void operator()( const iRegisterSSE& to, const ModSibBase& from ) const { writeXMMop( Prefix, 0xc2, to, from ); iWrite( CType ); } + Woot<0x00> PS; + Woot<0x66> PD; + Woot<0xf3> SS; + Woot<0xf2> SD; SSECompareImpl() {} //GCWhat? }; diff --git a/pcsx2/x86/ix86/ix86.cpp b/pcsx2/x86/ix86/ix86.cpp index 362d446037..2affc9c74e 100644 --- a/pcsx2/x86/ix86/ix86.cpp +++ b/pcsx2/x86/ix86/ix86.cpp @@ -66,54 +66,54 @@ __threadlocal XMMSSEType g_xmmtypes[iREGCNT_XMM] = { XMMT_INT }; namespace x86Emitter { -const iAddressIndexerBase ptr; -const iAddressIndexer ptr128; -const iAddressIndexer ptr64; -const iAddressIndexer ptr32; -const iAddressIndexer ptr16; -const iAddressIndexer ptr8; +const xAddressIndexerBase ptr; +const xAddressIndexer ptr128; +const xAddressIndexer ptr64; +const xAddressIndexer ptr32; +const xAddressIndexer ptr16; +const xAddressIndexer ptr8; // ------------------------------------------------------------------------ -template< typename OperandType > const iRegister iRegister::Empty; -const iAddressReg iAddressReg::Empty; +template< typename OperandType > const xRegister xRegister::Empty; +const xAddressReg xAddressReg::Empty; -const iRegisterSSE +const xRegisterSSE xmm0( 0 ), xmm1( 1 ), xmm2( 2 ), xmm3( 3 ), xmm4( 4 ), xmm5( 5 ), xmm6( 6 ), xmm7( 7 ); -const iRegisterMMX +const xRegisterMMX mm0( 0 ), mm1( 1 ), mm2( 2 ), mm3( 3 ), mm4( 4 ), mm5( 5 ), mm6( 6 ), mm7( 7 ); -const iRegister32 +const xRegister32 eax( 0 ), ebx( 3 ), ecx( 1 ), edx( 2 ), esi( 6 ), edi( 7 ), ebp( 5 ), esp( 4 ); -const iRegister16 +const xRegister16 ax( 0 ), bx( 3 ), cx( 1 ), dx( 2 ), si( 6 ), di( 7 ), bp( 5 ), sp( 4 ); -const iRegister8 +const xRegister8 al( 0 ), dl( 2 ), bl( 3 ), ah( 4 ), ch( 5 ), dh( 6 ), bh( 7 ); -const iRegisterCL cl; +const xRegisterCL cl; namespace Internal { // Performance note: VC++ wants to use byte/word register form for the following - // ModRM/SibSB constructors when we use iWrite, and furthermore unrolls the + // ModRM/SibSB constructors when we use xWrite, and furthermore unrolls the // the shift using a series of ADDs for the following results: // add cl,cl // add cl,cl @@ -137,7 +137,7 @@ namespace Internal __forceinline void ModRM( uint mod, uint reg, uint rm ) { - iWrite( (mod << 6) | (reg << 3) | rm ); + xWrite( (mod << 6) | (reg << 3) | rm ); //*(u32*)x86Ptr = (mod << 6) | (reg << 3) | rm; //x86Ptr++; } @@ -149,20 +149,20 @@ namespace Internal __forceinline void SibSB( u32 ss, u32 index, u32 base ) { - iWrite( (ss << 6) | (index << 3) | base ); + xWrite( (ss << 6) | (index << 3) | base ); //*(u32*)x86Ptr = (ss << 6) | (index << 3) | base; //x86Ptr++; } - __forceinline void iWriteDisp( int regfield, s32 displacement ) + __forceinline void xWriteDisp( int regfield, s32 displacement ) { ModRM( 0, regfield, ModRm_UseDisp32 ); - iWrite( displacement ); + xWrite( displacement ); } - __forceinline void iWriteDisp( int regfield, const void* address ) + __forceinline void xWriteDisp( int regfield, const void* address ) { - iWriteDisp( regfield, (s32)address ); + xWriteDisp( regfield, (s32)address ); } // ------------------------------------------------------------------------ @@ -206,7 +206,7 @@ namespace Internal if( info.Index.IsEmpty() ) { - iWriteDisp( regfield, info.Displacement ); + xWriteDisp( regfield, info.Displacement ); return; } else @@ -229,7 +229,7 @@ namespace Internal { ModRM( 0, regfield, ModRm_UseSib ); SibSB( info.Scale, info.Index.Id, ModRm_UseDisp32 ); - iWrite( info.Displacement ); + xWrite( info.Displacement ); return; } else @@ -245,116 +245,116 @@ namespace Internal if( displacement_size != 0 ) { if( displacement_size == 1 ) - iWrite( info.Displacement ); + xWrite( info.Displacement ); else - iWrite( info.Displacement ); + xWrite( info.Displacement ); } } } using namespace Internal; -const MovImplAll iMOV; -const TestImplAll iTEST; +const MovImplAll xMOV; +const TestImplAll xTEST; -const G1LogicImpl iAND; -const G1LogicImpl iOR; -const G1LogicImpl iXOR; +const G1LogicImpl_PlusSSE xAND; +const G1LogicImpl_PlusSSE xOR; +const G1LogicImpl_PlusSSE xXOR; -const G1ArithmeticImpl iADD; -const G1ArithmeticImpl iSUB; +const G1ArithmeticImpl_PlusSSE xADD; +const G1ArithmeticImpl_PlusSSE xSUB; -const Group1ImplAll iADC; -const Group1ImplAll iSBB; -const Group1ImplAll iCMP; +const Group1ImplAll xADC; +const Group1ImplAll xSBB; +const G1CompareImpl_PlusSSE xCMP; -const Group2ImplAll iROL; -const Group2ImplAll iROR; -const Group2ImplAll iRCL; -const Group2ImplAll iRCR; -const Group2ImplAll iSHL; -const Group2ImplAll iSHR; -const Group2ImplAll iSAR; +const Group2ImplAll xROL; +const Group2ImplAll xROR; +const Group2ImplAll xRCL; +const Group2ImplAll xRCR; +const Group2ImplAll xSHL; +const Group2ImplAll xSHR; +const Group2ImplAll xSAR; -const Group3ImplAll iNOT; -const Group3ImplAll iNEG; -const Group3ImplAll iUMUL; -const Group3ImplAll iUDIV; -const G3Impl_PlusSSE iDIV; -const iMul_PlusSSE iMUL; +const Group3ImplAll xNOT; +const Group3ImplAll xNEG; +const Group3ImplAll xUMUL; +const Group3ImplAll xUDIV; +const G3Impl_PlusSSE xDIV; +const iMul_PlusSSE xMUL; -const IncDecImplAll iINC; -const IncDecImplAll iDEC; +const IncDecImplAll xINC; +const IncDecImplAll xDEC; -const MovExtendImplAll iMOVZX; -const MovExtendImplAll iMOVSX; +const MovExtendImplAll xMOVZX; +const MovExtendImplAll xMOVSX; -const DwordShiftImplAll iSHLD; -const DwordShiftImplAll iSHRD; +const DwordShiftImplAll xSHLD; +const DwordShiftImplAll xSHRD; -const Group8ImplAll iBT; -const Group8ImplAll iBTR; -const Group8ImplAll iBTS; -const Group8ImplAll iBTC; +const Group8ImplAll xBT; +const Group8ImplAll xBTR; +const Group8ImplAll xBTS; +const Group8ImplAll xBTC; -const BitScanImplAll iBSF; -const BitScanImplAll iBSR; +const BitScanImplAll xBSF; +const BitScanImplAll xBSR; // ------------------------------------------------------------------------ -const CMovImplGeneric iCMOV; +const CMovImplGeneric xCMOV; -const CMovImplAll iCMOVA; -const CMovImplAll iCMOVAE; -const CMovImplAll iCMOVB; -const CMovImplAll iCMOVBE; +const CMovImplAll xCMOVA; +const CMovImplAll xCMOVAE; +const CMovImplAll xCMOVB; +const CMovImplAll xCMOVBE; -const CMovImplAll iCMOVG; -const CMovImplAll iCMOVGE; -const CMovImplAll iCMOVL; -const CMovImplAll iCMOVLE; +const CMovImplAll xCMOVG; +const CMovImplAll xCMOVGE; +const CMovImplAll xCMOVL; +const CMovImplAll xCMOVLE; -const CMovImplAll iCMOVZ; -const CMovImplAll iCMOVE; -const CMovImplAll iCMOVNZ; -const CMovImplAll iCMOVNE; +const CMovImplAll xCMOVZ; +const CMovImplAll xCMOVE; +const CMovImplAll xCMOVNZ; +const CMovImplAll xCMOVNE; -const CMovImplAll iCMOVO; -const CMovImplAll iCMOVNO; -const CMovImplAll iCMOVC; -const CMovImplAll iCMOVNC; +const CMovImplAll xCMOVO; +const CMovImplAll xCMOVNO; +const CMovImplAll xCMOVC; +const CMovImplAll xCMOVNC; -const CMovImplAll iCMOVS; -const CMovImplAll iCMOVNS; -const CMovImplAll iCMOVPE; -const CMovImplAll iCMOVPO; +const CMovImplAll xCMOVS; +const CMovImplAll xCMOVNS; +const CMovImplAll xCMOVPE; +const CMovImplAll xCMOVPO; // ------------------------------------------------------------------------ -const SetImplGeneric iSET; +const SetImplGeneric xSET; -const SetImplAll iSETA; -const SetImplAll iSETAE; -const SetImplAll iSETB; -const SetImplAll iSETBE; +const SetImplAll xSETA; +const SetImplAll xSETAE; +const SetImplAll xSETB; +const SetImplAll xSETBE; -const SetImplAll iSETG; -const SetImplAll iSETGE; -const SetImplAll iSETL; -const SetImplAll iSETLE; +const SetImplAll xSETG; +const SetImplAll xSETGE; +const SetImplAll xSETL; +const SetImplAll xSETLE; -const SetImplAll iSETZ; -const SetImplAll iSETE; -const SetImplAll iSETNZ; -const SetImplAll iSETNE; +const SetImplAll xSETZ; +const SetImplAll xSETE; +const SetImplAll xSETNZ; +const SetImplAll xSETNE; -const SetImplAll iSETO; -const SetImplAll iSETNO; -const SetImplAll iSETC; -const SetImplAll iSETNC; +const SetImplAll xSETO; +const SetImplAll xSETNO; +const SetImplAll xSETC; +const SetImplAll xSETNC; -const SetImplAll iSETS; -const SetImplAll iSETNS; -const SetImplAll iSETPE; -const SetImplAll iSETPO; +const SetImplAll xSETS; +const SetImplAll xSETNS; +const SetImplAll xSETPE; +const SetImplAll xSETPO; // ------------------------------------------------------------------------ @@ -389,7 +389,7 @@ __emitinline void iAdvancePtr( uint bytes ) { // common debugger courtesy: advance with INT3 as filler. for( uint i=0; i( 0xcc ); + xWrite( 0xcc ); } else x86Ptr += bytes; @@ -430,7 +430,7 @@ void ModSibBase::Reduce() Index = Base; Scale = 0; if( !Base.IsStackPointer() ) // prevent ESP from being encoded 'alone' - Base = iAddressReg::Empty; + Base = xAddressReg::Empty; return; } @@ -484,9 +484,9 @@ void ModSibBase::Reduce() // of LEA, which alters flags states. // template< typename OperandType > -static void EmitLeaMagic( iRegister to, const ModSibBase& src, bool preserve_flags ) +static void EmitLeaMagic( xRegister to, const ModSibBase& src, bool preserve_flags ) { - typedef iRegister ToReg; + typedef xRegister ToReg; int displacement_size = (src.Displacement == 0) ? 0 : ( ( src.IsByteSizeDisp() ) ? 1 : 2 ); @@ -501,12 +501,12 @@ static void EmitLeaMagic( iRegister to, const ModSibBase& src, bool if( src.Index.IsEmpty() ) { - iMOV( to, src.Displacement ); + xMOV( to, src.Displacement ); return; } else if( displacement_size == 0 ) { - iMOV( to, ToReg( src.Index.Id ) ); + xMOV( to, ToReg( src.Index.Id ) ); return; } else @@ -516,8 +516,8 @@ static void EmitLeaMagic( iRegister to, const ModSibBase& src, bool // encode as MOV and ADD combo. Make sure to use the immediate on the // ADD since it can encode as an 8-bit sign-extended value. - iMOV( to, ToReg( src.Index.Id ) ); - iADD( to, src.Displacement ); + xMOV( to, ToReg( src.Index.Id ) ); + xADD( to, src.Displacement ); return; } else @@ -525,7 +525,7 @@ static void EmitLeaMagic( iRegister to, const ModSibBase& src, bool // note: no need to do ebp+0 check since we encode all 0 displacements as // register assignments above (via MOV) - iWrite( 0x8d ); + xWrite( 0x8d ); ModRM( displacement_size, to.Id, src.Index.Id ); } } @@ -543,14 +543,14 @@ static void EmitLeaMagic( iRegister to, const ModSibBase& src, bool // (this does not apply to older model P4s with the broken barrel shifter, // but we currently aren't optimizing for that target anyway). - iMOV( to, ToReg( src.Index.Id ) ); - iSHL( to, src.Scale ); + xMOV( to, ToReg( src.Index.Id ) ); + xSHL( to, src.Scale ); return; } - iWrite( 0x8d ); + xWrite( 0x8d ); ModRM( 0, to.Id, ModRm_UseSib ); SibSB( src.Scale, src.Index.Id, ModRm_UseDisp32 ); - iWrite( src.Displacement ); + xWrite( src.Displacement ); return; } else @@ -562,14 +562,14 @@ static void EmitLeaMagic( iRegister to, const ModSibBase& src, bool if( src.Index == esp ) { // ESP is not encodable as an index (ix86 ignores it), thus: - iMOV( to, ToReg( src.Base.Id ) ); // will do the trick! - if( src.Displacement ) iADD( to, src.Displacement ); + xMOV( to, ToReg( src.Base.Id ) ); // will do the trick! + if( src.Displacement ) xADD( to, src.Displacement ); return; } else if( src.Displacement == 0 ) { - iMOV( to, ToReg( src.Base.Id ) ); - iADD( to, ToReg( src.Index.Id ) ); + xMOV( to, ToReg( src.Base.Id ) ); + xADD( to, ToReg( src.Index.Id ) ); return; } } @@ -578,7 +578,7 @@ static void EmitLeaMagic( iRegister to, const ModSibBase& src, bool // special case handling of ESP as Index, which is replaceable with // a single MOV even when preserve_flags is set! :D - iMOV( to, ToReg( src.Base.Id ) ); + xMOV( to, ToReg( src.Base.Id ) ); return; } } @@ -586,7 +586,7 @@ static void EmitLeaMagic( iRegister to, const ModSibBase& src, bool if( src.Base == ebp && displacement_size == 0 ) displacement_size = 1; // forces [ebp] to be encoded as [ebp+0]! - iWrite( 0x8d ); + xWrite( 0x8d ); ModRM( displacement_size, to.Id, ModRm_UseSib ); SibSB( src.Scale, src.Index.Id, src.Base.Id ); } @@ -595,19 +595,19 @@ static void EmitLeaMagic( iRegister to, const ModSibBase& src, bool if( displacement_size != 0 ) { if( displacement_size == 1 ) - iWrite( src.Displacement ); + xWrite( src.Displacement ); else - iWrite( src.Displacement ); + xWrite( src.Displacement ); } } -__emitinline void iLEA( iRegister32 to, const ModSibBase& src, bool preserve_flags ) +__emitinline void xLEA( xRegister32 to, const ModSibBase& src, bool preserve_flags ) { EmitLeaMagic( to, src, preserve_flags ); } -__emitinline void iLEA( iRegister16 to, const ModSibBase& src, bool preserve_flags ) +__emitinline void xLEA( xRegister16 to, const ModSibBase& src, bool preserve_flags ) { write8( 0x66 ); EmitLeaMagic( to, src, preserve_flags ); @@ -620,21 +620,21 @@ __emitinline void iLEA( iRegister16 to, const ModSibBase& src, bool preserve_fla // Note: pushad/popad implementations are intentionally left out. The instructions are // invalid in x64, and are super slow on x32. Use multiple Push/Pop instructions instead. -__emitinline void iPOP( const ModSibBase& from ) +__emitinline void xPOP( const ModSibBase& from ) { - iWrite( 0x8f ); + xWrite( 0x8f ); EmitSibMagic( 0, from ); } -__emitinline void iPUSH( const ModSibBase& from ) +__emitinline void xPUSH( const ModSibBase& from ) { - iWrite( 0xff ); + xWrite( 0xff ); EmitSibMagic( 6, from ); } ////////////////////////////////////////////////////////////////////////////////////////// // -__emitinline void iBSWAP( const iRegister32& to ) +__emitinline void xBSWAP( const xRegister32& to ) { write8( 0x0F ); write8( 0xC8 | to.Id ); @@ -645,66 +645,81 @@ __emitinline void iBSWAP( const iRegister32& to ) // MMX / XMM Instructions // (these will get put in their own file later) -const MovapsImplAll< 0, 0x28, 0x29 > iMOVAPS; -const MovapsImplAll< 0, 0x10, 0x11 > iMOVUPS; -const MovapsImplAll< 0x66, 0x28, 0x29 > iMOVAPD; -const MovapsImplAll< 0x66, 0x10, 0x11 > iMOVUPD; +const MovapsImplAll< 0, 0x28, 0x29 > xMOVAPS; +const MovapsImplAll< 0, 0x10, 0x11 > xMOVUPS; +const MovapsImplAll< 0x66, 0x28, 0x29 > xMOVAPD; +const MovapsImplAll< 0x66, 0x10, 0x11 > xMOVUPD; #ifdef ALWAYS_USE_MOVAPS -const MovapsImplAll< 0x66, 0x6f, 0x7f > iMOVDQA; -const MovapsImplAll< 0xf3, 0x6f, 0x7f > iMOVDQU; +const MovapsImplAll< 0x66, 0x6f, 0x7f > xMOVDQA; +const MovapsImplAll< 0xf3, 0x6f, 0x7f > xMOVDQU; #else -const MovapsImplAll< 0, 0x28, 0x29 > iMOVDQA; -const MovapsImplAll< 0, 0x10, 0x11 > iMOVDQU; +const MovapsImplAll< 0, 0x28, 0x29 > xMOVDQA; +const MovapsImplAll< 0, 0x10, 0x11 > xMOVDQU; #endif -const MovhlImplAll< 0, 0x16 > iMOVHPS; -const MovhlImplAll< 0, 0x12 > iMOVLPS; -const MovhlImplAll< 0x66, 0x16 > iMOVHPD; -const MovhlImplAll< 0x66, 0x12 > iMOVLPD; +const MovhlImplAll<0x16> xMOVH; +const MovhlImplAll<0x12> xMOVL; +const MovhlImpl_RtoR<0x16> xMOVLH; +const MovhlImpl_RtoR<0x12> xMOVHL; -const PLogicImplAll<0xdb> iPAND; -const PLogicImplAll<0xdf> iPANDN; -const PLogicImplAll<0xeb> iPOR; -const PLogicImplAll<0xef> iPXOR; +const PLogicImplAll<0xdb> xPAND; +const PLogicImplAll<0xdf> xPANDN; +const PLogicImplAll<0xeb> xPOR; +const PLogicImplAll<0xef> xPXOR; -const SSEAndNotImpl<0x55> iANDN; +const SSEAndNotImpl<0x55> xANDN; // Compute Reciprocal Packed Single-Precision Floating-Point Values -const SSELogicImpl<0,0x53> iRCPPS; +const SSELogicImpl<0,0x53> xRCPPS; // Compute Reciprocal of Scalar Single-Precision Floating-Point Value -const SSELogicImpl<0xf3,0x53> iRCPSS; +const SSELogicImpl<0xf3,0x53> xRCPSS; + +// ------------------------------------------------------------------------ + +const SSECompareImpl xCMPEQ; +const SSECompareImpl xCMPLT; +const SSECompareImpl xCMPLE; +const SSECompareImpl xCMPUNORD; +const SSECompareImpl xCMPNE; +const SSECompareImpl xCMPNLT; +const SSECompareImpl xCMPNLE; +const SSECompareImpl xCMPORD; + + +////////////////////////////////////////////////////////////////////////////////////////// +// // Moves from XMM to XMM, with the *upper 64 bits* of the destination register // being cleared to zero. -__forceinline void iMOVQZX( const iRegisterSSE& to, const iRegisterSSE& from ) { writeXMMop( 0xf3, 0x7e, to, from ); } +__forceinline void xMOVQZX( const xRegisterSSE& to, const xRegisterSSE& from ) { writeXMMop( 0xf3, 0x7e, to, from ); } // Moves from XMM to XMM, with the *upper 64 bits* of the destination register // being cleared to zero. -__forceinline void iMOVQZX( const iRegisterSSE& to, const ModSibBase& src ) { writeXMMop( 0xf3, 0x7e, to, src ); } +__forceinline void xMOVQZX( const xRegisterSSE& to, const ModSibBase& src ) { writeXMMop( 0xf3, 0x7e, to, src ); } // Moves from XMM to XMM, with the *upper 64 bits* of the destination register // being cleared to zero. -__forceinline void iMOVQZX( const iRegisterSSE& to, const void* src ) { writeXMMop( 0xf3, 0x7e, to, src ); } +__forceinline void xMOVQZX( const xRegisterSSE& to, const void* src ) { writeXMMop( 0xf3, 0x7e, to, src ); } // Moves lower quad of XMM to ptr64 (no bits are cleared) -__forceinline void iMOVQ( const ModSibBase& dest, const iRegisterSSE& from ) { writeXMMop( 0x66, 0xd6, from, dest ); } +__forceinline void xMOVQ( const ModSibBase& dest, const xRegisterSSE& from ) { writeXMMop( 0x66, 0xd6, from, dest ); } // Moves lower quad of XMM to ptr64 (no bits are cleared) -__forceinline void iMOVQ( void* dest, const iRegisterSSE& from ) { writeXMMop( 0x66, 0xd6, from, dest ); } +__forceinline void xMOVQ( void* dest, const xRegisterSSE& from ) { writeXMMop( 0x66, 0xd6, from, dest ); } -__forceinline void iMOVQ( const iRegisterMMX& to, const iRegisterMMX& from ) { if( to != from ) writeXMMop( 0x6f, to, from ); } -__forceinline void iMOVQ( const iRegisterMMX& to, const ModSibBase& src ) { writeXMMop( 0x6f, to, src ); } -__forceinline void iMOVQ( const iRegisterMMX& to, const void* src ) { writeXMMop( 0x6f, to, src ); } -__forceinline void iMOVQ( const ModSibBase& dest, const iRegisterMMX& from ) { writeXMMop( 0x7f, from, dest ); } -__forceinline void iMOVQ( void* dest, const iRegisterMMX& from ) { writeXMMop( 0x7f, from, dest ); } +__forceinline void xMOVQ( const xRegisterMMX& to, const xRegisterMMX& from ) { if( to != from ) writeXMMop( 0x6f, to, from ); } +__forceinline void xMOVQ( const xRegisterMMX& to, const ModSibBase& src ) { writeXMMop( 0x6f, to, src ); } +__forceinline void xMOVQ( const xRegisterMMX& to, const void* src ) { writeXMMop( 0x6f, to, src ); } +__forceinline void xMOVQ( const ModSibBase& dest, const xRegisterMMX& from ) { writeXMMop( 0x7f, from, dest ); } +__forceinline void xMOVQ( void* dest, const xRegisterMMX& from ) { writeXMMop( 0x7f, from, dest ); } -// This form of iMOVQ is Intel's adeptly named 'MOVQ2DQ' -__forceinline void iMOVQ( const iRegisterSSE& to, const iRegisterMMX& from ) { writeXMMop( 0xf3, 0xd6, to, from ); } +// This form of xMOVQ is Intel's adeptly named 'MOVQ2DQ' +__forceinline void xMOVQ( const xRegisterSSE& to, const xRegisterMMX& from ) { writeXMMop( 0xf3, 0xd6, to, from ); } -// This form of iMOVQ is Intel's adeptly named 'MOVDQ2Q' -__forceinline void iMOVQ( const iRegisterMMX& to, const iRegisterSSE& from ) +// This form of xMOVQ is Intel's adeptly named 'MOVDQ2Q' +__forceinline void xMOVQ( const xRegisterMMX& to, const xRegisterSSE& from ) { // Manual implementation of this form of MOVQ, since its parameters are unique in a way // that breaks the template inference of writeXMMop(); @@ -716,53 +731,42 @@ __forceinline void iMOVQ( const iRegisterMMX& to, const iRegisterSSE& from ) ////////////////////////////////////////////////////////////////////////////////////////// // -#define IMPLEMENT_iMOVS( ssd, prefix ) \ - __forceinline void iMOV##ssd( const iRegisterSSE& to, const iRegisterSSE& from ) { if( to != from ) writeXMMop( prefix, 0x10, to, from ); } \ - __forceinline void iMOV##ssd##ZX( const iRegisterSSE& to, const void* from ) { writeXMMop( prefix, 0x10, to, from ); } \ - __forceinline void iMOV##ssd##ZX( const iRegisterSSE& to, const ModSibBase& from ) { writeXMMop( prefix, 0x10, to, from ); } \ - __forceinline void iMOV##ssd( const void* to, const iRegisterSSE& from ) { writeXMMop( prefix, 0x11, from, to ); } \ - __forceinline void iMOV##ssd( const ModSibBase& to, const iRegisterSSE& from ) { writeXMMop( prefix, 0x11, from, to ); } +#define IMPLEMENT_xMOVS( ssd, prefix ) \ + __forceinline void xMOV##ssd( const xRegisterSSE& to, const xRegisterSSE& from ) { if( to != from ) writeXMMop( prefix, 0x10, to, from ); } \ + __forceinline void xMOV##ssd##ZX( const xRegisterSSE& to, const void* from ) { writeXMMop( prefix, 0x10, to, from ); } \ + __forceinline void xMOV##ssd##ZX( const xRegisterSSE& to, const ModSibBase& from ) { writeXMMop( prefix, 0x10, to, from ); } \ + __forceinline void xMOV##ssd( const void* to, const xRegisterSSE& from ) { writeXMMop( prefix, 0x11, from, to ); } \ + __forceinline void xMOV##ssd( const ModSibBase& to, const xRegisterSSE& from ) { writeXMMop( prefix, 0x11, from, to ); } -IMPLEMENT_iMOVS( SS, 0xf3 ) -IMPLEMENT_iMOVS( SD, 0xf2 ) +IMPLEMENT_xMOVS( SS, 0xf3 ) +IMPLEMENT_xMOVS( SD, 0xf2 ) ////////////////////////////////////////////////////////////////////////////////////////// // Non-temporal movs only support a register as a target (ie, load form only, no stores) // -__forceinline void iMOVNTDQA( const iRegisterSSE& to, const void* from ) +__forceinline void xMOVNTDQA( const xRegisterSSE& to, const void* from ) { - iWrite( 0x2A380f66 ); - iWriteDisp( to.Id, from ); + xWrite( 0x2A380f66 ); + xWriteDisp( to.Id, from ); } -__noinline void iMOVNTDQA( const iRegisterSSE& to, const ModSibBase& from ) +__noinline void xMOVNTDQA( const xRegisterSSE& to, const ModSibBase& from ) { - iWrite( 0x2A380f66 ); + xWrite( 0x2A380f66 ); EmitSibMagic( to.Id, from ); } -__forceinline void iMOVNTDQ( void* to, const iRegisterSSE& from ) { writeXMMop( 0x66, 0xe7, from, to ); } -__noinline void iMOVNTDQA( const ModSibBase& to, const iRegisterSSE& from ) { writeXMMop( 0x66, 0xe7, from, to ); } +__forceinline void xMOVNTDQ( void* to, const xRegisterSSE& from ) { writeXMMop( 0x66, 0xe7, from, to ); } +__noinline void xMOVNTDQA( const ModSibBase& to, const xRegisterSSE& from ) { writeXMMop( 0x66, 0xe7, from, to ); } -__forceinline void iMOVNTPD( void* to, const iRegisterSSE& from ) { writeXMMop( 0x66, 0x2b, from, to ); } -__noinline void iMOVNTPD( const ModSibBase& to, const iRegisterSSE& from ) { writeXMMop( 0x66, 0x2b, from, to ); } -__forceinline void iMOVNTPS( void* to, const iRegisterSSE& from ) { writeXMMop( 0x2b, from, to ); } -__noinline void iMOVNTPS( const ModSibBase& to, const iRegisterSSE& from ) { writeXMMop( 0x2b, from, to ); } +__forceinline void xMOVNTPD( void* to, const xRegisterSSE& from ) { writeXMMop( 0x66, 0x2b, from, to ); } +__noinline void xMOVNTPD( const ModSibBase& to, const xRegisterSSE& from ) { writeXMMop( 0x66, 0x2b, from, to ); } +__forceinline void xMOVNTPS( void* to, const xRegisterSSE& from ) { writeXMMop( 0x2b, from, to ); } +__noinline void xMOVNTPS( const ModSibBase& to, const xRegisterSSE& from ) { writeXMMop( 0x2b, from, to ); } -__forceinline void iMOVNTQ( void* to, const iRegisterMMX& from ) { writeXMMop( 0xe7, from, to ); } -__noinline void iMOVNTQ( const ModSibBase& to, const iRegisterMMX& from ) { writeXMMop( 0xe7, from, to ); } - -////////////////////////////////////////////////////////////////////////////////////////// -// Mov Low to High / High to Low -// -// These instructions come in xmmreg,xmmreg forms only! -// - -__forceinline void iMOVLHPS( const iRegisterSSE& to, const iRegisterSSE& from ) { writeXMMop( 0x16, to, from ); } -__forceinline void iMOVHLPS( const iRegisterSSE& to, const iRegisterSSE& from ) { writeXMMop( 0x12, to, from ); } -__forceinline void iMOVLHPD( const iRegisterSSE& to, const iRegisterSSE& from ) { writeXMMop( 0x66, 0x16, to, from ); } -__forceinline void iMOVHLPD( const iRegisterSSE& to, const iRegisterSSE& from ) { writeXMMop( 0x66, 0x12, to, from ); } +__forceinline void xMOVNTQ( void* to, const xRegisterMMX& from ) { writeXMMop( 0xe7, from, to ); } +__noinline void xMOVNTQ( const ModSibBase& to, const xRegisterMMX& from ) { writeXMMop( 0xe7, from, to ); } } diff --git a/pcsx2/x86/ix86/ix86_inlines.inl b/pcsx2/x86/ix86/ix86_inlines.inl index c9af4a8e04..c2b54cfcb0 100644 --- a/pcsx2/x86/ix86/ix86_inlines.inl +++ b/pcsx2/x86/ix86/ix86_inlines.inl @@ -53,29 +53,29 @@ namespace x86Emitter ////////////////////////////////////////////////////////////////////////////////////////// // x86Register Method Implementations // - __forceinline iAddressInfo iAddressReg::operator+( const iAddressReg& right ) const + __forceinline xAddressInfo xAddressReg::operator+( const xAddressReg& right ) const { - return iAddressInfo( *this, right ); + return xAddressInfo( *this, right ); } - __forceinline iAddressInfo iAddressReg::operator+( const iAddressInfo& right ) const + __forceinline xAddressInfo xAddressReg::operator+( const xAddressInfo& right ) const { return right + *this; } - __forceinline iAddressInfo iAddressReg::operator+( s32 right ) const + __forceinline xAddressInfo xAddressReg::operator+( s32 right ) const { - return iAddressInfo( *this, right ); + return xAddressInfo( *this, right ); } - __forceinline iAddressInfo iAddressReg::operator*( u32 right ) const + __forceinline xAddressInfo xAddressReg::operator*( u32 right ) const { - return iAddressInfo( Empty, *this, right ); + return xAddressInfo( Empty, *this, right ); } - __forceinline iAddressInfo iAddressReg::operator<<( u32 shift ) const + __forceinline xAddressInfo xAddressReg::operator<<( u32 shift ) const { - return iAddressInfo( Empty, *this, 1< - iForwardJump::iForwardJump( JccComparisonType cctype ) : + xForwardJump::xForwardJump( JccComparisonType cctype ) : BasePtr( (s8*)iGetPtr() + ((OperandSize == 1) ? 2 : // j8's are always 2 bytes. ((cctype==Jcc_Unconditional) ? 5 : 6 )) // j32's are either 5 or 6 bytes @@ -184,15 +184,15 @@ namespace x86Emitter jASSUME( OperandSize == 1 || OperandSize == 4 ); if( OperandSize == 1 ) - iWrite( (cctype == Jcc_Unconditional) ? 0xeb : (0x70 | cctype) ); + xWrite( (cctype == Jcc_Unconditional) ? 0xeb : (0x70 | cctype) ); else { if( cctype == Jcc_Unconditional ) - iWrite( 0xe9 ); + xWrite( 0xe9 ); else { - iWrite( 0x0f ); - iWrite( 0x80 | cctype ); + xWrite( 0x0f ); + xWrite( 0x80 | cctype ); } } @@ -201,7 +201,7 @@ namespace x86Emitter // ------------------------------------------------------------------------ template< typename OperandType > - void iForwardJump::SetTarget() const + void xForwardJump::SetTarget() const { jASSUME( BasePtr != NULL ); diff --git a/pcsx2/x86/ix86/ix86_instructions.h b/pcsx2/x86/ix86/ix86_instructions.h index 2b68790756..1421fba6dd 100644 --- a/pcsx2/x86/ix86/ix86_instructions.h +++ b/pcsx2/x86/ix86/ix86_instructions.h @@ -38,16 +38,16 @@ namespace x86Emitter // ------------------------------------------------------------------------ // Group 1 Instruction Class - extern const Internal::G1LogicImpl iAND; - extern const Internal::G1LogicImpl iOR; - extern const Internal::G1LogicImpl iXOR; - extern const Internal::SSEAndNotImpl<0x55> iANDN; + extern const Internal::G1LogicImpl_PlusSSE xAND; + extern const Internal::G1LogicImpl_PlusSSE xOR; + extern const Internal::G1LogicImpl_PlusSSE xXOR; - extern const Internal::G1ArithmeticImpl iADD; - extern const Internal::G1ArithmeticImpl iSUB; - extern const Internal::Group1ImplAll iADC; - extern const Internal::Group1ImplAll iSBB; - extern const Internal::Group1ImplAll iCMP; + extern const Internal::G1ArithmeticImpl_PlusSSE xADD; + extern const Internal::G1ArithmeticImpl_PlusSSE xSUB; + extern const Internal::G1CompareImpl_PlusSSE xCMP; + + extern const Internal::Group1ImplAll xADC; + extern const Internal::Group1ImplAll xSBB; // ------------------------------------------------------------------------ // Group 2 Instruction Class @@ -56,174 +56,154 @@ namespace x86Emitter // zero. This is a safe optimization since any zero-value shift does not affect any // flags. - extern const Internal::MovImplAll iMOV; - extern const Internal::TestImplAll iTEST; + extern const Internal::MovImplAll xMOV; + extern const Internal::TestImplAll xTEST; - extern const Internal::Group2ImplAll iROL; - extern const Internal::Group2ImplAll iROR; - extern const Internal::Group2ImplAll iRCL; - extern const Internal::Group2ImplAll iRCR; - extern const Internal::Group2ImplAll iSHL; - extern const Internal::Group2ImplAll iSHR; - extern const Internal::Group2ImplAll iSAR; + extern const Internal::Group2ImplAll xROL; + extern const Internal::Group2ImplAll xROR; + extern const Internal::Group2ImplAll xRCL; + extern const Internal::Group2ImplAll xRCR; + extern const Internal::Group2ImplAll xSHL; + extern const Internal::Group2ImplAll xSHR; + extern const Internal::Group2ImplAll xSAR; // ------------------------------------------------------------------------ // Group 3 Instruction Class - extern const Internal::Group3ImplAll iNOT; - extern const Internal::Group3ImplAll iNEG; - extern const Internal::Group3ImplAll iUMUL; - extern const Internal::Group3ImplAll iUDIV; - extern const Internal::G3Impl_PlusSSE iDIV; - extern const Internal::iMul_PlusSSE iMUL; + extern const Internal::Group3ImplAll xNOT; + extern const Internal::Group3ImplAll xNEG; + extern const Internal::Group3ImplAll xUMUL; + extern const Internal::Group3ImplAll xUDIV; + extern const Internal::G3Impl_PlusSSE xDIV; + extern const Internal::iMul_PlusSSE xMUL; - extern const Internal::IncDecImplAll iINC; - extern const Internal::IncDecImplAll iDEC; + extern const Internal::IncDecImplAll xINC; + extern const Internal::IncDecImplAll xDEC; - extern const Internal::MovExtendImplAll iMOVZX; - extern const Internal::MovExtendImplAll iMOVSX; + extern const Internal::MovExtendImplAll xMOVZX; + extern const Internal::MovExtendImplAll xMOVSX; - extern const Internal::DwordShiftImplAll iSHLD; - extern const Internal::DwordShiftImplAll iSHRD; + extern const Internal::DwordShiftImplAll xSHLD; + extern const Internal::DwordShiftImplAll xSHRD; - extern const Internal::Group8ImplAll iBT; - extern const Internal::Group8ImplAll iBTR; - extern const Internal::Group8ImplAll iBTS; - extern const Internal::Group8ImplAll iBTC; + extern const Internal::Group8ImplAll xBT; + extern const Internal::Group8ImplAll xBTR; + extern const Internal::Group8ImplAll xBTS; + extern const Internal::Group8ImplAll xBTC; - extern const Internal::JmpCallImplAll iJMP; - extern const Internal::JmpCallImplAll iCALL; + extern const Internal::JmpCallImplAll xJMP; + extern const Internal::JmpCallImplAll xCALL; - extern const Internal::BitScanImplAll iBSF; - extern const Internal::BitScanImplAll iBSR; + extern const Internal::BitScanImplAll xBSF; + extern const Internal::BitScanImplAll xBSR; // ------------------------------------------------------------------------ - extern const Internal::CMovImplGeneric iCMOV; + extern const Internal::CMovImplGeneric xCMOV; - extern const Internal::CMovImplAll iCMOVA; - extern const Internal::CMovImplAll iCMOVAE; - extern const Internal::CMovImplAll iCMOVB; - extern const Internal::CMovImplAll iCMOVBE; + extern const Internal::CMovImplAll xCMOVA; + extern const Internal::CMovImplAll xCMOVAE; + extern const Internal::CMovImplAll xCMOVB; + extern const Internal::CMovImplAll xCMOVBE; - extern const Internal::CMovImplAll iCMOVG; - extern const Internal::CMovImplAll iCMOVGE; - extern const Internal::CMovImplAll iCMOVL; - extern const Internal::CMovImplAll iCMOVLE; + extern const Internal::CMovImplAll xCMOVG; + extern const Internal::CMovImplAll xCMOVGE; + extern const Internal::CMovImplAll xCMOVL; + extern const Internal::CMovImplAll xCMOVLE; - extern const Internal::CMovImplAll iCMOVZ; - extern const Internal::CMovImplAll iCMOVE; - extern const Internal::CMovImplAll iCMOVNZ; - extern const Internal::CMovImplAll iCMOVNE; + extern const Internal::CMovImplAll xCMOVZ; + extern const Internal::CMovImplAll xCMOVE; + extern const Internal::CMovImplAll xCMOVNZ; + extern const Internal::CMovImplAll xCMOVNE; - extern const Internal::CMovImplAll iCMOVO; - extern const Internal::CMovImplAll iCMOVNO; - extern const Internal::CMovImplAll iCMOVC; - extern const Internal::CMovImplAll iCMOVNC; + extern const Internal::CMovImplAll xCMOVO; + extern const Internal::CMovImplAll xCMOVNO; + extern const Internal::CMovImplAll xCMOVC; + extern const Internal::CMovImplAll xCMOVNC; - extern const Internal::CMovImplAll iCMOVS; - extern const Internal::CMovImplAll iCMOVNS; - extern const Internal::CMovImplAll iCMOVPE; - extern const Internal::CMovImplAll iCMOVPO; + extern const Internal::CMovImplAll xCMOVS; + extern const Internal::CMovImplAll xCMOVNS; + extern const Internal::CMovImplAll xCMOVPE; + extern const Internal::CMovImplAll xCMOVPO; // ------------------------------------------------------------------------ - extern const Internal::SetImplGeneric iSET; + extern const Internal::SetImplGeneric xSET; - extern const Internal::SetImplAll iSETA; - extern const Internal::SetImplAll iSETAE; - extern const Internal::SetImplAll iSETB; - extern const Internal::SetImplAll iSETBE; + extern const Internal::SetImplAll xSETA; + extern const Internal::SetImplAll xSETAE; + extern const Internal::SetImplAll xSETB; + extern const Internal::SetImplAll xSETBE; - extern const Internal::SetImplAll iSETG; - extern const Internal::SetImplAll iSETGE; - extern const Internal::SetImplAll iSETL; - extern const Internal::SetImplAll iSETLE; + extern const Internal::SetImplAll xSETG; + extern const Internal::SetImplAll xSETGE; + extern const Internal::SetImplAll xSETL; + extern const Internal::SetImplAll xSETLE; - extern const Internal::SetImplAll iSETZ; - extern const Internal::SetImplAll iSETE; - extern const Internal::SetImplAll iSETNZ; - extern const Internal::SetImplAll iSETNE; + extern const Internal::SetImplAll xSETZ; + extern const Internal::SetImplAll xSETE; + extern const Internal::SetImplAll xSETNZ; + extern const Internal::SetImplAll xSETNE; - extern const Internal::SetImplAll iSETO; - extern const Internal::SetImplAll iSETNO; - extern const Internal::SetImplAll iSETC; - extern const Internal::SetImplAll iSETNC; + extern const Internal::SetImplAll xSETO; + extern const Internal::SetImplAll xSETNO; + extern const Internal::SetImplAll xSETC; + extern const Internal::SetImplAll xSETNC; - extern const Internal::SetImplAll iSETS; - extern const Internal::SetImplAll iSETNS; - extern const Internal::SetImplAll iSETPE; - extern const Internal::SetImplAll iSETPO; + extern const Internal::SetImplAll xSETS; + extern const Internal::SetImplAll xSETNS; + extern const Internal::SetImplAll xSETPE; + extern const Internal::SetImplAll xSETPO; ////////////////////////////////////////////////////////////////////////////////////////// // Miscellaneous Instructions // These are all defined inline or in ix86.cpp. // - extern void iBSWAP( const iRegister32& to ); + extern void xBSWAP( const xRegister32& to ); // ----- Lea Instructions (Load Effective Address) ----- // Note: alternate (void*) forms of these instructions are not provided since those // forms are functionally equivalent to Mov reg,imm, and thus better written as MOVs // instead. - extern void iLEA( iRegister32 to, const ModSibBase& src, bool preserve_flags=false ); - extern void iLEA( iRegister16 to, const ModSibBase& src, bool preserve_flags=false ); + extern void xLEA( xRegister32 to, const ModSibBase& src, bool preserve_flags=false ); + extern void xLEA( xRegister16 to, const ModSibBase& src, bool preserve_flags=false ); // ----- Push / Pop Instructions ----- // Note: pushad/popad implementations are intentionally left out. The instructions are // invalid in x64, and are super slow on x32. Use multiple Push/Pop instructions instead. - extern void iPOP( const ModSibBase& from ); - extern void iPUSH( const ModSibBase& from ); + extern void xPOP( const ModSibBase& from ); + extern void xPUSH( const ModSibBase& from ); - static __forceinline void iPOP( iRegister32 from ) { write8( 0x58 | from.Id ); } - static __forceinline void iPOP( void* from ) { iPOP( ptr[from] ); } + static __forceinline void xPOP( xRegister32 from ) { write8( 0x58 | from.Id ); } + static __forceinline void xPOP( void* from ) { xPOP( ptr[from] ); } - static __forceinline void iPUSH( u32 imm ) { write8( 0x68 ); write32( imm ); } - static __forceinline void iPUSH( iRegister32 from ) { write8( 0x50 | from.Id ); } - static __forceinline void iPUSH( void* from ) { iPUSH( ptr[from] ); } + static __forceinline void xPUSH( u32 imm ) { write8( 0x68 ); write32( imm ); } + static __forceinline void xPUSH( xRegister32 from ) { write8( 0x50 | from.Id ); } + static __forceinline void xPUSH( void* from ) { xPUSH( ptr[from] ); } // pushes the EFLAGS register onto the stack - static __forceinline void iPUSHFD() { write8( 0x9C ); } + static __forceinline void xPUSHFD() { write8( 0x9C ); } // pops the EFLAGS register from the stack - static __forceinline void iPOPFD() { write8( 0x9D ); } + static __forceinline void xPOPFD() { write8( 0x9D ); } // ----- Miscellaneous Instructions ----- // Various Instructions with no parameter and no special encoding logic. - __forceinline void iRET() { write8( 0xC3 ); } - __forceinline void iCBW() { write16( 0x9866 ); } - __forceinline void iCWD() { write8( 0x98 ); } - __forceinline void iCDQ() { write8( 0x99 ); } - __forceinline void iCWDE() { write8( 0x98 ); } + __forceinline void xRET() { write8( 0xC3 ); } + __forceinline void xCBW() { write16( 0x9866 ); } + __forceinline void xCWD() { write8( 0x98 ); } + __forceinline void xCDQ() { write8( 0x99 ); } + __forceinline void xCWDE() { write8( 0x98 ); } - __forceinline void iLAHF() { write8( 0x9f ); } - __forceinline void iSAHF() { write8( 0x9e ); } + __forceinline void xLAHF() { write8( 0x9f ); } + __forceinline void xSAHF() { write8( 0x9e ); } - __forceinline void iSTC() { write8( 0xF9 ); } - __forceinline void iCLC() { write8( 0xF8 ); } + __forceinline void xSTC() { write8( 0xF9 ); } + __forceinline void xCLC() { write8( 0xF8 ); } // NOP 1-byte - __forceinline void iNOP() { write8(0x90); } - - ////////////////////////////////////////////////////////////////////////////////////////// - // MUL / DIV instructions - - /*extern void iMUL( const iRegister32& to, const iRegister32& from ); - extern void iMUL( const iRegister32& to, const void* src ); - extern void iMUL( const iRegister32& to, const iRegister32& from, s32 imm ); - extern void iMUL( const iRegister32& to, const ModSibBase& src ); - extern void iMUL( const iRegister32& to, const ModSibBase& src, s32 imm ); - - extern void iMUL( const iRegister16& to, const iRegister16& from ); - extern void iMUL( const iRegister16& to, const void* src ); - extern void iMUL( const iRegister16& to, const iRegister16& from, s16 imm ); - extern void iMUL( const iRegister16& to, const ModSibBase& src ); - extern void iMUL( const iRegister16& to, const ModSibBase& src, s16 imm ); - - template< typename T > - __forceinline void iMUL( const iRegister& from ) { Internal::Group3Impl::Emit( Internal::G3Type_iMUL, from ); } - template< typename T > - __noinline void iMUL( const ModSibStrict& from ) { Internal::Group3Impl::Emit( Internal::G3Type_iMUL, from ); }*/ + __forceinline void xNOP() { write8(0x90); } ////////////////////////////////////////////////////////////////////////////////////////// // JMP / Jcc Instructions! @@ -232,92 +212,92 @@ namespace x86Emitter #define DEFINE_FORWARD_JUMP( label, cond ) \ template< typename OperandType > \ - class iForward##label : public iForwardJump \ + class xForward##label : public xForwardJump \ { \ public: \ - iForward##label() : iForwardJump( cond ) {} \ + xForward##label() : xForwardJump( cond ) {} \ }; // ------------------------------------------------------------------------ // Note: typedefs below are defined individually in order to appease Intellisense // resolution. Including them into the class definition macro above breaks it. - typedef iForwardJump iForwardJump8; - typedef iForwardJump iForwardJump32; + typedef xForwardJump xForwardJump8; + typedef xForwardJump xForwardJump32; DEFINE_FORWARD_JUMP( JA, Jcc_Above ); DEFINE_FORWARD_JUMP( JB, Jcc_Below ); DEFINE_FORWARD_JUMP( JAE, Jcc_AboveOrEqual ); DEFINE_FORWARD_JUMP( JBE, Jcc_BelowOrEqual ); - typedef iForwardJA iForwardJA8; - typedef iForwardJA iForwardJA32; - typedef iForwardJB iForwardJB8; - typedef iForwardJB iForwardJB32; - typedef iForwardJAE iForwardJAE8; - typedef iForwardJAE iForwardJAE32; - typedef iForwardJBE iForwardJBE8; - typedef iForwardJBE iForwardJBE32; + typedef xForwardJA xForwardJA8; + typedef xForwardJA xForwardJA32; + typedef xForwardJB xForwardJB8; + typedef xForwardJB xForwardJB32; + typedef xForwardJAE xForwardJAE8; + typedef xForwardJAE xForwardJAE32; + typedef xForwardJBE xForwardJBE8; + typedef xForwardJBE xForwardJBE32; DEFINE_FORWARD_JUMP( JG, Jcc_Greater ); DEFINE_FORWARD_JUMP( JL, Jcc_Less ); DEFINE_FORWARD_JUMP( JGE, Jcc_GreaterOrEqual ); DEFINE_FORWARD_JUMP( JLE, Jcc_LessOrEqual ); - typedef iForwardJG iForwardJG8; - typedef iForwardJG iForwardJG32; - typedef iForwardJL iForwardJL8; - typedef iForwardJL iForwardJL32; - typedef iForwardJGE iForwardJGE8; - typedef iForwardJGE iForwardJGE32; - typedef iForwardJLE iForwardJLE8; - typedef iForwardJLE iForwardJLE32; + typedef xForwardJG xForwardJG8; + typedef xForwardJG xForwardJG32; + typedef xForwardJL xForwardJL8; + typedef xForwardJL xForwardJL32; + typedef xForwardJGE xForwardJGE8; + typedef xForwardJGE xForwardJGE32; + typedef xForwardJLE xForwardJLE8; + typedef xForwardJLE xForwardJLE32; DEFINE_FORWARD_JUMP( JZ, Jcc_Zero ); DEFINE_FORWARD_JUMP( JE, Jcc_Equal ); DEFINE_FORWARD_JUMP( JNZ, Jcc_NotZero ); DEFINE_FORWARD_JUMP( JNE, Jcc_NotEqual ); - typedef iForwardJZ iForwardJZ8; - typedef iForwardJZ iForwardJZ32; - typedef iForwardJE iForwardJE8; - typedef iForwardJE iForwardJE32; - typedef iForwardJNZ iForwardJNZ8; - typedef iForwardJNZ iForwardJNZ32; - typedef iForwardJNE iForwardJNE8; - typedef iForwardJNE iForwardJNE32; + typedef xForwardJZ xForwardJZ8; + typedef xForwardJZ xForwardJZ32; + typedef xForwardJE xForwardJE8; + typedef xForwardJE xForwardJE32; + typedef xForwardJNZ xForwardJNZ8; + typedef xForwardJNZ xForwardJNZ32; + typedef xForwardJNE xForwardJNE8; + typedef xForwardJNE xForwardJNE32; DEFINE_FORWARD_JUMP( JS, Jcc_Signed ); DEFINE_FORWARD_JUMP( JNS, Jcc_Unsigned ); - typedef iForwardJS iForwardJS8; - typedef iForwardJS iForwardJS32; - typedef iForwardJNS iForwardJNS8; - typedef iForwardJNS iForwardJNS32; + typedef xForwardJS xForwardJS8; + typedef xForwardJS xForwardJS32; + typedef xForwardJNS xForwardJNS8; + typedef xForwardJNS xForwardJNS32; DEFINE_FORWARD_JUMP( JO, Jcc_Overflow ); DEFINE_FORWARD_JUMP( JNO, Jcc_NotOverflow ); - typedef iForwardJO iForwardJO8; - typedef iForwardJO iForwardJO32; - typedef iForwardJNO iForwardJNO8; - typedef iForwardJNO iForwardJNO32; + typedef xForwardJO xForwardJO8; + typedef xForwardJO xForwardJO32; + typedef xForwardJNO xForwardJNO8; + typedef xForwardJNO xForwardJNO32; DEFINE_FORWARD_JUMP( JC, Jcc_Carry ); DEFINE_FORWARD_JUMP( JNC, Jcc_NotCarry ); - typedef iForwardJC iForwardJC8; - typedef iForwardJC iForwardJC32; - typedef iForwardJNC iForwardJNC8; - typedef iForwardJNC iForwardJNC32; + typedef xForwardJC xForwardJC8; + typedef xForwardJC xForwardJC32; + typedef xForwardJNC xForwardJNC8; + typedef xForwardJNC xForwardJNC32; DEFINE_FORWARD_JUMP( JPE, Jcc_ParityEven ); DEFINE_FORWARD_JUMP( JPO, Jcc_ParityOdd ); - typedef iForwardJPE iForwardJPE8; - typedef iForwardJPE iForwardJPE32; - typedef iForwardJPO iForwardJPO8; - typedef iForwardJPO iForwardJPO32; + typedef xForwardJPE xForwardJPE8; + typedef xForwardJPE xForwardJPE32; + typedef xForwardJPO xForwardJPO8; + typedef xForwardJPO xForwardJPO32; ////////////////////////////////////////////////////////////////////////////////////////// // MMX Mov Instructions (MOVD, MOVQ, MOVSS). @@ -332,53 +312,53 @@ namespace x86Emitter // MOVD has valid forms for MMX and XMM registers. // template< typename T > - __emitinline void iMOVDZX( const iRegisterSIMD& to, const iRegister32& from ) + __emitinline void xMOVDZX( const xRegisterSIMD& to, const xRegister32& from ) { Internal::writeXMMop( 0x66, 0x6e, to, from ); } template< typename T > - __emitinline void iMOVDZX( const iRegisterSIMD& to, const void* src ) + __emitinline void xMOVDZX( const xRegisterSIMD& to, const void* src ) { Internal::writeXMMop( 0x66, 0x6e, to, src ); } template< typename T > - void iMOVDZX( const iRegisterSIMD& to, const ModSibBase& src ) + void xMOVDZX( const xRegisterSIMD& to, const ModSibBase& src ) { Internal::writeXMMop( 0x66, 0x6e, to, src ); } template< typename T > - __emitinline void iMOVD( const iRegister32& to, const iRegisterSIMD& from ) + __emitinline void xMOVD( const xRegister32& to, const xRegisterSIMD& from ) { Internal::writeXMMop( 0x66, 0x7e, from, to ); } template< typename T > - __emitinline void iMOVD( void* dest, const iRegisterSIMD& from ) + __emitinline void xMOVD( void* dest, const xRegisterSIMD& from ) { Internal::writeXMMop( 0x66, 0x7e, from, dest ); } template< typename T > - void iMOVD( const ModSibBase& dest, const iRegisterSIMD& from ) + void xMOVD( const ModSibBase& dest, const xRegisterSIMD& from ) { Internal::writeXMMop( 0x66, 0x7e, from, dest ); } // ------------------------------------------------------------------------ - // iMASKMOV: + // xMASKMOV: // Selectively write bytes from mm1/xmm1 to memory location using the byte mask in mm2/xmm2. // The default memory location is specified by DS:EDI. The most significant bit in each byte // of the mask operand determines whether the corresponding byte in the source operand is // written to the corresponding byte location in memory. template< typename T > - static __forceinline void iMASKMOV( const iRegisterSIMD& to, const iRegisterSIMD& from ) { Internal::writeXMMop( 0x66, 0xf7, to, from ); } + static __forceinline void xMASKMOV( const xRegisterSIMD& to, const xRegisterSIMD& from ) { Internal::writeXMMop( 0x66, 0xf7, to, from ); } - // iPMOVMSKB: + // xPMOVMSKB: // Creates a mask made up of the most significant bit of each byte of the source // operand and stores the result in the low byte or word of the destination operand. // Upper bits of the destination are cleared to zero. @@ -387,93 +367,91 @@ namespace x86Emitter // 128-bit (SSE) source, the byte mask is 16-bits. // template< typename T > - static __forceinline void iPMOVMSKB( const iRegister32& to, const iRegisterSIMD& from ) { Internal::writeXMMop( 0x66, 0xd7, to, from ); } + static __forceinline void xPMOVMSKB( const xRegister32& to, const xRegisterSIMD& from ) { Internal::writeXMMop( 0x66, 0xd7, to, from ); } // ------------------------------------------------------------------------ - extern void iMOVQ( const iRegisterMMX& to, const iRegisterMMX& from ); - extern void iMOVQ( const iRegisterMMX& to, const iRegisterSSE& from ); - extern void iMOVQ( const iRegisterSSE& to, const iRegisterMMX& from ); + extern void xMOVQ( const xRegisterMMX& to, const xRegisterMMX& from ); + extern void xMOVQ( const xRegisterMMX& to, const xRegisterSSE& from ); + extern void xMOVQ( const xRegisterSSE& to, const xRegisterMMX& from ); - extern void iMOVQ( void* dest, const iRegisterSSE& from ); - extern void iMOVQ( const ModSibBase& dest, const iRegisterSSE& from ); - extern void iMOVQ( void* dest, const iRegisterMMX& from ); - extern void iMOVQ( const ModSibBase& dest, const iRegisterMMX& from ); - extern void iMOVQ( const iRegisterMMX& to, const void* src ); - extern void iMOVQ( const iRegisterMMX& to, const ModSibBase& src ); + extern void xMOVQ( void* dest, const xRegisterSSE& from ); + extern void xMOVQ( const ModSibBase& dest, const xRegisterSSE& from ); + extern void xMOVQ( void* dest, const xRegisterMMX& from ); + extern void xMOVQ( const ModSibBase& dest, const xRegisterMMX& from ); + extern void xMOVQ( const xRegisterMMX& to, const void* src ); + extern void xMOVQ( const xRegisterMMX& to, const ModSibBase& src ); - extern void iMOVQZX( const iRegisterSSE& to, const void* src ); - extern void iMOVQZX( const iRegisterSSE& to, const ModSibBase& src ); - extern void iMOVQZX( const iRegisterSSE& to, const iRegisterSSE& from ); + extern void xMOVQZX( const xRegisterSSE& to, const void* src ); + extern void xMOVQZX( const xRegisterSSE& to, const ModSibBase& src ); + extern void xMOVQZX( const xRegisterSSE& to, const xRegisterSSE& from ); - extern void iMOVSS( const iRegisterSSE& to, const iRegisterSSE& from ); - extern void iMOVSS( const void* to, const iRegisterSSE& from ); - extern void iMOVSS( const ModSibBase& to, const iRegisterSSE& from ); - extern void iMOVSD( const iRegisterSSE& to, const iRegisterSSE& from ); - extern void iMOVSD( const void* to, const iRegisterSSE& from ); - extern void iMOVSD( const ModSibBase& to, const iRegisterSSE& from ); + extern void xMOVSS( const xRegisterSSE& to, const xRegisterSSE& from ); + extern void xMOVSS( const void* to, const xRegisterSSE& from ); + extern void xMOVSS( const ModSibBase& to, const xRegisterSSE& from ); + extern void xMOVSD( const xRegisterSSE& to, const xRegisterSSE& from ); + extern void xMOVSD( const void* to, const xRegisterSSE& from ); + extern void xMOVSD( const ModSibBase& to, const xRegisterSSE& from ); - extern void iMOVSSZX( const iRegisterSSE& to, const void* from ); - extern void iMOVSSZX( const iRegisterSSE& to, const ModSibBase& from ); - extern void iMOVSDZX( const iRegisterSSE& to, const void* from ); - extern void iMOVSDZX( const iRegisterSSE& to, const ModSibBase& from ); + extern void xMOVSSZX( const xRegisterSSE& to, const void* from ); + extern void xMOVSSZX( const xRegisterSSE& to, const ModSibBase& from ); + extern void xMOVSDZX( const xRegisterSSE& to, const void* from ); + extern void xMOVSDZX( const xRegisterSSE& to, const ModSibBase& from ); - extern void iMOVNTDQA( const iRegisterSSE& to, const void* from ); - extern void iMOVNTDQA( const iRegisterSSE& to, const ModSibBase& from ); - extern void iMOVNTDQ( void* to, const iRegisterSSE& from ); - extern void iMOVNTDQA( const ModSibBase& to, const iRegisterSSE& from ); + extern void xMOVNTDQA( const xRegisterSSE& to, const void* from ); + extern void xMOVNTDQA( const xRegisterSSE& to, const ModSibBase& from ); + extern void xMOVNTDQ( void* to, const xRegisterSSE& from ); + extern void xMOVNTDQA( const ModSibBase& to, const xRegisterSSE& from ); - extern void iMOVNTPD( void* to, const iRegisterSSE& from ); - extern void iMOVNTPD( const ModSibBase& to, const iRegisterSSE& from ); - extern void iMOVNTPS( void* to, const iRegisterSSE& from ); - extern void iMOVNTPS( const ModSibBase& to, const iRegisterSSE& from ); - extern void iMOVNTQ( void* to, const iRegisterMMX& from ); - extern void iMOVNTQ( const ModSibBase& to, const iRegisterMMX& from ); - - extern void iMOVLHPS( const iRegisterSSE& to, const iRegisterSSE& from ); - extern void iMOVHLPS( const iRegisterSSE& to, const iRegisterSSE& from ); - extern void iMOVLHPD( const iRegisterSSE& to, const iRegisterSSE& from ); - extern void iMOVHLPD( const iRegisterSSE& to, const iRegisterSSE& from ); + extern void xMOVNTPD( void* to, const xRegisterSSE& from ); + extern void xMOVNTPD( const ModSibBase& to, const xRegisterSSE& from ); + extern void xMOVNTPS( void* to, const xRegisterSSE& from ); + extern void xMOVNTPS( const ModSibBase& to, const xRegisterSSE& from ); + extern void xMOVNTQ( void* to, const xRegisterMMX& from ); + extern void xMOVNTQ( const ModSibBase& to, const xRegisterMMX& from ); ////////////////////////////////////////////////////////////////////////////////////////// // - extern const Internal::MovapsImplAll<0, 0x28, 0x29> iMOVAPS; - extern const Internal::MovapsImplAll<0, 0x10, 0x11> iMOVUPS; + extern const Internal::MovapsImplAll<0, 0x28, 0x29> xMOVAPS; + extern const Internal::MovapsImplAll<0, 0x10, 0x11> xMOVUPS; - extern const Internal::MovapsImplAll<0x66, 0x28, 0x29> iMOVAPD; - extern const Internal::MovapsImplAll<0x66, 0x10, 0x11> iMOVUPD; + extern const Internal::MovapsImplAll<0x66, 0x28, 0x29> xMOVAPD; + extern const Internal::MovapsImplAll<0x66, 0x10, 0x11> xMOVUPD; #ifdef ALWAYS_USE_MOVAPS - extern const Internal::MovapsImplAll<0x66, 0x6f, 0x7f> iMOVDQA; - extern const Internal::MovapsImplAll<0xf3, 0x6f, 0x7f> iMOVDQU; + extern const Internal::MovapsImplAll<0x66, 0x6f, 0x7f> xMOVDQA; + extern const Internal::MovapsImplAll<0xf3, 0x6f, 0x7f> xMOVDQU; #else - extern const Internal::MovapsImplAll<0, 0x28, 0x29> iMOVDQA; - extern const Internal::MovapsImplAll<0, 0x10, 0x11> iMOVDQU; + extern const Internal::MovapsImplAll<0, 0x28, 0x29> xMOVDQA; + extern const Internal::MovapsImplAll<0, 0x10, 0x11> xMOVDQU; #endif - extern const Internal::MovhlImplAll<0, 0x16> iMOVHPS; - extern const Internal::MovhlImplAll<0, 0x12> iMOVLPS; - extern const Internal::MovhlImplAll<0x66, 0x16> iMOVHPD; - extern const Internal::MovhlImplAll<0x66, 0x12> iMOVLPD; + extern const Internal::MovhlImpl_RtoR<0x16> xMOVLH; + extern const Internal::MovhlImpl_RtoR<0x12> xMOVHL; - extern const Internal::PLogicImplAll<0xdb> iPAND; - extern const Internal::PLogicImplAll<0xdf> iPANDN; - extern const Internal::PLogicImplAll<0xeb> iPOR; - extern const Internal::PLogicImplAll<0xef> iPXOR; + extern const Internal::MovhlImplAll<0x16> xMOVH; + extern const Internal::MovhlImplAll<0x12> xMOVL; - extern const Internal::SSELogicImpl<0,0x53> iRCPPS; - extern const Internal::SSELogicImpl<0xf3,0x53> iRCPSS; + extern const Internal::PLogicImplAll<0xdb> xPAND; + extern const Internal::PLogicImplAll<0xdf> xPANDN; + extern const Internal::PLogicImplAll<0xeb> xPOR; + extern const Internal::PLogicImplAll<0xef> xPXOR; - extern const Internal::SSECompareImplGeneric<0x00> iCMPPS; - extern const Internal::SSECompareImplGeneric<0x66> iCMPPD; - extern const Internal::SSECompareImplGeneric<0xf3> iCMPSS; - extern const Internal::SSECompareImplGeneric<0xf2> iCMPSD; - - extern const Internal::SSECompareImplGeneric<0x00> iCMPPS; - extern const Internal::SSECompareImplGeneric<0x66> iCMPPD; - extern const Internal::SSECompareImplGeneric<0xf3> iCMPSS; - extern const Internal::SSECompareImplGeneric<0xf2> iCMPSD; + extern const Internal::SSEAndNotImpl<0x55> xANDN; + extern const Internal::SSELogicImpl<0,0x53> xRCPPS; + extern const Internal::SSELogicImpl<0xf3,0x53> xRCPSS; + + // ------------------------------------------------------------------------ + + extern const Internal::SSECompareImpl xCMPEQ; + extern const Internal::SSECompareImpl xCMPLT; + extern const Internal::SSECompareImpl xCMPLE; + extern const Internal::SSECompareImpl xCMPUNORD; + extern const Internal::SSECompareImpl xCMPNE; + extern const Internal::SSECompareImpl xCMPNLT; + extern const Internal::SSECompareImpl xCMPNLE; + extern const Internal::SSECompareImpl xCMPORD; } diff --git a/pcsx2/x86/ix86/ix86_jmp.cpp b/pcsx2/x86/ix86/ix86_jmp.cpp index 9189cd21da..15f3fc68f9 100644 --- a/pcsx2/x86/ix86/ix86_jmp.cpp +++ b/pcsx2/x86/ix86/ix86_jmp.cpp @@ -40,11 +40,11 @@ namespace x86Emitter { using namespace Internal; -const JmpCallImplAll iJMP; -const JmpCallImplAll iCALL; +const JmpCallImplAll xJMP; +const JmpCallImplAll xCALL; // ------------------------------------------------------------------------ -void iSmartJump::SetTarget() +void xSmartJump::SetTarget() { u8* target = iGetPtr(); if( m_baseptr == NULL ) return; @@ -67,7 +67,7 @@ void iSmartJump::SetTarget() } } -iSmartJump::~iSmartJump() +xSmartJump::~xSmartJump() { SetTarget(); m_baseptr = NULL; // just in case (sometimes helps in debugging too) @@ -78,7 +78,7 @@ iSmartJump::~iSmartJump() // Writes a jump at the current x86Ptr, which targets a pre-established target address. // (usually a backwards jump) // -// slideForward - used internally by iSmartJump to indicate that the jump target is going +// slideForward - used internally by xSmartJump to indicate that the jump target is going // to slide forward in the event of an 8 bit displacement. // // Using this @@ -96,21 +96,21 @@ __emitinline void iJccKnownTarget( JccComparisonType comparison, void* target, b if( is_s8( displacement8 ) ) { - iWrite( (comparison == Jcc_Unconditional) ? 0xeb : (0x70 | comparison) ); - iWrite( displacement8 ); + xWrite( (comparison == Jcc_Unconditional) ? 0xeb : (0x70 | comparison) ); + xWrite( displacement8 ); } else { // Perform a 32 bit jump instead. :( if( comparison == Jcc_Unconditional ) - iWrite( 0xe9 ); + xWrite( 0xe9 ); else { - iWrite( 0x0f ); - iWrite( 0x80 | comparison ); + xWrite( 0x0f ); + xWrite( 0x80 | comparison ); } - iWrite( (sptr)target - ((sptr)iGetPtr() + 4) ); + xWrite( (sptr)target - ((sptr)iGetPtr() + 4) ); } } diff --git a/pcsx2/x86/ix86/ix86_legacy.cpp b/pcsx2/x86/ix86/ix86_legacy.cpp index a484579f88..8f07278443 100644 --- a/pcsx2/x86/ix86/ix86_legacy.cpp +++ b/pcsx2/x86/ix86/ix86_legacy.cpp @@ -35,9 +35,9 @@ using namespace x86Emitter; template< typename ImmType > -static __forceinline iRegister _reghlp( x86IntRegType src ) +static __forceinline xRegister _reghlp( x86IntRegType src ) { - return iRegister( src ); + return xRegister( src ); } static __forceinline ModSibBase _mrmhlp( x86IntRegType src ) @@ -48,43 +48,43 @@ static __forceinline ModSibBase _mrmhlp( x86IntRegType src ) template< typename ImmType > static __forceinline ModSibStrict _mhlp( x86IntRegType src ) { - return ModSibStrict( iAddressReg::Empty, iAddressReg(src) ); + return ModSibStrict( xAddressReg::Empty, xAddressReg(src) ); } template< typename ImmType > static __forceinline ModSibStrict _mhlp2( x86IntRegType src1, x86IntRegType src2 ) { - return ModSibStrict( iAddressReg(src2), iAddressReg(src1) ); + return ModSibStrict( xAddressReg(src2), xAddressReg(src1) ); } ////////////////////////////////////////////////////////////////////////////////////////// // #define DEFINE_LEGACY_HELPER( cod, bits ) \ - emitterT void cod##bits##RtoR( x86IntRegType to, x86IntRegType from ) { i##cod( _reghlp(to), _reghlp(from) ); } \ - emitterT void cod##bits##ItoR( x86IntRegType to, u##bits imm ) { i##cod( _reghlp(to), imm ); } \ - emitterT void cod##bits##MtoR( x86IntRegType to, uptr from ) { i##cod( _reghlp(to), (void*)from ); } \ - emitterT void cod##bits##RtoM( uptr to, x86IntRegType from ) { i##cod( (void*)to, _reghlp(from) ); } \ - emitterT void cod##bits##ItoM( uptr to, u##bits imm ) { i##cod( ptr##bits[to], imm ); } \ - emitterT void cod##bits##ItoRm( x86IntRegType to, u##bits imm, int offset ) { i##cod( _mhlp(to) + offset, imm ); } \ - emitterT void cod##bits##RmtoR( x86IntRegType to, x86IntRegType from, int offset ) { i##cod( _reghlp(to), _mhlp(from) + offset ); } \ - emitterT void cod##bits##RtoRm( x86IntRegType to, x86IntRegType from, int offset ) { i##cod( _mhlp(to) + offset, _reghlp(from) ); } \ + emitterT void cod##bits##RtoR( x86IntRegType to, x86IntRegType from ) { x##cod( _reghlp(to), _reghlp(from) ); } \ + emitterT void cod##bits##ItoR( x86IntRegType to, u##bits imm ) { x##cod( _reghlp(to), imm ); } \ + emitterT void cod##bits##MtoR( x86IntRegType to, uptr from ) { x##cod( _reghlp(to), (void*)from ); } \ + emitterT void cod##bits##RtoM( uptr to, x86IntRegType from ) { x##cod( (void*)to, _reghlp(from) ); } \ + emitterT void cod##bits##ItoM( uptr to, u##bits imm ) { x##cod( ptr##bits[to], imm ); } \ + emitterT void cod##bits##ItoRm( x86IntRegType to, u##bits imm, int offset ) { x##cod( _mhlp(to) + offset, imm ); } \ + emitterT void cod##bits##RmtoR( x86IntRegType to, x86IntRegType from, int offset ) { x##cod( _reghlp(to), _mhlp(from) + offset ); } \ + emitterT void cod##bits##RtoRm( x86IntRegType to, x86IntRegType from, int offset ) { x##cod( _mhlp(to) + offset, _reghlp(from) ); } \ emitterT void cod##bits##RtoRmS( x86IntRegType to1, x86IntRegType to2, x86IntRegType from, int offset ) \ - { i##cod( _mhlp2(to1,to2) + offset, _reghlp(from) ); } \ + { x##cod( _mhlp2(to1,to2) + offset, _reghlp(from) ); } \ emitterT void cod##bits##RmStoR( x86IntRegType to, x86IntRegType from1, x86IntRegType from2, int offset ) \ - { i##cod( _reghlp(to), _mhlp2(from1,from2) + offset ); } + { x##cod( _reghlp(to), _mhlp2(from1,from2) + offset ); } #define DEFINE_LEGACY_SHIFT_HELPER( cod, bits ) \ - emitterT void cod##bits##CLtoR( x86IntRegType to ) { i##cod( _reghlp(to), cl ); } \ - emitterT void cod##bits##ItoR( x86IntRegType to, u8 imm ) { i##cod( _reghlp(to), imm ); } \ - emitterT void cod##bits##CLtoM( uptr to ) { i##cod( ptr##bits[to], cl ); } \ - emitterT void cod##bits##ItoM( uptr to, u8 imm ) { i##cod( ptr##bits[to], imm ); } \ - emitterT void cod##bits##ItoRm( x86IntRegType to, u8 imm, int offset ) { i##cod( _mhlp(to) + offset, imm ); } \ - emitterT void cod##bits##CLtoRm( x86IntRegType to, int offset ) { i##cod( _mhlp(to) + offset, cl ); } + emitterT void cod##bits##CLtoR( x86IntRegType to ) { x##cod( _reghlp(to), cl ); } \ + emitterT void cod##bits##ItoR( x86IntRegType to, u8 imm ) { x##cod( _reghlp(to), imm ); } \ + emitterT void cod##bits##CLtoM( uptr to ) { x##cod( ptr##bits[to], cl ); } \ + emitterT void cod##bits##ItoM( uptr to, u8 imm ) { x##cod( ptr##bits[to], imm ); } \ + emitterT void cod##bits##ItoRm( x86IntRegType to, u8 imm, int offset ) { x##cod( _mhlp(to) + offset, imm ); } \ + emitterT void cod##bits##CLtoRm( x86IntRegType to, int offset ) { x##cod( _mhlp(to) + offset, cl ); } #define DEFINE_LEGACY_ONEREG_HELPER( cod, bits ) \ - emitterT void cod##bits##R( x86IntRegType to ) { i##cod( _reghlp(to) ); } \ - emitterT void cod##bits##M( uptr to ) { i##cod( ptr##bits[to] ); } \ - emitterT void cod##bits##Rm( x86IntRegType to, uptr offset ) { i##cod( _mhlp(to) + offset ); } + emitterT void cod##bits##R( x86IntRegType to ) { x##cod( _reghlp(to) ); } \ + emitterT void cod##bits##M( uptr to ) { x##cod( ptr##bits[to] ); } \ + emitterT void cod##bits##Rm( x86IntRegType to, uptr offset ) { x##cod( _mhlp(to) + offset ); } //emitterT void cod##bits##RtoRmS( x86IntRegType to1, x86IntRegType to2, x86IntRegType from, int offset ) \ // { cod( _mhlp2(to1,to2) + offset, _reghlp(from) ); } \ @@ -133,9 +133,9 @@ DEFINE_OPCODE_ONEREG_LEGACY( NEG ) // ------------------------------------------------------------------------ #define DEFINE_LEGACY_MOVEXTEND( form, destbits, srcbits ) \ - emitterT void MOV##form##destbits##R##srcbits##toR( x86IntRegType to, x86IntRegType from ) { iMOV##form( iRegister##destbits( to ), iRegister##srcbits( from ) ); } \ - emitterT void MOV##form##destbits##Rm##srcbits##toR( x86IntRegType to, x86IntRegType from, int offset ) { iMOV##form( iRegister##destbits( to ), ptr##srcbits[iAddressReg( from ) + offset] ); } \ - emitterT void MOV##form##destbits##M##srcbits##toR( x86IntRegType to, u32 from ) { iMOV##form( iRegister##destbits( to ), ptr##srcbits[from] ); } + emitterT void MOV##form##destbits##R##srcbits##toR( x86IntRegType to, x86IntRegType from ) { xMOV##form( xRegister##destbits( to ), xRegister##srcbits( from ) ); } \ + emitterT void MOV##form##destbits##Rm##srcbits##toR( x86IntRegType to, x86IntRegType from, int offset ) { xMOV##form( xRegister##destbits( to ), ptr##srcbits[xAddressReg( from ) + offset] ); } \ + emitterT void MOV##form##destbits##M##srcbits##toR( x86IntRegType to, u32 from ) { xMOV##form( xRegister##destbits( to ), ptr##srcbits[from] ); } DEFINE_LEGACY_MOVEXTEND( SX, 32, 16 ) DEFINE_LEGACY_MOVEXTEND( ZX, 32, 16 ) @@ -145,164 +145,164 @@ DEFINE_LEGACY_MOVEXTEND( ZX, 32, 8 ) DEFINE_LEGACY_MOVEXTEND( SX, 16, 8 ) DEFINE_LEGACY_MOVEXTEND( ZX, 16, 8 ) -emitterT void TEST32ItoR( x86IntRegType to, u32 from ) { iTEST( iRegister32(to), from ); } -emitterT void TEST32ItoM( uptr to, u32 from ) { iTEST( ptr32[to], from ); } -emitterT void TEST32RtoR( x86IntRegType to, x86IntRegType from ) { iTEST( iRegister32(to), iRegister32(from) ); } -emitterT void TEST32ItoRm( x86IntRegType to, u32 from ) { iTEST( ptr32[iAddressReg(to)], from ); } +emitterT void TEST32ItoR( x86IntRegType to, u32 from ) { xTEST( xRegister32(to), from ); } +emitterT void TEST32ItoM( uptr to, u32 from ) { xTEST( ptr32[to], from ); } +emitterT void TEST32RtoR( x86IntRegType to, x86IntRegType from ) { xTEST( xRegister32(to), xRegister32(from) ); } +emitterT void TEST32ItoRm( x86IntRegType to, u32 from ) { xTEST( ptr32[xAddressReg(to)], from ); } -emitterT void TEST16ItoR( x86IntRegType to, u16 from ) { iTEST( iRegister16(to), from ); } -emitterT void TEST16ItoM( uptr to, u16 from ) { iTEST( ptr16[to], from ); } -emitterT void TEST16RtoR( x86IntRegType to, x86IntRegType from ) { iTEST( iRegister16(to), iRegister16(from) ); } -emitterT void TEST16ItoRm( x86IntRegType to, u16 from ) { iTEST( ptr16[iAddressReg(to)], from ); } +emitterT void TEST16ItoR( x86IntRegType to, u16 from ) { xTEST( xRegister16(to), from ); } +emitterT void TEST16ItoM( uptr to, u16 from ) { xTEST( ptr16[to], from ); } +emitterT void TEST16RtoR( x86IntRegType to, x86IntRegType from ) { xTEST( xRegister16(to), xRegister16(from) ); } +emitterT void TEST16ItoRm( x86IntRegType to, u16 from ) { xTEST( ptr16[xAddressReg(to)], from ); } -emitterT void TEST8ItoR( x86IntRegType to, u8 from ) { iTEST( iRegister8(to), from ); } -emitterT void TEST8ItoM( uptr to, u8 from ) { iTEST( ptr8[to], from ); } -emitterT void TEST8RtoR( x86IntRegType to, x86IntRegType from ) { iTEST( iRegister8(to), iRegister8(from) ); } -emitterT void TEST8ItoRm( x86IntRegType to, u8 from ) { iTEST( ptr8[iAddressReg(to)], from ); } +emitterT void TEST8ItoR( x86IntRegType to, u8 from ) { xTEST( xRegister8(to), from ); } +emitterT void TEST8ItoM( uptr to, u8 from ) { xTEST( ptr8[to], from ); } +emitterT void TEST8RtoR( x86IntRegType to, x86IntRegType from ) { xTEST( xRegister8(to), xRegister8(from) ); } +emitterT void TEST8ItoRm( x86IntRegType to, u8 from ) { xTEST( ptr8[xAddressReg(to)], from ); } // mov r32 to [r32<(to), from ); + xAND( _reghlp(to), from ); } emitterT void AND32I8toM( uptr to, s8 from ) { - iAND( ptr8[to], from ); + xAND( ptr8[to], from ); } /* cmove r32 to r32*/ emitterT void CMOVE32RtoR( x86IntRegType to, x86IntRegType from ) { - iCMOVE( iRegister32(to), iRegister32(from) ); + xCMOVE( xRegister32(to), xRegister32(from) ); } // shld imm8 to r32 emitterT void SHLD32ItoR( x86IntRegType to, x86IntRegType from, u8 shift ) { - iSHLD( iRegister32(to), iRegister32(from), shift ); + xSHLD( xRegister32(to), xRegister32(from), shift ); } // shrd imm8 to r32 emitterT void SHRD32ItoR( x86IntRegType to, x86IntRegType from, u8 shift ) { - iSHRD( iRegister32(to), iRegister32(from), shift ); + xSHRD( xRegister32(to), xRegister32(from), shift ); } /* mul eax by r32 to edx:eax */ -emitterT void MUL32R( x86IntRegType from ) { iUMUL( iRegister32(from) ); } +emitterT void MUL32R( x86IntRegType from ) { xUMUL( xRegister32(from) ); } /* imul eax by r32 to edx:eax */ -emitterT void IMUL32R( x86IntRegType from ) { iMUL( iRegister32(from) ); } +emitterT void IMUL32R( x86IntRegType from ) { xMUL( xRegister32(from) ); } /* mul eax by m32 to edx:eax */ -emitterT void MUL32M( u32 from ) { iUMUL( ptr32[from] ); } +emitterT void MUL32M( u32 from ) { xUMUL( ptr32[from] ); } /* imul eax by m32 to edx:eax */ -emitterT void IMUL32M( u32 from ) { iMUL( ptr32[from] ); } +emitterT void IMUL32M( u32 from ) { xMUL( ptr32[from] ); } /* imul r32 by r32 to r32 */ emitterT void IMUL32RtoR( x86IntRegType to, x86IntRegType from ) { - iMUL( iRegister32(to), iRegister32(from) ); + xMUL( xRegister32(to), xRegister32(from) ); } /* div eax by r32 to edx:eax */ -emitterT void DIV32R( x86IntRegType from ) { iUDIV( iRegister32(from) ); } +emitterT void DIV32R( x86IntRegType from ) { xUDIV( xRegister32(from) ); } /* idiv eax by r32 to edx:eax */ -emitterT void IDIV32R( x86IntRegType from ) { iDIV( iRegister32(from) ); } +emitterT void IDIV32R( x86IntRegType from ) { xDIV( xRegister32(from) ); } /* div eax by m32 to edx:eax */ -emitterT void DIV32M( u32 from ) { iUDIV( ptr32[from] ); } +emitterT void DIV32M( u32 from ) { xUDIV( ptr32[from] ); } /* idiv eax by m32 to edx:eax */ -emitterT void IDIV32M( u32 from ) { iDIV( ptr32[from] ); } +emitterT void IDIV32M( u32 from ) { xDIV( ptr32[from] ); } emitterT void LEA32RtoR(x86IntRegType to, x86IntRegType from, s32 offset) { - iLEA( iRegister32( to ), ptr[iAddressReg(from)+offset] ); + xLEA( xRegister32( to ), ptr[xAddressReg(from)+offset] ); } emitterT void LEA32RRtoR(x86IntRegType to, x86IntRegType from0, x86IntRegType from1) { - iLEA( iRegister32( to ), ptr[iAddressReg(from0)+iAddressReg(from1)] ); + xLEA( xRegister32( to ), ptr[xAddressReg(from0)+xAddressReg(from1)] ); } // Don't inline recursive functions emitterT void LEA32RStoR(x86IntRegType to, x86IntRegType from, u32 scale) { - iLEA( iRegister32( to ), ptr[iAddressReg(from)*(1< static __forceinline bool is_s8( T imm ) { return (s8)imm == (s32)imm; } template< typename T > -static __forceinline void iWrite( T val ) +static __forceinline void xWrite( T val ) { *(T*)x86Ptr = val; x86Ptr += sizeof(T); @@ -159,7 +159,7 @@ namespace x86Emitter static const int ModRm_UseSib = 4; // same index value as ESP (used in RM field) static const int ModRm_UseDisp32 = 5; // same index value as EBP (used in Mod field) - class iAddressInfo; + class xAddressInfo; class ModSibBase; extern void iSetPtr( void* ptr ); @@ -170,12 +170,12 @@ namespace x86Emitter static __forceinline void write8( u8 val ) { - iWrite( val ); + xWrite( val ); } static __forceinline void write16( u16 val ) { - iWrite( val ); + xWrite( val ); } static __forceinline void write24( u32 val ) @@ -186,30 +186,30 @@ namespace x86Emitter static __forceinline void write32( u32 val ) { - iWrite( val ); + xWrite( val ); } static __forceinline void write64( u64 val ) { - iWrite( val ); + xWrite( val ); } ////////////////////////////////////////////////////////////////////////////////////////// - // iRegister - // Unless templating some fancy stuff, use the friendly iRegister32/16/8 typedefs instead. + // xRegister + // Unless templating some fancy stuff, use the friendly xRegister32/16/8 typedefs instead. // template< typename OperandType > - class iRegister + class xRegister { public: static const uint OperandSize = sizeof( OperandType ); - static const iRegister Empty; // defined as an empty/unused value (-1) + static const xRegister Empty; // defined as an empty/unused value (-1) int Id; - iRegister( const iRegister& src ) : Id( src.Id ) {} - iRegister(): Id( -1 ) {} - explicit iRegister( int regId ) : Id( regId ) { jASSUME( Id >= -1 && Id < 8 ); } + xRegister( const xRegister& src ) : Id( src.Id ) {} + xRegister(): Id( -1 ) {} + explicit xRegister( int regId ) : Id( regId ) { jASSUME( Id >= -1 && Id < 8 ); } bool IsEmpty() const { return Id < 0; } @@ -219,17 +219,17 @@ namespace x86Emitter // returns true if the register is a valid MMX or XMM register. bool IsSIMD() const { return OperandSize == 8 || OperandSize == 16; } - bool operator==( const iRegister& src ) const + bool operator==( const xRegister& src ) const { return (Id == src.Id); } - bool operator!=( const iRegister& src ) const + bool operator!=( const xRegister& src ) const { return (Id != src.Id); } - iRegister& operator=( const iRegister& src ) + xRegister& operator=( const xRegister& src ) { Id = src.Id; return *this; @@ -239,20 +239,20 @@ namespace x86Emitter ////////////////////////////////////////////////////////////////////////////////////////// // template< typename OperandType > - class iRegisterSIMD : public iRegister + class xRegisterSIMD : public xRegister { public: - static const iRegisterSIMD Empty; // defined as an empty/unused value (-1) + static const xRegisterSIMD Empty; // defined as an empty/unused value (-1) public: - iRegisterSIMD(): iRegister() {} - iRegisterSIMD( const iRegisterSIMD& src ) : iRegister( src.Id ) {} - iRegisterSIMD( const iRegister& src ) : iRegister( src ) {} - explicit iRegisterSIMD( int regId ) : iRegister( regId ) {} + xRegisterSIMD(): xRegister() {} + xRegisterSIMD( const xRegisterSIMD& src ) : xRegister( src.Id ) {} + xRegisterSIMD( const xRegister& src ) : xRegister( src ) {} + explicit xRegisterSIMD( int regId ) : xRegister( regId ) {} - iRegisterSIMD& operator=( const iRegisterSIMD& src ) + xRegisterSIMD& operator=( const xRegisterSIMD& src ) { - iRegister::Id = src.Id; + xRegister::Id = src.Id; return *this; } }; @@ -266,66 +266,66 @@ namespace x86Emitter // all about the the templated code in haphazard fashion. Yay.. >_< // - typedef iRegisterSIMD iRegisterSSE; - typedef iRegisterSIMD iRegisterMMX; - typedef iRegister iRegister32; - typedef iRegister iRegister16; - typedef iRegister iRegister8; + typedef xRegisterSIMD xRegisterSSE; + typedef xRegisterSIMD xRegisterMMX; + typedef xRegister xRegister32; + typedef xRegister xRegister16; + typedef xRegister xRegister8; - class iRegisterCL : public iRegister8 + class xRegisterCL : public xRegister8 { public: - iRegisterCL(): iRegister8( 1 ) {} + xRegisterCL(): xRegister8( 1 ) {} }; - extern const iRegisterSSE + extern const xRegisterSSE xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7; - extern const iRegisterMMX + extern const xRegisterMMX mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7; - extern const iRegister32 + extern const xRegister32 eax, ebx, ecx, edx, esi, edi, ebp, esp; - extern const iRegister16 + extern const xRegister16 ax, bx, cx, dx, si, di, bp, sp; - extern const iRegister8 + extern const xRegister8 al, dl, bl, ah, ch, dh, bh; - extern const iRegisterCL cl; // I'm special! + extern const xRegisterCL cl; // I'm special! ////////////////////////////////////////////////////////////////////////////////////////// // Use 32 bit registers as out index register (for ModSib memory address calculations) - // Only iAddressReg provides operators for constructing iAddressInfo types. + // Only xAddressReg provides operators for constructing xAddressInfo types. // - class iAddressReg : public iRegister32 + class xAddressReg : public xRegister32 { public: - static const iAddressReg Empty; // defined as an empty/unused value (-1) + static const xAddressReg Empty; // defined as an empty/unused value (-1) public: - iAddressReg(): iRegister32() {} - iAddressReg( const iAddressReg& src ) : iRegister32( src.Id ) {} - iAddressReg( const iRegister32& src ) : iRegister32( src ) {} - explicit iAddressReg( int regId ) : iRegister32( regId ) {} + xAddressReg(): xRegister32() {} + xAddressReg( const xAddressReg& src ) : xRegister32( src.Id ) {} + xAddressReg( const xRegister32& src ) : xRegister32( src ) {} + explicit xAddressReg( int regId ) : xRegister32( regId ) {} // Returns true if the register is the stack pointer: ESP. bool IsStackPointer() const { return Id == 4; } - iAddressInfo operator+( const iAddressReg& right ) const; - iAddressInfo operator+( const iAddressInfo& right ) const; - iAddressInfo operator+( s32 right ) const; + xAddressInfo operator+( const xAddressReg& right ) const; + xAddressInfo operator+( const xAddressInfo& right ) const; + xAddressInfo operator+( s32 right ) const; - iAddressInfo operator*( u32 factor ) const; - iAddressInfo operator<<( u32 shift ) const; + xAddressInfo operator*( u32 factor ) const; + xAddressInfo operator<<( u32 shift ) const; - iAddressReg& operator=( const iRegister32& src ) + xAddressReg& operator=( const xRegister32& src ) { Id = src.Id; return *this; @@ -334,16 +334,16 @@ namespace x86Emitter ////////////////////////////////////////////////////////////////////////////////////////// // - class iAddressInfo + class xAddressInfo { public: - iAddressReg Base; // base register (no scale) - iAddressReg Index; // index reg gets multiplied by the scale + xAddressReg Base; // base register (no scale) + xAddressReg Index; // index reg gets multiplied by the scale int Factor; // scale applied to the index register, in factor form (not a shift!) s32 Displacement; // address displacement public: - __forceinline iAddressInfo( const iAddressReg& base, const iAddressReg& index, int factor=1, s32 displacement=0 ) : + __forceinline xAddressInfo( const xAddressReg& base, const xAddressReg& index, int factor=1, s32 displacement=0 ) : Base( base ), Index( index ), Factor( factor ), @@ -351,7 +351,7 @@ namespace x86Emitter { } - __forceinline explicit iAddressInfo( const iAddressReg& index, int displacement=0 ) : + __forceinline explicit xAddressInfo( const xAddressReg& index, int displacement=0 ) : Base(), Index( index ), Factor(0), @@ -359,7 +359,7 @@ namespace x86Emitter { } - __forceinline explicit iAddressInfo( s32 displacement ) : + __forceinline explicit xAddressInfo( s32 displacement ) : Base(), Index(), Factor(0), @@ -367,24 +367,24 @@ namespace x86Emitter { } - static iAddressInfo FromIndexReg( const iAddressReg& index, int scale=0, s32 displacement=0 ); + static xAddressInfo FromIndexReg( const xAddressReg& index, int scale=0, s32 displacement=0 ); public: bool IsByteSizeDisp() const { return is_s8( Displacement ); } - __forceinline iAddressInfo& Add( s32 imm ) + __forceinline xAddressInfo& Add( s32 imm ) { Displacement += imm; return *this; } - __forceinline iAddressInfo& Add( const iAddressReg& src ); - __forceinline iAddressInfo& Add( const iAddressInfo& src ); + __forceinline xAddressInfo& Add( const xAddressReg& src ); + __forceinline xAddressInfo& Add( const xAddressInfo& src ); - __forceinline iAddressInfo operator+( const iAddressReg& right ) const { return iAddressInfo( *this ).Add( right ); } - __forceinline iAddressInfo operator+( const iAddressInfo& right ) const { return iAddressInfo( *this ).Add( right ); } - __forceinline iAddressInfo operator+( s32 imm ) const { return iAddressInfo( *this ).Add( imm ); } - __forceinline iAddressInfo operator-( s32 imm ) const { return iAddressInfo( *this ).Add( -imm ); } + __forceinline xAddressInfo operator+( const xAddressReg& right ) const { return xAddressInfo( *this ).Add( right ); } + __forceinline xAddressInfo operator+( const xAddressInfo& right ) const { return xAddressInfo( *this ).Add( right ); } + __forceinline xAddressInfo operator+( s32 imm ) const { return xAddressInfo( *this ).Add( imm ); } + __forceinline xAddressInfo operator-( s32 imm ) const { return xAddressInfo( *this ).Add( -imm ); } }; ////////////////////////////////////////////////////////////////////////////////////////// @@ -392,25 +392,25 @@ namespace x86Emitter // // This class serves two purposes: It houses 'reduced' ModRM/SIB info only, which means // that the Base, Index, Scale, and Displacement values are all in the correct arrange- - // ments, and it serves as a type-safe layer between the iRegister's operators (which - // generate iAddressInfo types) and the emitter's ModSib instruction forms. Without this, - // the iRegister would pass as a ModSib type implicitly, and that would cause ambiguity + // ments, and it serves as a type-safe layer between the xRegister's operators (which + // generate xAddressInfo types) and the emitter's ModSib instruction forms. Without this, + // the xRegister would pass as a ModSib type implicitly, and that would cause ambiguity // on a number of instructions. // - // End users should always use iAddressInfo instead. + // End users should always use xAddressInfo instead. // class ModSibBase { public: - iAddressReg Base; // base register (no scale) - iAddressReg Index; // index reg gets multiplied by the scale + xAddressReg Base; // base register (no scale) + xAddressReg Index; // index reg gets multiplied by the scale uint Scale; // scale applied to the index register, in scale/shift form s32 Displacement; // offset applied to the Base/Index registers. public: - explicit ModSibBase( const iAddressInfo& src ); + explicit ModSibBase( const xAddressInfo& src ); explicit ModSibBase( s32 disp ); - ModSibBase( iAddressReg base, iAddressReg index, int scale=0, s32 displacement=0 ); + ModSibBase( xAddressReg base, xAddressReg index, int scale=0, s32 displacement=0 ); bool IsByteSizeDisp() const { return is_s8( Displacement ); } @@ -437,9 +437,9 @@ namespace x86Emitter public: static const uint OperandSize = sizeof( OperandType ); - __forceinline explicit ModSibStrict( const iAddressInfo& src ) : ModSibBase( src ) {} + __forceinline explicit ModSibStrict( const xAddressInfo& src ) : ModSibBase( src ) {} __forceinline explicit ModSibStrict( s32 disp ) : ModSibBase( disp ) {} - __forceinline ModSibStrict( iAddressReg base, iAddressReg index, int scale=0, s32 displacement=0 ) : + __forceinline ModSibStrict( xAddressReg base, xAddressReg index, int scale=0, s32 displacement=0 ) : ModSibBase( base, index, scale, displacement ) {} __forceinline ModSibStrict& Add( s32 imm ) @@ -453,20 +453,20 @@ namespace x86Emitter }; ////////////////////////////////////////////////////////////////////////////////////////// - // iAddressIndexerBase - This is a static class which provisions our ptr[] syntax. + // xAddressIndexerBase - This is a static class which provisions our ptr[] syntax. // - struct iAddressIndexerBase + struct xAddressIndexerBase { // passthrough instruction, allows ModSib to pass silently through ptr translation // without doing anything and without compiler error. const ModSibBase& operator[]( const ModSibBase& src ) const { return src; } - __forceinline ModSibBase operator[]( iAddressReg src ) const + __forceinline ModSibBase operator[]( xAddressReg src ) const { - return ModSibBase( src, iAddressReg::Empty ); + return ModSibBase( src, xAddressReg::Empty ); } - __forceinline ModSibBase operator[]( const iAddressInfo& src ) const + __forceinline ModSibBase operator[]( const xAddressInfo& src ) const { return ModSibBase( src ); } @@ -481,7 +481,7 @@ namespace x86Emitter return ModSibBase( (uptr)src ); } - iAddressIndexerBase() {} // appease the GCC gods + xAddressIndexerBase() {} // appease the GCC gods }; ////////////////////////////////////////////////////////////////////////////////////////// @@ -489,7 +489,7 @@ namespace x86Emitter // specification of the operand size for ImmToMem operations. // template< typename OperandType > - struct iAddressIndexer + struct xAddressIndexer { static const uint OperandSize = sizeof( OperandType ); @@ -497,12 +497,12 @@ namespace x86Emitter // without doing anything and without compiler error. const ModSibStrict& operator[]( const ModSibStrict& src ) const { return src; } - __forceinline ModSibStrict operator[]( iAddressReg src ) const + __forceinline ModSibStrict operator[]( xAddressReg src ) const { - return ModSibStrict( src, iAddressReg::Empty ); + return ModSibStrict( src, xAddressReg::Empty ); } - __forceinline ModSibStrict operator[]( const iAddressInfo& src ) const + __forceinline ModSibStrict operator[]( const xAddressInfo& src ) const { return ModSibStrict( src ); } @@ -517,17 +517,17 @@ namespace x86Emitter return ModSibStrict( (uptr)src ); } - iAddressIndexer() {} // GCC initialization dummy + xAddressIndexer() {} // GCC initialization dummy }; // ptr[] - use this form for instructions which can resolve the address operand size from // the other register operand sizes. - extern const iAddressIndexerBase ptr; - extern const iAddressIndexer ptr128; - extern const iAddressIndexer ptr64; - extern const iAddressIndexer ptr32; // explicitly typed addressing, usually needed for '[dest],imm' instruction forms - extern const iAddressIndexer ptr16; // explicitly typed addressing, usually needed for '[dest],imm' instruction forms - extern const iAddressIndexer ptr8; // explicitly typed addressing, usually needed for '[dest],imm' instruction forms + extern const xAddressIndexerBase ptr; + extern const xAddressIndexer ptr128; + extern const xAddressIndexer ptr64; + extern const xAddressIndexer ptr32; // explicitly typed addressing, usually needed for '[dest],imm' instruction forms + extern const xAddressIndexer ptr16; // explicitly typed addressing, usually needed for '[dest],imm' instruction forms + extern const xAddressIndexer ptr8; // explicitly typed addressing, usually needed for '[dest],imm' instruction forms ////////////////////////////////////////////////////////////////////////////////////////// // JccComparisonType - enumerated possibilities for inspired code branching! @@ -561,26 +561,41 @@ namespace x86Emitter // Not supported yet: //E3 cb JECXZ rel8 Jump short if ECX register is 0. + ////////////////////////////////////////////////////////////////////////////////////////// + // SSE2_ComparisonType - enumerated possibilities for SIMD data comparison! + // + enum SSE2_ComparisonType + { + SSE2_Equal = 0, + SSE2_Less, + SSE2_LessOrEqual, + SSE2_Unordered, + SSE2_NotEqual, + SSE2_NotLess, + SSE2_NotLessOrEqual, + SSE2_Ordered + }; + ////////////////////////////////////////////////////////////////////////////////////////// - // iSmartJump + // xSmartJump // This class provides an interface for generating forward-based j8's or j32's "smartly" // as per the measured displacement distance. If the displacement is a valid s8, then // a j8 is inserted, else a j32. // - // Note: This class is inherently unsafe, and so it's recommended to use iForwardJump8/32 + // Note: This class is inherently unsafe, and so it's recommended to use xForwardJump8/32 // whenever it is known that the jump destination is (or is not) short. Only use - // iSmartJump in cases where it's unknown what jump encoding will be ideal. + // xSmartJump in cases where it's unknown what jump encoding will be ideal. // - // Important: Use this tool with caution! iSmartJump cannot be used in cases where jump + // Important: Use this tool with caution! xSmartJump cannot be used in cases where jump // targets overlap, since the writeback of the second target will alter the position of // the first target (which breaks the relative addressing). To assist in avoiding such - // errors, iSmartJump works based on C++ block scope, where the destruction of the - // iSmartJump object (invoked by a '}') signals the target of the jump. Example: + // errors, xSmartJump works based on C++ block scope, where the destruction of the + // xSmartJump object (invoked by a '}') signals the target of the jump. Example: // // { // iCMP( EAX, ECX ); - // iSmartJump jumpTo( Jcc_Above ); + // xSmartJump jumpTo( Jcc_Above ); // [... conditional code ...] // } // smartjump targets this spot. // @@ -593,7 +608,7 @@ namespace x86Emitter // speed benefits in the form of L1/L2 cache clutter, on any CPU. They're also notably // faster on P4's, and mildly faster on AMDs. (Core2's and i7's don't care) // - class iSmartJump : public NoncopyableObject + class xSmartJump : public NoncopyableObject { protected: u8* m_baseptr; // base address of the instruction (passed to the instruction emitter) @@ -607,12 +622,12 @@ namespace x86Emitter } JccComparisonType GetCondition() const { return m_cc; } - virtual ~iSmartJump(); + virtual ~xSmartJump(); // ------------------------------------------------------------------------ // ccType - Comparison type to be written back to the jump instruction position. // - iSmartJump( JccComparisonType ccType ) + xSmartJump( JccComparisonType ccType ) { jASSUME( ccType != Jcc_Unknown ); m_baseptr = iGetPtr(); @@ -625,12 +640,12 @@ namespace x86Emitter }; ////////////////////////////////////////////////////////////////////////////////////////// - // iForwardJump - // Primary use of this class is through the various iForwardJA8/iForwardJLE32/etc. helpers + // xForwardJump + // Primary use of this class is through the various xForwardJA8/xForwardJLE32/etc. helpers // defined later in this header. :) // template< typename OperandType > - class iForwardJump + class xForwardJump { public: static const uint OperandSize = sizeof( OperandType ); @@ -641,7 +656,7 @@ namespace x86Emitter // The jump instruction is emitted at the point of object construction. The conditional // type must be valid (Jcc_Unknown generates an assertion). - iForwardJump( JccComparisonType cctype = Jcc_Unconditional ); + xForwardJump( JccComparisonType cctype = Jcc_Unconditional ); // Sets the jump target by writing back the current x86Ptr to the jump instruction. // This method can be called multiple times, re-writing the jump instruction's target @@ -656,8 +671,8 @@ namespace x86Emitter extern void ModRM( uint mod, uint reg, uint rm ); extern void ModRM_Direct( uint reg, uint rm ); extern void SibSB( u32 ss, u32 index, u32 base ); - extern void iWriteDisp( int regfield, s32 displacement ); - extern void iWriteDisp( int regfield, const void* address ); + extern void xWriteDisp( int regfield, s32 displacement ); + extern void xWriteDisp( int regfield, const void* address ); extern void EmitSibMagic( uint regfield, const ModSibBase& info );