mirror of https://github.com/PCSX2/pcsx2.git
Merge bfb8351e73
into de9d08075e
This commit is contained in:
commit
17b365785a
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@ -3755,6 +3755,8 @@ SCED-52759:
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region: "PAL-M5"
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clampModes:
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vuClampMode: 0 # Resolves I Reg Clamping / performance impact and yellow graphics in certain areas.
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gameFixes:
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- IbitHack # Reduces VU recompilation.
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gsHWFixes:
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halfPixelOffset: 4 # Fixes post positioning.
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nativeScaling: 2 # Fixes post effects.
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@ -3784,6 +3786,8 @@ SCED-52846:
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region: "PAL-E"
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clampModes:
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vuClampMode: 0 # Resolves I Reg Clamping / performance impact and yellow graphics in certain areas.
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gameFixes:
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- IbitHack # Reduces VU recompilation.
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gsHWFixes:
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halfPixelOffset: 4 # Fixes post positioning.
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nativeScaling: 2 # Fixes post effects.
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@ -3855,6 +3859,8 @@ SCED-52899:
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region: "PAL-M5"
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clampModes:
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vuClampMode: 0 # Resolves I Reg Clamping / performance impact and yellow graphics in certain areas.
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gameFixes:
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- IbitHack # Reduces VU recompilation.
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gsHWFixes:
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halfPixelOffset: 4 # Fixes post positioning.
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nativeScaling: 2 # Fixes post effects.
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@ -5358,6 +5364,8 @@ SCES-52004:
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compat: 5
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clampModes:
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vuClampMode: 0 # Resolves I Reg Clamping / performance impact and yellow graphics in certain areas.
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gameFixes:
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- IbitHack # Reduces VU recompilation.
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gsHWFixes:
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halfPixelOffset: 4 # Fixes post positioning.
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nativeScaling: 2 # Fixes post effects.
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@ -5690,6 +5698,8 @@ SCES-52893:
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region: "PAL-E-GR-R"
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clampModes:
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vuClampMode: 0 # Resolves I Reg Clamping / performance impact and yellow graphics in certain areas.
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gameFixes:
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- IbitHack # Reduces VU recompilation.
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gsHWFixes:
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halfPixelOffset: 4 # Fixes post positioning.
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nativeScaling: 2 # Fixes post effects.
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@ -7203,6 +7213,8 @@ SCKA-20048:
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region: "NTSC-K"
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clampModes:
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vuClampMode: 0 # Resolves I Reg Clamping / performance impact and yellow graphics in certain areas.
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gameFixes:
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- IbitHack # Reduces VU recompilation.
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gsHWFixes:
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halfPixelOffset: 4 # Fixes post positioning.
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nativeScaling: 2 # Fixes post effects.
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@ -7415,6 +7427,8 @@ SCKA-20078:
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region: "NTSC-K"
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clampModes:
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vuClampMode: 0 # Resolves I Reg Clamping / performance impact and yellow graphics in certain areas.
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gameFixes:
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- IbitHack # Reduces VU recompilation.
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gsHWFixes:
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halfPixelOffset: 4 # Fixes post positioning.
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nativeScaling: 2 # Fixes post effects.
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@ -11537,6 +11551,8 @@ SCUS-97402:
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compat: 5
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clampModes:
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vuClampMode: 0 # Resolves I Reg Clamping / performance impact and yellow graphics in certain areas.
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gameFixes:
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- IbitHack # Reduces VU recompilation.
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gsHWFixes:
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halfPixelOffset: 4 # Fixes post positioning.
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nativeScaling: 2 # Fixes post effects.
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@ -11677,6 +11693,8 @@ SCUS-97431:
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region: "NTSC-U"
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clampModes:
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vuClampMode: 0 # Resolves I Reg Clamping / performance impact and yellow graphics in certain areas.
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gameFixes:
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- IbitHack # Reduces VU recompilation.
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gsHWFixes:
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halfPixelOffset: 4 # Fixes post positioning.
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nativeScaling: 2 # Fixes post effects.
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@ -11685,6 +11703,8 @@ SCUS-97432:
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region: "NTSC-U"
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clampModes:
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vuClampMode: 0 # Resolves I Reg Clamping / performance impact and yellow graphics in certain areas.
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gameFixes:
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- IbitHack # Reduces VU recompilation.
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gsHWFixes:
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halfPixelOffset: 4 # Fixes post positioning.
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nativeScaling: 2 # Fixes post effects.
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@ -12128,6 +12148,8 @@ SCUS-97517:
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region: "NTSC-U"
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clampModes:
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vuClampMode: 0 # Resolves I Reg Clamping / performance impact and yellow graphics in certain areas.
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gameFixes:
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- IbitHack # Reduces VU recompilation.
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gsHWFixes:
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halfPixelOffset: 4 # Fixes post positioning.
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nativeScaling: 2 # Fixes post effects.
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@ -13316,6 +13338,8 @@ SLED-52899:
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region: "PAL-M5"
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clampModes:
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vuClampMode: 0 # Resolves I Reg Clamping / performance impact and yellow graphics in certain areas.
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gameFixes:
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- IbitHack # Reduces VU recompilation.
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gsHWFixes:
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halfPixelOffset: 4 # Fixes post positioning.
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nativeScaling: 2 # Fixes post effects.
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@ -18441,6 +18465,8 @@ SLES-51981:
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region: "PAL-E"
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clampModes:
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vuClampMode: 0 # Resolves I Reg Clamping / performance impact and yellow graphics in certain areas.
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gameFixes:
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- IbitHack # Reduces VU recompilation.
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gsHWFixes:
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roundSprite: 1 # Fixes slight blur.
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SLES-51982:
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@ -18448,6 +18474,8 @@ SLES-51982:
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region: "PAL-M3"
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clampModes:
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vuClampMode: 0 # Resolves I Reg Clamping / performance impact and yellow graphics in certain areas.
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gameFixes:
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- IbitHack # Reduces VU recompilation.
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gsHWFixes:
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roundSprite: 1 # Fixes slight blur.
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SLES-51986:
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@ -45399,6 +45427,8 @@ SLPM-66151:
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region: "NTSC-J"
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clampModes:
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vuClampMode: 0 # Resolves I Reg Clamping / performance impact and yellow graphics in certain areas.
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gameFixes:
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- IbitHack # Reduces VU recompilation.
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gsHWFixes:
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halfPixelOffset: 4 # Fixes post positioning.
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nativeScaling: 2 # Fixes post effects.
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@ -65100,6 +65130,8 @@ SLUS-20828:
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compat: 5
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clampModes:
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vuClampMode: 0 # Resolves I Reg Clamping / performance impact and yellow graphics in certain areas.
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gameFixes:
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- IbitHack # Reduces VU recompilation.
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gsHWFixes:
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roundSprite: 1 # Fixes slight blur.
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SLUS-20830:
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@ -72595,6 +72627,8 @@ TCES-52004:
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region: "PAL-E"
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clampModes:
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vuClampMode: 0 # Resolves I Reg Clamping / performance impact and yellow graphics in certain areas.
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gameFixes:
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- IbitHack # Reduces VU recompilation.
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gsHWFixes:
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halfPixelOffset: 4 # Fixes post positioning.
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nativeScaling: 2 # Fixes post effects.
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@ -228,7 +228,7 @@ __fi void mVUanalyzeIALU2(mV, int Is, int It)
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__fi void mVUanalyzeIADDI(mV, int Is, int It, s16 imm)
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{
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mVUanalyzeIALU2(mVU, Is, It);
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if (!Is)
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if (!Is && !EmuConfig.Gamefixes.IbitHack)
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{
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setConstReg(It, imm);
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}
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@ -742,12 +742,27 @@ void* mVUcompile(microVU& mVU, u32 startPC, uptr pState)
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{
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mVUsetupRange(mVU, xPC, false);
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if (branch < 2)
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mVUsetupRange(mVU, xPC + 8, true); // Ideally we'd do +4 but the mmx compare only works in 64bits, this should be fine
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mVUsetupRange(mVU, xPC + 4, true);
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}
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}
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else
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{
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incPC(-1);
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if (EmuConfig.Gamefixes.IbitHack)
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{
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// Ignore IADDI, IADDIU and ISUBU, ILW, ISW, LQ, SQ.
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// Be warned, this is a little risky as we could be ignoring subtle differences in the operations.
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// 2 is too much, 1 is too little, so it gets 2. It's a hack anyways...
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const u32 upper = (mVU.code >> 25);
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if (upper == 0x1 || upper == 0x0 || upper == 0x4 || upper == 0x5 || upper == 0x8 || upper == 0x9 || (upper == 0x40 && (mVU.code & 0x3F) == 0x32))
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{
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incPC(1);
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mVUsetupRange(mVU, xPC, false);
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if (branch < 2)
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mVUsetupRange(mVU, xPC + 2, true);
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incPC(-1);
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}
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}
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mVUopL(mVU, 0);
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incPC(1);
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}
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@ -858,17 +858,37 @@ mVUop(mVU_IADDI)
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if (_Is_ == 0)
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{
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const xRegister32& regT = mVU.regAlloc->allocGPR(-1, _It_, mVUlow.backupVI);
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if (_Imm5_ != 0)
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xMOV(regT, _Imm5_);
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if (!EmuConfig.Gamefixes.IbitHack)
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{
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if (_Imm5_ != 0)
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xMOV(regT, _Imm5_);
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else
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xXOR(regT, regT);
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}
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else
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xXOR(regT, regT);
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{
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xMOV(regT, ptr32[&curI]);
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xSHL(regT, 21);
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xSAR(regT, 27);
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}
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mVU.regAlloc->clearNeeded(regT);
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}
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else
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{
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const xRegister32& regS = mVU.regAlloc->allocGPR(_Is_, _It_, mVUlow.backupVI);
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if (_Imm5_ != 0)
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xADD(regS, _Imm5_);
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if (!EmuConfig.Gamefixes.IbitHack)
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{
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if (_Imm5_ != 0)
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xADD(regS, _Imm5_);
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}
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else
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{
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xMOV(gprT1, ptr32[&curI]);
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xSHL(gprT1, 21);
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xSAR(gprT1, 27);
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xADD(regS, gprT1);
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}
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mVU.regAlloc->clearNeeded(regS);
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}
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mVU.profiler.EmitOp(opIADDI);
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@ -884,17 +904,43 @@ mVUop(mVU_IADDIU)
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if (_Is_ == 0)
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{
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const xRegister32& regT = mVU.regAlloc->allocGPR(-1, _It_, mVUlow.backupVI);
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if (_Imm15_ != 0)
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xMOV(regT, _Imm15_);
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if (!EmuConfig.Gamefixes.IbitHack)
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{
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if (_Imm15_ != 0)
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xMOV(regT, _Imm15_);
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else
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xXOR(regT, regT);
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}
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else
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xXOR(regT, regT);
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{
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xMOV(regT, ptr32[&curI]);
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xMOV(gprT1, regT);
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xSHR(gprT1, 10);
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xAND(gprT1, 0x7800);
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xAND(regT, 0x7FF);
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xOR(regT, gprT1);
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}
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mVU.regAlloc->clearNeeded(regT);
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}
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else
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{
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const xRegister32& regS = mVU.regAlloc->allocGPR(_Is_, _It_, mVUlow.backupVI);
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if (_Imm15_ != 0)
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xADD(regS, _Imm15_);
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if (!EmuConfig.Gamefixes.IbitHack)
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{
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if (_Imm15_ != 0)
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xADD(regS, _Imm15_);
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}
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else
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{
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xMOV(gprT1, ptr32[&curI]);
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xMOV(gprT2, gprT1);
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xSHR(gprT2, 10);
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xAND(gprT2, 0x7800);
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xAND(gprT1, 0x7FF);
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xOR(gprT1, gprT2);
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xADD(regS, gprT1);
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}
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mVU.regAlloc->clearNeeded(regS);
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}
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mVU.profiler.EmitOp(opIADDIU);
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|
@ -964,8 +1010,22 @@ mVUop(mVU_ISUBIU)
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pass2
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{
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const xRegister32& regS = mVU.regAlloc->allocGPR(_Is_, _It_, mVUlow.backupVI);
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if (_Imm15_ != 0)
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xSUB(regS, _Imm15_);
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if (!EmuConfig.Gamefixes.IbitHack)
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{
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if (_Imm15_ != 0)
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xSUB(regS, _Imm15_);
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}
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else
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{
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xMOV(gprT1, ptr32[&curI]);
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xMOV(gprT2, gprT1);
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xSHR(gprT2, 10);
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xAND(gprT2, 0x7800);
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xAND(gprT1, 0x7FF);
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xOR(gprT1, gprT2);
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xSUB(regS, gprT1);
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}
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mVU.regAlloc->clearNeeded(regS);
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mVU.profiler.EmitOp(opISUBIU);
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}
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|
@ -1100,12 +1160,23 @@ mVUop(mVU_ILW)
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pass2
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{
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void* ptr = mVU.regs().Mem + offsetSS;
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std::optional<xAddressVoid> optaddr(mVUoptimizeConstantAddr(mVU, _Is_, _Imm11_, offsetSS));
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std::optional<xAddressVoid> optaddr(EmuConfig.Gamefixes.IbitHack ? std::nullopt : mVUoptimizeConstantAddr(mVU, _Is_, _Imm11_, offsetSS));
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if (!optaddr.has_value())
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{
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mVU.regAlloc->moveVIToGPR(gprT1, _Is_);
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if (_Imm11_ != 0)
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xADD(gprT1, _Imm11_);
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if (!EmuConfig.Gamefixes.IbitHack)
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{
|
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if (_Imm11_ != 0)
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xADD(gprT1, _Imm11_);
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}
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else
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{
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xMOV(gprT2, ptr32[&curI]);
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xSHL(gprT2, 21);
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xSAR(gprT2, 21);
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xADD(gprT1, gprT2);
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}
|
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mVUaddrFix(mVU, gprT1q);
|
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}
|
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|
@ -1164,12 +1235,23 @@ mVUop(mVU_ISW)
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|||
}
|
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pass2
|
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{
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||||
std::optional<xAddressVoid> optaddr(mVUoptimizeConstantAddr(mVU, _Is_, _Imm11_, 0));
|
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std::optional<xAddressVoid> optaddr(EmuConfig.Gamefixes.IbitHack ? std::nullopt : mVUoptimizeConstantAddr(mVU, _Is_, _Imm11_, 0));
|
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if (!optaddr.has_value())
|
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{
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mVU.regAlloc->moveVIToGPR(gprT1, _Is_);
|
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if (_Imm11_ != 0)
|
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xADD(gprT1, _Imm11_);
|
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if (!EmuConfig.Gamefixes.IbitHack)
|
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{
|
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if (_Imm11_ != 0)
|
||||
xADD(gprT1, _Imm11_);
|
||||
}
|
||||
else
|
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{
|
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xMOV(gprT2, ptr32[&curI]);
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xSHL(gprT2, 21);
|
||||
xSAR(gprT2, 21);
|
||||
|
||||
xADD(gprT1, gprT2);
|
||||
}
|
||||
mVUaddrFix(mVU, gprT1q);
|
||||
}
|
||||
|
||||
|
@ -1251,12 +1333,23 @@ mVUop(mVU_LQ)
|
|||
pass1 { mVUanalyzeLQ(mVU, _Ft_, _Is_, false); }
|
||||
pass2
|
||||
{
|
||||
const std::optional<xAddressVoid> optaddr(mVUoptimizeConstantAddr(mVU, _Is_, _Imm11_, 0));
|
||||
const std::optional<xAddressVoid> optaddr(EmuConfig.Gamefixes.IbitHack ? std::nullopt : mVUoptimizeConstantAddr(mVU, _Is_, _Imm11_, 0));
|
||||
if (!optaddr.has_value())
|
||||
{
|
||||
mVU.regAlloc->moveVIToGPR(gprT1, _Is_);
|
||||
if (_Imm11_ != 0)
|
||||
xADD(gprT1, _Imm11_);
|
||||
if (!EmuConfig.Gamefixes.IbitHack)
|
||||
{
|
||||
if (_Imm11_ != 0)
|
||||
xADD(gprT1, _Imm11_);
|
||||
}
|
||||
else
|
||||
{
|
||||
xMOV(gprT2, ptr32[&curI]);
|
||||
xSHL(gprT2, 21);
|
||||
xSAR(gprT2, 21);
|
||||
|
||||
xADD(gprT1, gprT2);
|
||||
}
|
||||
mVUaddrFix(mVU, gprT1q);
|
||||
}
|
||||
|
||||
|
@ -1345,12 +1438,23 @@ mVUop(mVU_SQ)
|
|||
pass1 { mVUanalyzeSQ(mVU, _Fs_, _It_, false); }
|
||||
pass2
|
||||
{
|
||||
const std::optional<xAddressVoid> optptr(mVUoptimizeConstantAddr(mVU, _It_, _Imm11_, 0));
|
||||
const std::optional<xAddressVoid> optptr(EmuConfig.Gamefixes.IbitHack ? std::nullopt : mVUoptimizeConstantAddr(mVU, _It_, _Imm11_, 0));
|
||||
if (!optptr.has_value())
|
||||
{
|
||||
mVU.regAlloc->moveVIToGPR(gprT1, _It_);
|
||||
if (_Imm11_ != 0)
|
||||
xADD(gprT1, _Imm11_);
|
||||
if (!EmuConfig.Gamefixes.IbitHack)
|
||||
{
|
||||
if (_Imm11_ != 0)
|
||||
xADD(gprT1, _Imm11_);
|
||||
}
|
||||
else
|
||||
{
|
||||
xMOV(gprT2, ptr32[&curI]);
|
||||
xSHL(gprT2, 21);
|
||||
xSAR(gprT2, 21);
|
||||
|
||||
xADD(gprT1, gprT2);
|
||||
}
|
||||
mVUaddrFix(mVU, gprT1q);
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in New Issue