mirror of https://github.com/PCSX2/pcsx2.git
EE Cache: Shrink tag size by 4 bytes
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@ -23,10 +23,11 @@ namespace
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// When this happens, the cache still fills with the data and when it gets evicted the data is lost.
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// When this happens, the cache still fills with the data and when it gets evicted the data is lost.
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// We don't emulate memory access on a logic level, so we need to ensure that we don't try to load/store to a non-existant physical address.
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// We don't emulate memory access on a logic level, so we need to ensure that we don't try to load/store to a non-existant physical address.
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// This fixes the Find My Own Way demo.
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// This fixes the Find My Own Way demo.
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bool validPFN = true;
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// The lower parts of a cache tags structure is as follows:
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// The lower parts of a cache tags structure is as follows:
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// 31 - 12: The physical address cache tag.
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// 31 - 12: The physical address cache tag.
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// 11 - 7: Unused.
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// 11: Used by PCSX2 to indicate if the physical address is valid.
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// 10 - 7: Unused.
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// 6: Dirty flag.
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// 6: Dirty flag.
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// 5: Valid flag.
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// 5: Valid flag.
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// 4: LRF flag - least recently filled flag.
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// 4: LRF flag - least recently filled flag.
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@ -39,7 +40,8 @@ namespace
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VALID_FLAG = 0x20,
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VALID_FLAG = 0x20,
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LRF_FLAG = 0x10,
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LRF_FLAG = 0x10,
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LOCK_FLAG = 0x8,
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LOCK_FLAG = 0x8,
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ALL_FLAGS = 0xFFF
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ALL_FLAGS = 0x7FF,
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ALL_BITS = 0xFFF
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};
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};
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int flags() const
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int flags() const
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@ -65,23 +67,36 @@ namespace
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void clearLocked() { rawValue &= ~LOCK_FLAG; }
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void clearLocked() { rawValue &= ~LOCK_FLAG; }
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void toggleLRF() { rawValue ^= LRF_FLAG; }
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void toggleLRF() { rawValue ^= LRF_FLAG; }
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uptr addr() const { return rawValue & ~ALL_FLAGS; }
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uptr addr() const { return rawValue & ~ALL_BITS; }
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void setAddr(uptr addr)
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void setAddr(uptr addr)
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{
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{
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rawValue &= ALL_FLAGS;
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rawValue &= ALL_BITS;
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rawValue |= (addr & ~ALL_FLAGS);
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rawValue |= (addr & ~ALL_BITS);
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}
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}
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bool matches(uptr other) const
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bool matches(uptr other) const
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{
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{
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return isValid() && addr() == (other & ~ALL_FLAGS);
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return isValid() && addr() == (other & ~ALL_BITS);
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}
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}
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void clear()
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void clear()
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{
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{
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rawValue &= LRF_FLAG;
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rawValue &= LRF_FLAG;
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}
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}
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constexpr bool isValidPFN() const
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{
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return rawValue & 0x800;
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}
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constexpr void setValidPFN(bool valid)
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{
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if (valid)
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rawValue |= 0x800;
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else
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rawValue &= ~0x800;
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}
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};
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};
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struct CacheLine
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struct CacheLine
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@ -103,7 +118,7 @@ namespace
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uptr target = addr();
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uptr target = addr();
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CACHE_LOG("Write back at %zx", target);
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CACHE_LOG("Write back at %zx", target);
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if (tag.validPFN)
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if (tag.isValidPFN())
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*reinterpret_cast<CacheData*>(target) = data;
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*reinterpret_cast<CacheData*>(target) = data;
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tag.clearDirty();
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tag.clearDirty();
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}
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}
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@ -113,7 +128,7 @@ namespace
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pxAssertMsg(!tag.isDirtyAndValid(), "Loaded a value into cache without writing back the old one!");
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pxAssertMsg(!tag.isDirtyAndValid(), "Loaded a value into cache without writing back the old one!");
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tag.setAddr(ppf);
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tag.setAddr(ppf);
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if (!tag.validPFN)
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if (!tag.isValidPFN())
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{
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{
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// Reading from invalid physical addresses seems to return 0 on hardware
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// Reading from invalid physical addresses seems to return 0 on hardware
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std::memset(&data, 0, sizeof(data));
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std::memset(&data, 0, sizeof(data));
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@ -238,7 +253,7 @@ static int getFreeCache(u32 mem, int* way, bool validPFN)
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CacheLine line = cache.lineAt(setIdx, newWay);
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CacheLine line = cache.lineAt(setIdx, newWay);
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line.writeBackIfNeeded();
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line.writeBackIfNeeded();
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line.tag.validPFN = validPFN;
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line.tag.setValidPFN(validPFN);
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line.load(ppf);
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line.load(ppf);
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line.tag.toggleLRF();
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line.tag.toggleLRF();
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}
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}
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