diff --git a/pcsx2/FiFo.cpp b/pcsx2/FiFo.cpp index 92756317d5..2b0a022404 100644 --- a/pcsx2/FiFo.cpp +++ b/pcsx2/FiFo.cpp @@ -53,7 +53,7 @@ extern int FOreadpos; void __fastcall ReadFIFO_page_4(u32 mem, u64 *out) { - jASSUME( (mem >= 0x10004000) && (mem < 0x10005000) ); + jASSUME( (mem >= VIF0_FIFO) && (mem < VIF1_FIFO) ); VIF_LOG("ReadFIFO/VIF0 0x%08X", mem); //out[0] = psHu64(mem ); @@ -65,7 +65,7 @@ void __fastcall ReadFIFO_page_4(u32 mem, u64 *out) void __fastcall ReadFIFO_page_5(u32 mem, u64 *out) { - jASSUME( (mem >= 0x10005000) && (mem < 0x10006000) ); + jASSUME( (mem >= VIF1_FIFO) && (mem < GIF_FIFO) ); VIF_LOG("ReadFIFO/VIF1, addr=0x%08X", mem); @@ -87,7 +87,7 @@ void __fastcall ReadFIFO_page_5(u32 mem, u64 *out) void __fastcall ReadFIFO_page_6(u32 mem, u64 *out) { - jASSUME( (mem >= 0x10006000) && (mem < 0x10007000) ); + jASSUME( (mem >= GIF_FIFO) && (mem < IPUout_FIFO) ); DevCon::Notice( "ReadFIFO/GIF, addr=0x%x", params mem ); @@ -100,7 +100,7 @@ void __fastcall ReadFIFO_page_6(u32 mem, u64 *out) void __fastcall ReadFIFO_page_7(u32 mem, u64 *out) { - jASSUME( (mem >= 0x10007000) && (mem < 0x10008000) ); + jASSUME( (mem >= IPUout_FIFO) && (mem < D0_CHCR) ); // All addresses in this page map to 0x7000 and 0x7010: mem &= 0x10; @@ -125,7 +125,7 @@ void __fastcall ReadFIFO_page_7(u32 mem, u64 *out) void __fastcall WriteFIFO_page_4(u32 mem, const mem128_t *value) { - jASSUME( (mem >= 0x10004000) && (mem < 0x10005000) ); + jASSUME( (mem >= VIF0_FIFO) && (mem < VIF1_FIFO) ); VIF_LOG("WriteFIFO/VIF0, addr=0x%08X", mem); @@ -142,7 +142,7 @@ void __fastcall WriteFIFO_page_4(u32 mem, const mem128_t *value) void __fastcall WriteFIFO_page_5(u32 mem, const mem128_t *value) { - jASSUME( (mem >= 0x10005000) && (mem < 0x10006000) ); + jASSUME( (mem >= VIF1_FIFO) && (mem < GIF_FIFO) ); VIF_LOG("WriteFIFO/VIF1, addr=0x%08X", mem); @@ -164,7 +164,7 @@ void __fastcall WriteFIFO_page_5(u32 mem, const mem128_t *value) void __fastcall WriteFIFO_page_6(u32 mem, const mem128_t *value) { - jASSUME( (mem >= 0x10006000) && (mem < 0x10007000) ); + jASSUME( (mem >= GIF_FIFO) && (mem < IPUout_FIFO) ); GIF_LOG("WriteFIFO/GIF, addr=0x%08X", mem); //psHu64(mem ) = value[0]; @@ -192,7 +192,7 @@ void __fastcall WriteFIFO_page_6(u32 mem, const mem128_t *value) void __fastcall WriteFIFO_page_7(u32 mem, const mem128_t *value) { - jASSUME( (mem >= 0x10007000) && (mem < 0x10008000) ); + jASSUME( (mem >= IPUout_FIFO) && (mem < D0_CHCR) ); // All addresses in this page map to 0x7000 and 0x7010: mem &= 0x10; diff --git a/pcsx2/Hw.h b/pcsx2/Hw.h index 480a22ef37..0b0dc0cb0e 100644 --- a/pcsx2/Hw.h +++ b/pcsx2/Hw.h @@ -99,6 +99,55 @@ enum HWaddress GIF_CNT = 0x10003080, GIF_P3CNT = 0x10003090, GIF_P3TAG = 0x100030A0, + + // Vif Memory Locations + VIF0_STAT = 0x10003800, + VIF0_FBRST = 0x10003810, + VIF0_ERR = 0x10003820, + VIF0_MARK = 0x10003830, + VIF0_CYCLE = 0x10003840, + VIF0_MODE = 0x10003850, + VIF0_NUM = 0x10003860, + VIF0_MASK = 0x10003870, + VIF0_CODE = 0x10003880, + VIF0_ITOPS = 0x10003890, + VIF0_ITOP = 0x100038d0, + VIF0_TOP = 0x100038e0, + VIF0_R0 = 0x10003900, + VIF0_R1 = 0x10003910, + VIF0_R2 = 0x10003920, + VIF0_R3 = 0x10003930, + VIF0_C0 = 0x10003940, + VIF0_C1 = 0x10003950, + VIF0_C2 = 0x10003960, + VIF0_C3 = 0x10003970, + + VIF1_STAT = 0x10003c00, + VIF1_FBRST = 0x10003c10, + VIF1_ERR = 0x10003c20, + VIF1_MARK = 0x10003c30, + VIF1_CYCLE = 0x10003c40, + VIF1_MODE = 0x10003c50, + VIF1_NUM = 0x10003c60, + VIF1_MASK = 0x10003c70, + VIF1_CODE = 0x10003c80, + VIF1_ITOPS = 0x10003c90, + VIF1_BASE = 0x10003ca0, + VIF1_OFST = 0x10003cb0, + VIF1_TOPS = 0x10003cc0, + VIF1_ITOP = 0x10003cd0, + VIF1_TOP = 0x10003ce0, + VIF1_R0 = 0x10003d00, + VIF1_R1 = 0x10003d10, + VIF1_R2 = 0x10003d20, + VIF1_R3 = 0x10003d30, + VIF1_C0 = 0x10003d40, + VIF1_C1 = 0x10003d50, + VIF1_C2 = 0x10003d60, + VIF1_C3 = 0x10003d70, + + VIF0_FIFO = 0x10004000, + VIF1_FIFO = 0x10005000, GIF_FIFO = 0x10006000, IPUout_FIFO = 0x10007000, @@ -150,6 +199,7 @@ enum HWaddress D6_CHCR = 0x1000C400, D6_MADR = 0x1000C410, D6_QWC = 0x1000C420, + D6_TADR = 0x1000C430, //SIF2 D7_CHCR = 0x1000C800, @@ -161,6 +211,7 @@ enum HWaddress D8_MADR = 0x1000D010, D8_QWC = 0x1000D020, D8_SADR = 0x1000D080, + SPR1_CHCR = 0x1000D400, DMAC_CTRL = 0x1000E000, DMAC_STAT = 0x1000E010, @@ -173,10 +224,26 @@ enum HWaddress INTC_STAT = 0x1000F000, INTC_MASK = 0x1000F010, - SBUS_F220 = 0x1000F220, - SBUS_SMFLG = 0x1000F230, + SIO_LCR = 0x1000F100, + SIO_LSR = 0x1000F110, + SIO_IER = 0x1000F120, + SIO_ISR = 0x1000F130,// + SIO_FCR = 0x1000F140, + SIO_BGR = 0x1000F150, + SIO_TXFIFO = 0x1000F180, + SIO_RXFIFO = 0x1000F1C0, + + SBUS_F200 = 0x1000F200, //MSCOM + SBUS_F210 = 0x1000F210, //SMCOM + SBUS_F220 = 0x1000F220, //MSFLG + SBUS_F230 = 0x1000F230, //SMFLG SBUS_F240 = 0x1000F240, + SBUS_F250 = 0x1000F250, + SBUS_F260 = 0x1000F260, + MCH_RICM = 0x1000F430, + MCH_DRD = 0x1000F440, + DMAC_ENABLER = 0x1000F520, DMAC_ENABLEW = 0x1000F590, diff --git a/pcsx2/HwRead.cpp b/pcsx2/HwRead.cpp index 60a9eb6ab5..d1ca5c3b67 100644 --- a/pcsx2/HwRead.cpp +++ b/pcsx2/HwRead.cpp @@ -56,7 +56,7 @@ __forceinline mem8_t hwRead8(u32 mem) { u8 ret; - if( mem >= 0x10002000 && mem < 0x10008000 ) + if( mem >= IPU_CMD && mem < D0_CHCR ) DevCon::Notice("Unexpected hwRead8 from 0x%x", params mem); switch (mem) @@ -95,14 +95,23 @@ __forceinline mem8_t hwRead8(u32 mem) case 0x10001821: ret = (u8)(counters[3].target>>8); break; default: - if ((mem & 0xffffff0f) == 0x1000f200) + if ((mem & 0xffffff0f) == SBUS_F200) { - if(mem == 0x1000f260) ret = 0; - else if(mem == SBUS_F240) { - ret = psHu32(mem); - //psHu32(mem) &= ~0x4000; + switch (mem) + { + case SBUS_F240: + ret = psHu32(mem); + //psHu32(mem) &= ~0x4000; + break; + + case SBUS_F260: + ret = 0; + break; + + default: + ret = psHu32(mem); + break; } - else ret = psHu32(mem); return (u8)ret; } @@ -145,15 +154,23 @@ __forceinline mem16_t hwRead16(u32 mem) case RCNT3_TARGET: ret = (u16)counters[3].target; break; default: - if ((mem & 0xffffff0f) == 0x1000f200) + if ((mem & 0xffffff0f) == SBUS_F200) { - if(mem == 0x1000f260) ret = 0; - else if(mem == SBUS_F240) { - ret = psHu16(mem) | 0x0102; - psHu32(mem) &= ~0x4000; + switch (mem) + { + case SBUS_F240: + ret = psHu16(mem) | 0x0102; + psHu32(mem) &= ~0x4000; // not commented out like in bit mode? + break; + + case SBUS_F260: + ret = 0; + break; + + default: + ret = psHu32(mem); + break; } - else - ret = psHu32(mem); return (u16)ret; } ret = psHu16(mem); @@ -231,16 +248,16 @@ static __forceinline mem32_t __hwRead32_page_0F( u32 mem, bool intchack ) HW_LOG("INTC_MASK Read32, value=0x%x", psHu32(INTC_MASK)); break; - case 0xf130: // 0x1000f130 - case 0xf260: // 0x1000f260 SBUS? + case 0xf130: // SIO_ISR + case 0xf260: // SBUS_F260 case 0xf410: // 0x1000f410 case 0xf430: // MCH_RICM return 0; - case 0xf240: // 0x1000f240: SBUS + case 0xf240: // SBUS_F240 return psHu32(0xf240) | 0xF0000102; - case 0xf440: // 0x1000f440: MCH_DRD + case 0xf440: // MCH_DRD if( !((psHu32(0xf430) >> 6) & 0xF) ) { @@ -362,7 +379,7 @@ void __fastcall hwRead64_page_02(u32 mem, mem64_t* result ) void __fastcall hwRead64_generic_INTC_HACK(u32 mem, mem64_t* result ) { - if( mem == INTC_STAT ) IntCHackCheck(); + if (mem == INTC_STAT) IntCHackCheck(); *result = psHu64(mem); HW_LOG("Unknown Hardware Read 64 at %x",mem); diff --git a/pcsx2/HwWrite.cpp b/pcsx2/HwWrite.cpp index 88ff3cba91..f715b4e67b 100644 --- a/pcsx2/HwWrite.cpp +++ b/pcsx2/HwWrite.cpp @@ -43,7 +43,8 @@ static __forceinline void DmaExec8( void (*func)(), u32 mem, u8 value ) u32 qwcRegister = (mem | 0x20) & ~0x1; //Need to remove the lower bit else we end up clearing TADR //Its invalid for the hardware to write a DMA while it is active, not without Suspending the DMAC - if((value & 0x1) && (psHu8(mem) & 0x1) == 0x1 && (psHu32(DMAC_CTRL) & 0x1) == 1) { + if ((value & 0x1) && ((psHu8(mem) & 0x1) == 0x1) && ((psHu32(DMAC_CTRL) & 0x1) == 1)) + { DMA_LOG( "DMAExec8 Attempt to run DMA while one is already active mem = %x", mem ); } @@ -69,7 +70,8 @@ static __forceinline void DmaExec16( void (*func)(), u32 mem, u16 value ) u32 qwcRegister = mem | 0x20; //Its invalid for the hardware to write a DMA while it is active, not without Suspending the DMAC - if((value & 0x100) && (psHu32(mem) & 0x100) == 0x100 && (psHu32(DMAC_CTRL) & 0x1) == 1) { + if ((value & 0x100) && ((psHu32(mem) & 0x100) == 0x100) && ((psHu32(DMAC_CTRL) & 0x1) == 1)) + { DMA_LOG( "DMAExec16 Attempt to run DMA while one is already active mem = %x", mem); } @@ -95,7 +97,8 @@ static void DmaExec( void (*func)(), u32 mem, u32 value ) u32 qwcRegister = mem | 0x20; //Its invalid for the hardware to write a DMA while it is active, not without Suspending the DMAC - if((value & 0x100) && (psHu32(mem) & 0x100) == 0x100 && (psHu32(DMAC_CTRL) & 0x1) == 1) { + if ((value & 0x100) && ((psHu32(mem) & 0x100) == 0x100) && ((psHu32(DMAC_CTRL) & 0x1) == 1)) + { DMA_LOG( "DMAExec32 Attempt to run DMA while one is already active mem = %x", mem ); return; } @@ -110,8 +113,8 @@ static void DmaExec( void (*func)(), u32 mem, u32 value ) } /* Keep the old tag if in chain mode and hw doesnt set it*/ - if( (value & 0xc) == 0x4 && (value & 0xffff0000) == 0) - psHu32(mem) = (psHu32(mem) & 0xFFFF0000) | (u16)value; + if (((value & 0xc) == 0x4) && ((value & 0xffff0000) == 0)) + psHu32(mem) = (psHu32(mem) & 0xffff0000) | (u16)value; else /* Else (including Normal mode etc) write whatever the hardware sends*/ psHu32(mem) = (u32)value; @@ -127,14 +130,15 @@ char sio_buffer[1024]; int sio_count; u16 QueuedDMA = 0; -void hwWrite8(u32 mem, u8 value) { - - if( (mem>=0x10003800) && (mem<0x10004000) ) +void hwWrite8(u32 mem, u8 value) +{ + if ((mem >= VIF0_STAT) && (mem < VIF0_FIFO)) { u32 bytemod = mem & 0x3; u32 bitpos = 8 * bytemod; u32 newval = psHu8(mem) & (255UL << bitpos); - if( mem < 0x10003c00 ) + + if (mem < VIF1_STAT) vif0Write32( mem & ~0x3, newval | (value<= 0x10002000 && mem < 0x10008000 ) + if( mem >= IPU_CMD && mem < D0_CHCR ) DevCon::Notice( "hwWrite8 to 0x%x = 0x%x", params mem, value ); switch (mem) { @@ -168,14 +172,12 @@ void hwWrite8(u32 mem, u8 value) { case 0x10001811: rcntWmode(3, (counters[3].modeval & 0xff) | value << 8); break; case RCNT3_TARGET: rcntWtarget(3, value); break; - case 0x1000f180: + case SIO_TXFIFO: { - //bool flush = false; - // Terminate lines on CR or full buffers, and ignore \n's if the string contents // are empty (otherwise terminate on \n too!) - if( ( value == '\r' ) || ( sio_count == 1023 ) || - ( value == '\n' && sio_count != 0 ) ) + if (( value == '\r' ) || ( sio_count == 1023 ) || + ( value == '\n' && sio_count != 0 )) { sio_buffer[sio_count] = 0; Console::WriteLn( Color_Cyan, sio_buffer ); @@ -293,28 +295,48 @@ void hwWrite8(u32 mem, u8 value) { DmaExec8(dmaSPR1, mem, value); break; - case 0x1000f592: // DMAC_ENABLEW + case 0x1000f592: // DMAC_ENABLEW + 2 psHu8(0xf592) = value; psHu8(0xf522) = value; break; - case 0x1000f200: // SIF(?) + case SBUS_F200: // SIF(?) psHu8(mem) = value; break; - case 0x1000f240:// SIF(?) - if(!(value & 0x100)) - psHu32(mem) &= ~0x100; + case SBUS_F210: + psHu8(mem) = value; + break; + + case SBUS_F220: + psHu8(mem) = value; + break; + + case SBUS_F230: + psHu8(mem) = value; + break; + + case SBUS_F240:// SIF(?) + if (!(value & 0x100)) psHu32(mem) &= ~0x100; + break; + + case SBUS_F250: + psHu8(mem) = value; + break; + + case SBUS_F260: + psHu8(mem) = value; break; default: assert( (mem&0xff0f) != 0xf200 ); switch(mem&~3) { - case 0x1000f130: + case SIO_ISR: case 0x1000f410: - case 0x1000f430: + case MCH_RICM: break; + default: psHu8(mem) = value; } @@ -325,7 +347,7 @@ void hwWrite8(u32 mem, u8 value) { __forceinline void hwWrite16(u32 mem, u16 value) { - if( mem >= 0x10002000 && mem < 0x10008000 ) + if( mem >= IPU_CMD && mem < D0_CHCR ) Console::Notice( "hwWrite16 to %x", params mem ); switch(mem) @@ -374,22 +396,27 @@ __forceinline void hwWrite16(u32 mem, u16 value) HW_LOG("VIF1dma Madr %lx", value); psHu16(mem) = value;//dma1 madr break; + case D1_QWC: // dma1 - vif1 - qwc HW_LOG("VIF1dma QWC %lx", value); psHu16(mem) = value;//dma1 qwc break; + case D1_TADR: // dma1 - vif1 - tadr HW_LOG("VIF1dma TADR %lx", value); psHu16(mem) = value;//dma1 tadr break; + case D1_ASR0: // dma1 - vif1 - asr0 HW_LOG("VIF1dma ASR0 %lx", value); psHu16(mem) = value;//dma1 asr0 break; + case D1_ASR1: // dma1 - vif1 - asr1 HW_LOG("VIF1dma ASR1 %lx", value); psHu16(mem) = value;//dma1 asr1 break; + case D1_SADR: // dma1 - vif1 - sadr HW_LOG("VIF1dma SADR %lx", value); psHu16(mem) = value;//dma1 sadr @@ -412,22 +439,27 @@ __forceinline void hwWrite16(u32 mem, u16 value) psHu16(mem) = value;//dma2 madr HW_LOG("Hardware write DMA2_MADR 32bit at %x with value %x",mem,value); break; + case D2_QWC: psHu16(mem) = value;//dma2 qwc HW_LOG("Hardware write DMA2_QWC 32bit at %x with value %x",mem,value); break; + case D2_TADR: psHu16(mem) = value;//dma2 taddr HW_LOG("Hardware write DMA2_TADDR 32bit at %x with value %x",mem,value); break; + case D2_ASR0: psHu16(mem) = value;//dma2 asr0 HW_LOG("Hardware write DMA2_ASR0 32bit at %x with value %x",mem,value); break; + case D2_ASR1: psHu16(mem) = value;//dma2 asr1 HW_LOG("Hardware write DMA2_ASR1 32bit at %x with value %x",mem,value); break; + case D2_SADR: psHu16(mem) = value;//dma2 saddr HW_LOG("Hardware write DMA2_SADDR 32bit at %x with value %x",mem,value); @@ -449,14 +481,17 @@ __forceinline void hwWrite16(u32 mem, u16 value) psHu16(mem) = value;//dma2 madr HW_LOG("Hardware write IPU0DMA_MADR 32bit at %x with value %x",mem,value); break; + case D3_QWC: psHu16(mem) = value;//dma2 madr HW_LOG("Hardware write IPU0DMA_QWC 32bit at %x with value %x",mem,value); - break; + break; + case D3_TADR: psHu16(mem) = value;//dma2 tadr HW_LOG("Hardware write IPU0DMA_TADR 32bit at %x with value %x",mem,value); break; + case D3_SADR: psHu16(mem) = value;//dma2 saddr HW_LOG("Hardware write IPU0DMA_SADDR 32bit at %x with value %x",mem,value); @@ -478,14 +513,17 @@ __forceinline void hwWrite16(u32 mem, u16 value) psHu16(mem) = value;//dma2 madr HW_LOG("Hardware write IPU1DMA_MADR 32bit at %x with value %x",mem,value); break; + case D4_QWC: psHu16(mem) = value;//dma2 madr HW_LOG("Hardware write IPU1DMA_QWC 32bit at %x with value %x",mem,value); break; + case D4_TADR: psHu16(mem) = value;//dma2 tadr HW_LOG("Hardware write IPU1DMA_TADR 32bit at %x with value %x",mem,value); break; + case D4_SADR: psHu16(mem) = value;//dma2 saddr HW_LOG("Hardware write IPU1DMA_SADDR 32bit at %x with value %x",mem,value); @@ -502,9 +540,10 @@ __forceinline void hwWrite16(u32 mem, u16 value) DmaExec16(dmaSIF0, mem, value); break; - case 0x1000c002: + case 0x1000c002: // D5_CHCR + 2 //? break; + case D6_CHCR: // dma6 - sif1 DMA_LOG("SIF1dma %lx", value); if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1)) @@ -514,15 +553,24 @@ __forceinline void hwWrite16(u32 mem, u16 value) } DmaExec16(dmaSIF1, mem, value); break; - + + // Given the other values here, perhaps something like this is in order? + /*case 0x1000C402: // D6_CHCR + 2 + //? + break;*/ + #ifdef PCSX2_DEVBUILD - // No D6_MADR, and a TADR address that's not in the defines? + case D6_MADR: // dma6 - sif1 - madr + HW_LOG("SIF1dma MADR = %lx", value); + psHu16(mem) = value; + break; + case D6_QWC: // dma6 - sif1 - qwc HW_LOG("SIF1dma QWC = %lx", value); psHu16(mem) = value; break; - case 0x1000c430: // dma6 - sif1 - tadr + case D6_TADR: // dma6 - sif1 - tadr HW_LOG("SIF1dma TADR = %lx", value); psHu16(mem) = value; break; @@ -537,9 +585,11 @@ __forceinline void hwWrite16(u32 mem, u16 value) } DmaExec16(dmaSIF2, mem, value); break; - case 0x1000c802: + + case 0x1000c802: // D7_CHCR + 2 //? break; + case D8_CHCR: // dma8 - fromSPR DMA_LOG("fromSPRdma %lx", value); if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1)) @@ -550,7 +600,7 @@ __forceinline void hwWrite16(u32 mem, u16 value) DmaExec16(dmaSPR0, mem, value); break; - case 0x1000d400: // dma9 - toSPR + case SPR1_CHCR: // dma9 - toSPR DMA_LOG("toSPRdma %lx", value); if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1)) { @@ -559,35 +609,48 @@ __forceinline void hwWrite16(u32 mem, u16 value) } DmaExec16(dmaSPR1, mem, value); break; - case 0x1000f592: // DMAC_ENABLEW + + case 0x1000f592: // DMAC_ENABLEW + 2 psHu16(0xf592) = value; psHu16(0xf522) = value; break; - case 0x1000f130: + + case SIO_ISR: case 0x1000f132: case 0x1000f410: case 0x1000f412: - case 0x1000f430: + case MCH_RICM: case 0x1000f432: break; - case 0x1000f200: + case SBUS_F200: + psHu16(mem) = value; + break; + + case SBUS_F210: psHu16(mem) = value; break; case SBUS_F220: psHu16(mem) |= value; break; - case SBUS_SMFLG: + + case SBUS_F230: psHu16(mem) &= ~value; break; + case SBUS_F240: - if(!(value & 0x100)) + if (!(value & 0x100)) psHu16(mem) &= ~0x100; else psHu16(mem) |= 0x100; break; - case 0x1000f260: + + case SBUS_F250: + psHu16(mem) = value; + break; + + case SBUS_F260: psHu16(mem) = 0; break; @@ -644,9 +707,9 @@ void __fastcall hwWrite32_page_02( u32 mem, u32 value ) // Page 3 contains writes to vif0 and vif1 registers, plus some GIF stuff! void __fastcall hwWrite32_page_03( u32 mem, u32 value ) { - if(mem>=0x10003800) + if (mem >= VIF0_STAT) { - if(mem<0x10003c00) + if(mem < VIF1_STAT) vif0Write32(mem, value); else vif1Write32(mem, value); @@ -657,6 +720,7 @@ void __fastcall hwWrite32_page_03( u32 mem, u32 value ) { case GIF_CTRL: psHu32(mem) = value & 0x8; + if (value & 0x1) gsGIFReset(); else if( value & 8 ) @@ -701,7 +765,7 @@ void __fastcall hwWrite32_page_0B( u32 mem, u32 value ) QueuedDMA |= 0x8; } DmaExec(dmaIPU0, mem, value); - return; + return; case D3_MADR: regName = "IPU0DMA_MADR"; break; case D3_QWC: regName = "IPU0DMA_QWC"; break; @@ -718,7 +782,7 @@ void __fastcall hwWrite32_page_0B( u32 mem, u32 value ) QueuedDMA |= 0x10; } DmaExec(dmaIPU1, mem, value); - return; + return; case D4_MADR: regName = "IPU1DMA_MADR"; break; case D4_QWC: regName = "IPU1DMA_QWC"; break; @@ -746,32 +810,39 @@ void __fastcall StartQueuedDMA() void __fastcall hwWrite32_page_0E( u32 mem, u32 value ) { - if( mem == DMAC_CTRL ) + switch (mem) { - HW_LOG("DMAC_CTRL Write 32bit %x", value); - //Check for DMAS that were started while the DMAC was disabled - if((psHu32(mem) & 0x1) == 0 && (value & 0x1) == 1) + case DMAC_CTRL: { + u32 oldvalue = psHu32(mem); + + HW_LOG("DMAC_CTRL Write 32bit %x", value); + psHu32(mem) = value; - if(QueuedDMA != 0) StartQueuedDMA(); - return; + //Check for DMAS that were started while the DMAC was disabled + if (((oldvalue & 0x1) == 0) && ((value & 0x1) == 1)) + { + if (QueuedDMA != 0) StartQueuedDMA(); + } + break; } + + case DMAC_STAT: + HW_LOG("DMAC_STAT Write 32bit %x", value); + + // lower 16 bits: clear on 1 + // upper 16 bits: reverse on 1 + + psHu16(0xe010) &= ~(value & 0xffff); + psHu16(0xe012) ^= (u16)(value >> 16); + + cpuTestDMACInts(); + break; + + default: + psHu32(mem) = value; + break; } - else if( mem == DMAC_STAT ) - { - HW_LOG("DMAC_STAT Write 32bit %x", value); - - // lower 16 bits: clear on 1 - // upper 16 bits: reverse on 1 - - psHu16(0xe010) &= ~(value & 0xffff); - psHu16(0xe012) ^= (u16)(value >> 16); - - cpuTestDMACInts(); - return; - } - - psHu32(mem) = value; } void __fastcall hwWrite32_page_0F( u32 mem, u32 value ) @@ -796,46 +867,50 @@ void __fastcall hwWrite32_page_0F( u32 mem, u32 value ) break; //------------------------------------------------------------------ - case HELPSWITCH(0x1000f430)://MCH_RICM: x:4|SA:12|x:5|SDEV:1|SOP:4|SBC:1|SDEV:5 + case HELPSWITCH(MCH_RICM)://MCH_RICM: x:4|SA:12|x:5|SDEV:1|SOP:4|SBC:1|SDEV:5 if ((((value >> 16) & 0xFFF) == 0x21) && (((value >> 6) & 0xF) == 1) && (((psHu32(0xf440) >> 7) & 1) == 0))//INIT & SRP=0 rdram_sdevid = 0; // if SIO repeater is cleared, reset sdevid psHu32(mem) = value & ~0x80000000; //kill the busy bit break; - case HELPSWITCH(0x1000f200): + case HELPSWITCH(SBUS_F200): psHu32(mem) = value; break; + case HELPSWITCH(SBUS_F220): psHu32(mem) |= value; break; - case HELPSWITCH(SBUS_SMFLG): + + case HELPSWITCH(SBUS_F230): psHu32(mem) &= ~value; break; + case HELPSWITCH(SBUS_F240): if(!(value & 0x100)) psHu32(mem) &= ~0x100; else psHu32(mem) |= 0x100; break; - case HELPSWITCH(0x1000f260): + + case HELPSWITCH(SBUS_F260): psHu32(mem) = 0; break; - case HELPSWITCH(0x1000f440)://MCH_DRD: + case HELPSWITCH(MCH_DRD)://MCH_DRD: psHu32(mem) = value; break; - case HELPSWITCH(DMAC_ENABLEW): // DMAC_ENABLEW + case HELPSWITCH(DMAC_ENABLEW): HW_LOG("DMAC_ENABLEW Write 32bit %lx", value); psHu32(0xf590) = value; psHu32(0xf520) = value; break; //------------------------------------------------------------------ - case HELPSWITCH(0x1000f130): + case HELPSWITCH(SIO_ISR): case HELPSWITCH(0x1000f410): HW_LOG("Unknown Hardware write 32 at %x with value %x (%x)", mem, value, cpuRegs.CP0.n.Status.val); - break; + break; default: psHu32(mem) = value; @@ -851,26 +926,31 @@ void __fastcall hwWrite32_generic( u32 mem, u32 value ) { case D0_CHCR: // dma0 - vif0 DMA_LOG("VIF0dma EXECUTE, value=0x%x", value); + if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1)) { DevCon::Notice("32 bit VIF0 DMA Start while DMAC Disabled\n"); QueuedDMA |= 0x1; } + DmaExec(dmaVIF0, mem, value); return; //------------------------------------------------------------------ case D1_CHCR: // dma1 - vif1 - chcr DMA_LOG("VIF1dma EXECUTE, value=0x%x", value); + if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1)) { DevCon::Notice("32 bit VIF1 DMA Start while DMAC Disabled\n"); QueuedDMA |= 0x2; } - if(value & 0x100) + + if (value & 0x100) { vif1.done = false; //This must be done here! some games (ala Crash of the Titans) pause the dma to start MFIFO - } + } + DmaExec(dmaVIF1, mem, value); return; @@ -921,9 +1001,9 @@ void __fastcall hwWrite32_generic( u32 mem, u32 value ) DmaExec(dmaSIF1, mem, value); return; - // Again, no MADR, and an undefined TADR. + case D6_MADR: regName = "SIF1dma MADR"; break; case D6_QWC: regName = "SIF1dma QWC"; break; - case 0x1000c430: regName = "SIF1dma TADR"; break; + case D6_TADR: regName = "SIF1dma TADR"; break; //------------------------------------------------------------------ case D7_CHCR: // dma7 - sif2 @@ -946,7 +1026,7 @@ void __fastcall hwWrite32_generic( u32 mem, u32 value ) DmaExec(dmaSPR0, mem, value); return; //------------------------------------------------------------------ - case 0x1000d400: // dma9 - toSPR + case SPR1_CHCR: // dma9 - toSPR DMA_LOG("SPR1dma EXECUTE (toSPR), value=0x%x", value); if ((value & 0x100) && !(psHu32(DMAC_CTRL) & 0x1)) { @@ -974,9 +1054,9 @@ void __fastcall hwWrite64_page_03( u32 mem, const mem64_t* srcval ) //hwWrite64( mem, *srcval ); return; const u64 value = *srcval; - if(mem>=0x10003800) + if (mem >= VIF0_STAT) { - if(mem<0x10003c00) + if (mem < VIF1_STAT) vif0Write32(mem, value); else vif1Write32(mem, value); @@ -997,23 +1077,23 @@ void __fastcall hwWrite64_page_03( u32 mem, const mem64_t* srcval ) else psHu32(GIF_STAT) &= ~8; } - - return; + break; case GIF_MODE: { + // set/clear bits 0 and 2 as per the GIF_MODE value. + const u32 bitmask = 0x1 | 0x4; + Console::Status("GIFMODE64 %x", params value); psHu64(GIF_MODE) = value; - - // set/clear bits 0 and 2 as per the GIF_MODE value. - const u32 bitmask = 0x1 | 0x4; psHu32(GIF_STAT) &= ~bitmask; psHu32(GIF_STAT) |= (u32)value & bitmask; + break; } case GIF_STAT: // stat is readonly - return; + break; } } @@ -1023,31 +1103,38 @@ void __fastcall hwWrite64_page_0E( u32 mem, const mem64_t* srcval ) const u64 value = *srcval; - if( mem == DMAC_CTRL ) + switch (mem) { - HW_LOG("DMAC_CTRL Write 64bit %x", value); - if((psHu32(mem) & 0x1) == 0 && (value & 0x1) == 1) + case DMAC_CTRL: { + u32 oldvalue = psHu32(mem); psHu64(mem) = value; - if(QueuedDMA != 0) StartQueuedDMA(); - return; + + HW_LOG("DMAC_CTRL Write 64bit %x", value); + + if (((oldvalue & 0x1) == 0) && ((value & 0x1) == 1)) + { + if (QueuedDMA != 0) StartQueuedDMA(); + } + break; } + + case DMAC_STAT: + HW_LOG("DMAC_STAT Write 64bit %x", value); + + // lower 16 bits: clear on 1 + // upper 16 bits: reverse on 1 + + psHu16(0xe010) &= ~(value & 0xffff); + psHu16(0xe012) ^= (u16)(value >> 16); + + cpuTestDMACInts(); + break; + + default: + psHu64(mem) = value; + break; } - else if( mem == DMAC_STAT ) - { - HW_LOG("DMAC_STAT Write 64bit %x", value); - - // lower 16 bits: clear on 1 - // upper 16 bits: reverse on 1 - - psHu16(0xe010) &= ~(value & 0xffff); - psHu16(0xe012) ^= (u16)(value >> 16); - - cpuTestDMACInts(); - return; - } - - psHu64(mem) = value; } void __fastcall hwWrite64_generic( u32 mem, const mem64_t* srcval ) @@ -1061,23 +1148,23 @@ void __fastcall hwWrite64_generic( u32 mem, const mem64_t* srcval ) case D2_CHCR: // dma2 - gif DMA_LOG("0x%8.8x hwWrite64: GSdma %x", cpuRegs.cycle, value); DmaExec(dmaGIF, mem, value); - break; + break; case INTC_STAT: HW_LOG("INTC_STAT Write 64bit %x", (u32)value); psHu32(INTC_STAT) &= ~value; //cpuTestINTCInts(); - break; + break; case INTC_MASK: HW_LOG("INTC_MASK Write 64bit %x", (u32)value); psHu32(INTC_MASK) ^= (u16)value; cpuTestINTCInts(); - break; + break; - case 0x1000f130: + case SIO_ISR: case 0x1000f410: - case 0x1000f430: + case MCH_RICM: break; case DMAC_ENABLEW: // DMAC_ENABLEW @@ -1118,9 +1205,9 @@ void __fastcall hwWrite128_generic(u32 mem, const mem128_t *srcval) psHu32(0xf520) = srcval[0]; break; - case 0x1000f130: + case SIO_ISR: case 0x1000f410: - case 0x1000f430: + case MCH_RICM: break; default: diff --git a/pcsx2/IopDma.cpp b/pcsx2/IopDma.cpp index 1e9231a99d..96ed3e3c7e 100644 --- a/pcsx2/IopDma.cpp +++ b/pcsx2/IopDma.cpp @@ -170,13 +170,13 @@ void psxDma9(u32 madr, u32 bcr, u32 chcr) SIF_LOG("IOP: dmaSIF0 chcr = %lx, madr = %lx, bcr = %lx, tadr = %lx", chcr, madr, bcr, HW_DMA9_TADR); iopsifbusy[0] = 1; - psHu32(0x1000F240) |= 0x2000; + psHu32(SBUS_F240) |= 0x2000; if (eesifbusy[0] == 1) { SIF0Dma(); - psHu32(0x1000F240) &= ~0x20; - psHu32(0x1000F240) &= ~0x2000; + psHu32(SBUS_F240) &= ~0x20; + psHu32(SBUS_F240) &= ~0x2000; } } @@ -185,15 +185,15 @@ void psxDma10(u32 madr, u32 bcr, u32 chcr) SIF_LOG("IOP: dmaSIF1 chcr = %lx, madr = %lx, bcr = %lx", chcr, madr, bcr); iopsifbusy[1] = 1; - psHu32(0x1000F240) |= 0x4000; + psHu32(SBUS_F240) |= 0x4000; if (eesifbusy[1] == 1) { FreezeXMMRegs(1); SIF1Dma(); - psHu32(0x1000F240) &= ~0x40; - psHu32(0x1000F240) &= ~0x100; - psHu32(0x1000F240) &= ~0x4000; + psHu32(SBUS_F240) &= ~0x40; + psHu32(SBUS_F240) &= ~0x100; + psHu32(SBUS_F240) &= ~0x4000; FreezeXMMRegs(0); } } diff --git a/pcsx2/IopMem.cpp b/pcsx2/IopMem.cpp index a9580a1cdb..55003d58b7 100644 --- a/pcsx2/IopMem.cpp +++ b/pcsx2/IopMem.cpp @@ -195,13 +195,13 @@ u16 iopMemRead16(u32 mem) switch(mem & 0xF0) { case 0x00: - ret= psHu16(0x1000F200); + ret= psHu16(SBUS_F200); break; case 0x10: - ret= psHu16(0x1000F210); + ret= psHu16(SBUS_F210); break; case 0x40: - ret= psHu16(0x1000F240) | 0x0002; + ret= psHu16(SBUS_F240) | 0x0002; break; case 0x60: ret = 0; @@ -261,19 +261,19 @@ u32 iopMemRead32(u32 mem) switch(mem & 0xF0) { case 0x00: - ret= psHu32(0x1000F200); + ret= psHu32(SBUS_F200); break; case 0x10: - ret= psHu32(0x1000F210); + ret= psHu32(SBUS_F210); break; case 0x20: - ret= psHu32(0x1000F220); + ret= psHu32(SBUS_F220); break; case 0x30: // EE Side - ret= psHu32(0x1000F230); + ret= psHu32(SBUS_F230); break; case 0x40: - ret= psHu32(0x1000F240) | 0xF0000002; + ret= psHu32(SBUS_F240) | 0xF0000002; break; case 0x60: ret = 0; @@ -405,7 +405,7 @@ void iopMemWrite16(u32 mem, u16 value) { case 0x10: // write to ps2 mem - psHu16(0x1000F210) = value; + psHu16(SBUS_F210) = value; return; case 0x40: { @@ -413,17 +413,19 @@ void iopMemWrite16(u32 mem, u16 value) // write to ps2 mem if(value & 0x20 || value & 0x80) { - psHu16(0x1000F240) &= ~0xF000; - psHu16(0x1000F240) |= 0x2000; + psHu16(SBUS_F240) &= ~0xF000; + psHu16(SBUS_F240) |= 0x2000; } - if(psHu16(0x1000F240) & temp) psHu16(0x1000F240) &= ~temp; - else psHu16(0x1000F240) |= temp; + if(psHu16(SBUS_F240) & temp) + psHu16(SBUS_F240) &= ~temp; + else + psHu16(SBUS_F240) |= temp; return; } case 0x60: - psHu32(0x1000F260) = 0; + psHu32(SBUS_F260) = 0; return; } @@ -490,36 +492,36 @@ void iopMemWrite32(u32 mem, u32 value) return; // this is the IOP, so read-only (do nothing) case 0x10: // IOP write path (EE/IOP readable) - psHu32(0x1000F210) = value; + psHu32(SBUS_F210) = value; return; case 0x20: // Bits cleared when written from IOP. - psHu32(0x1000F220) &= ~value; + psHu32(SBUS_F220) &= ~value; return; case 0x30: // bits set when written from IOP - psHu32(0x1000F230) |= value; + psHu32(SBUS_F230) |= value; return; case 0x40: // Control Register { u32 temp = value & 0xF0; - if(value & 0x20 || value & 0x80) + if (value & 0x20 || value & 0x80) { - psHu32(0x1000F240) &= ~0xF000; - psHu32(0x1000F240) |= 0x2000; + psHu32(SBUS_F240) &= ~0xF000; + psHu32(SBUS_F240) |= 0x2000; } - if(psHu32(0x1000F240) & temp) - psHu32(0x1000F240) &= ~temp; + if (psHu32(SBUS_F240) & temp) + psHu32(SBUS_F240) &= ~temp; else - psHu32(0x1000F240) |= temp; + psHu32(SBUS_F240) |= temp; return; } case 0x60: - psHu32(0x1000F260) = 0; + psHu32(SBUS_F260) = 0; return; } psxSu32(mem) = value; diff --git a/pcsx2/Sif.cpp b/pcsx2/Sif.cpp index 5fdaa6ca05..73d1c8d8f0 100644 --- a/pcsx2/Sif.cpp +++ b/pcsx2/Sif.cpp @@ -452,15 +452,15 @@ __forceinline void dmaSIF0() SIF_LOG("warning, sif0.fifoReadPos != sif0.fifoWritePos"); } - psHu32(0x1000F240) |= 0x2000; + psHu32(SBUS_F240) |= 0x2000; eesifbusy[0] = 1; if (iopsifbusy[0] == 1) { FreezeXMMRegs(1); hwIntcIrq(INTC_SBUS); SIF0Dma(); - psHu32(0x1000F240) &= ~0x20; - psHu32(0x1000F240) &= ~0x2000; + psHu32(SBUS_F240) &= ~0x20; + psHu32(SBUS_F240) &= ~0x2000; FreezeXMMRegs(0); } } @@ -475,15 +475,15 @@ __forceinline void dmaSIF1() SIF_LOG("warning, sif1.fifoReadPos != sif1.fifoWritePos"); } - psHu32(0x1000F240) |= 0x4000; + psHu32(SBUS_F240) |= 0x4000; eesifbusy[1] = 1; if (iopsifbusy[1] == 1) { FreezeXMMRegs(1); SIF1Dma(); - psHu32(0x1000F240) &= ~0x40; - psHu32(0x1000F240) &= ~0x100; - psHu32(0x1000F240) &= ~0x4000; + psHu32(SBUS_F240) &= ~0x40; + psHu32(SBUS_F240) &= ~0x100; + psHu32(SBUS_F240) &= ~0x4000; FreezeXMMRegs(0); } diff --git a/pcsx2/VifDma.cpp b/pcsx2/VifDma.cpp index e24adc47d9..e6ca05a339 100644 --- a/pcsx2/VifDma.cpp +++ b/pcsx2/VifDma.cpp @@ -351,7 +351,6 @@ static int VIFalign(u32 *data, vifCode *v, unsigned int size, const unsigned int vifMaskRegs = g_vif0Masks; vif = &vif0; vifRow = g_vifRow0; - assert(v->addr < memsize); } else { @@ -360,8 +359,8 @@ static int VIFalign(u32 *data, vifCode *v, unsigned int size, const unsigned int vifMaskRegs = g_vif1Masks; vif = &vif1; vifRow = g_vifRow1; - assert(v->addr < memsize); } + assert(v->addr < memsize); dest = (u32*)(VU->Mem + v->addr); @@ -1554,8 +1553,8 @@ void vif0Write32(u32 mem, u32 value) memzero_obj(vif0); vif0ch->qwc = 0; //? cpuRegs.interrupt &= ~1; //Stop all vif0 DMA's - psHu64(0x10004000) = 0; - psHu64(0x10004008) = 0; + psHu64(VIF0_FIFO) = 0; + psHu64(0x10004008) = 0; // VIF0_FIFO + 8 vif0.done = true; vif0Regs->err = 0; vif0Regs->stat &= ~(0xF000000 | VIF0_STAT_INT | VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS | VIF0_STAT_VPS); // FQC=0 @@ -1619,22 +1618,25 @@ void vif0Write32(u32 mem, u32 value) vif0Regs->err = value; break; + case VIF0_R0: + case VIF0_R1: + case VIF0_R2: + case VIF0_R3: + assert((mem&0xf) == 0); + g_vifRow0[(mem>>4) & 3] = value; + break; + + case VIF0_C0: + case VIF0_C1: + case VIF0_C2: + case VIF0_C3: + assert((mem&0xf) == 0); + g_vifCol0[(mem>>4) & 3] = value; + break; + default: Console::WriteLn("Unknown Vif0 write to %x", params mem); - if (mem >= VIF0_R0 && mem < 0x10003980) // mem <= VIF0_C3? - { - assert((mem&0xf) == 0); - - if (mem < VIF0_C0) - g_vifRow0[(mem>>4)&3] = value; - else - g_vifCol0[(mem>>4)&3] = value; - - } - else - { - psHu32(mem) = value; - } + psHu32(mem) = value; break; } /* Other registers are read-only so do nothing for them */ @@ -1646,8 +1648,8 @@ void vif0Reset() memzero_obj(vif0); memzero_obj(*vif0Regs); SetNewMask(g_vif0Masks, g_vif0HasMask3, 0, 0xffffffff); - psHu64(0x10004000) = 0; - psHu64(0x10004008) = 0; + psHu64(VIF0_FIFO) = 0; + psHu64(0x10004008) = 0; // VIF0_FIFO + 8 vif0Regs->stat &= ~VIF0_STAT_VPS; vif0.done = true; vif0Regs->stat &= ~0xF000000; // FQC=0 @@ -1790,7 +1792,7 @@ static int __fastcall Vif1TransSTRow(u32 *data) pmem[0] = data[0]; pmem2[0] = data[0]; break; - jNO_DEFAULT; + jNO_DEFAULT; } vif1.tag.addr += ret; vif1.tag.size -= ret; @@ -2645,8 +2647,8 @@ void vif1Write32(u32 mem, u32 value) memzero_obj(vif1); cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's vif1ch->qwc = 0; //? - psHu64(0x10005000) = 0; - psHu64(0x10005008) = 0; + psHu64(VIF1_FIFO) = 0; + psHu64(0x10005008) = 0; // VIF1_FIFO + 8 vif1.done = true; vif1Regs->err = 0; vif1.inprogress = 0; @@ -2750,20 +2752,25 @@ void vif1Write32(u32 mem, u32 value) vif1Regs->mode = value; break; + case VIF1_R0: + case VIF1_R1: + case VIF1_R2: + case VIF1_R3: + assert((mem&0xf) == 0); + g_vifRow1[(mem>>4) & 3] = value; + break; + + case VIF1_C0: + case VIF1_C1: + case VIF1_C2: + case VIF1_C3: + assert((mem&0xf) == 0); + g_vifCol1[(mem>>4) & 3] = value; + break; + default: Console::WriteLn("Unknown Vif1 write to %x", params mem); - if ((mem >= VIF1_R0) && (mem < 0x10003d80)) // mem <= VIF1_C3? - { - assert((mem&0xf) == 0); - if (mem < VIF1_C0) - g_vifRow1[(mem>>4)&3] = value; - else - g_vifCol1[(mem>>4)&3] = value; - } - else - { - psHu32(mem) = value; - } + psHu32(mem) = value; break; } @@ -2776,8 +2783,8 @@ void vif1Reset() memzero_obj(vif1); memzero_obj(*vif1Regs); SetNewMask(g_vif1Masks, g_vif1HasMask3, 0, 0xffffffff); - psHu64(0x10005000) = 0; - psHu64(0x10005008) = 0; + psHu64(VIF1_FIFO) = 0; + psHu64(0x10005008) = 0; // VIF1_FIFO + 8 vif1Regs->stat &= ~VIF1_STAT_VPS; vif1.done = true; cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's diff --git a/pcsx2/VifDma.h b/pcsx2/VifDma.h index 86a1d1f78d..56c08d7d6f 100644 --- a/pcsx2/VifDma.h +++ b/pcsx2/VifDma.h @@ -25,54 +25,6 @@ enum VifModes VIF_CHAIN_MODE = 2 }; -enum VifMemoryLocations -{ - VIF0_STAT = 0x10003800, - VIF0_FBRST = 0x10003810, - VIF0_ERR = 0x10003820, - VIF0_MARK = 0x10003830, - VIF0_CYCLE = 0x10003840, - VIF0_MODE = 0x10003850, - VIF0_NUM = 0x10003860, - VIF0_MASK = 0x10003870, - VIF0_CODE = 0x10003880, - VIF0_ITOPS = 0x10003890, - VIF0_ITOP = 0x100038d0, - VIF0_TOP = 0x100038e0, - VIF0_R0 = 0x10003900, - VIF0_R1 = 0x10003910, - VIF0_R2 = 0x10003920, - VIF0_R3 = 0x10003930, - VIF0_C0 = 0x10003940, - VIF0_C1 = 0x10003950, - VIF0_C2 = 0x10003960, - VIF0_C3 = 0x10003970, - - VIF1_STAT = 0x10003c00, - VIF1_FBRST = 0x10003c10, - VIF1_ERR = 0x10003c20, - VIF1_MARK = 0x10003c30, - VIF1_CYCLE = 0x10003c40, - VIF1_MODE = 0x10003c50, - VIF1_NUM = 0x10003c60, - VIF1_MASK = 0x10003c70, - VIF1_CODE = 0x10003c80, - VIF1_ITOPS = 0x10003c90, - VIF1_BASE = 0x10003ca0, - VIF1_OFST = 0x10003cb0, - VIF1_TOPS = 0x10003cc0, - VIF1_ITOP = 0x10003cd0, - VIF1_TOP = 0x10003ce0, - VIF1_R0 = 0x10003d00, - VIF1_R1 = 0x10003d10, - VIF1_R2 = 0x10003d20, - VIF1_R3 = 0x10003d30, - VIF1_C0 = 0x10003d40, - VIF1_C1 = 0x10003d50, - VIF1_C2 = 0x10003d60, - VIF1_C3 = 0x10003d70 -}; - struct vifCode { u32 addr; u32 size;