diff --git a/plugins/spu2-x/src/Debug.cpp b/plugins/spu2-x/src/Debug.cpp index 8c88bcdf02..cf38fb7f49 100644 --- a/plugins/spu2-x/src/Debug.cpp +++ b/plugins/spu2-x/src/Debug.cpp @@ -216,39 +216,39 @@ void DoFullDump() fprintf(dump, " - IN_COEF_L: %x\n", Cores[c].Revb.IN_COEF_R); fprintf(dump, " - IN_COEF_R: %x\n", Cores[c].Revb.IN_COEF_L); - fprintf(dump, " - FB_ALPHA: %x\n", Cores[c].Revb.FB_ALPHA); - fprintf(dump, " - FB_X: %x\n", Cores[c].Revb.FB_X); - fprintf(dump, " - FB_SIZE_A: %x\n", Cores[c].Revb.FB_SIZE_A); - fprintf(dump, " - FB_SIZE_B: %x\n", Cores[c].Revb.FB_SIZE_B); + fprintf(dump, " - APF1_VOL: %x\n", Cores[c].Revb.APF1_VOL); + fprintf(dump, " - APF2_VOL: %x\n", Cores[c].Revb.APF2_VOL); + fprintf(dump, " - APF1_SIZE: %x\n", Cores[c].Revb.APF1_SIZE); + fprintf(dump, " - APF2_SIZE: %x\n", Cores[c].Revb.APF2_SIZE); - fprintf(dump, " - IIR_ALPHA: %x\n", Cores[c].Revb.IIR_ALPHA); - fprintf(dump, " - IIR_COEF: %x\n", Cores[c].Revb.IIR_COEF); - fprintf(dump, " - IIR_SRC_A0: %x\n", Cores[c].Revb.IIR_SRC_A0); - fprintf(dump, " - IIR_SRC_A1: %x\n", Cores[c].Revb.IIR_SRC_A1); - fprintf(dump, " - IIR_SRC_B0: %x\n", Cores[c].Revb.IIR_SRC_B0); - fprintf(dump, " - IIR_SRC_B1: %x\n", Cores[c].Revb.IIR_SRC_B1); - fprintf(dump, " - IIR_DEST_A0: %x\n", Cores[c].Revb.IIR_DEST_A0); - fprintf(dump, " - IIR_DEST_A1: %x\n", Cores[c].Revb.IIR_DEST_A1); - fprintf(dump, " - IIR_DEST_B0: %x\n", Cores[c].Revb.IIR_DEST_B0); - fprintf(dump, " - IIR_DEST_B1: %x\n", Cores[c].Revb.IIR_DEST_B1); + fprintf(dump, " - IIR_VOL: %x\n", Cores[c].Revb.IIR_VOL); + fprintf(dump, " - WALL_VOL: %x\n", Cores[c].Revb.WALL_VOL); + fprintf(dump, " - SAME_L_SRC: %x\n", Cores[c].Revb.SAME_L_SRC); + fprintf(dump, " - SAME_R_SRC: %x\n", Cores[c].Revb.SAME_R_SRC); + fprintf(dump, " - DIFF_L_SRC: %x\n", Cores[c].Revb.DIFF_L_SRC); + fprintf(dump, " - DIFF_R_SRC: %x\n", Cores[c].Revb.DIFF_R_SRC); + fprintf(dump, " - SAME_L_DST: %x\n", Cores[c].Revb.SAME_L_DST); + fprintf(dump, " - SAME_R_DST: %x\n", Cores[c].Revb.SAME_R_DST); + fprintf(dump, " - DIFF_L_DST: %x\n", Cores[c].Revb.DIFF_L_DST); + fprintf(dump, " - DIFF_R_DST: %x\n", Cores[c].Revb.DIFF_R_DST); - fprintf(dump, " - ACC_COEF_A: %x\n", Cores[c].Revb.ACC_COEF_A); - fprintf(dump, " - ACC_COEF_B: %x\n", Cores[c].Revb.ACC_COEF_B); - fprintf(dump, " - ACC_COEF_C: %x\n", Cores[c].Revb.ACC_COEF_C); - fprintf(dump, " - ACC_COEF_D: %x\n", Cores[c].Revb.ACC_COEF_D); - fprintf(dump, " - ACC_SRC_A0: %x\n", Cores[c].Revb.ACC_SRC_A0); - fprintf(dump, " - ACC_SRC_A1: %x\n", Cores[c].Revb.ACC_SRC_A1); - fprintf(dump, " - ACC_SRC_B0: %x\n", Cores[c].Revb.ACC_SRC_B0); - fprintf(dump, " - ACC_SRC_B1: %x\n", Cores[c].Revb.ACC_SRC_B1); - fprintf(dump, " - ACC_SRC_C0: %x\n", Cores[c].Revb.ACC_SRC_C0); - fprintf(dump, " - ACC_SRC_C1: %x\n", Cores[c].Revb.ACC_SRC_C1); - fprintf(dump, " - ACC_SRC_D0: %x\n", Cores[c].Revb.ACC_SRC_D0); - fprintf(dump, " - ACC_SRC_D1: %x\n", Cores[c].Revb.ACC_SRC_D1); + fprintf(dump, " - COMB1_VOL: %x\n", Cores[c].Revb.COMB1_VOL); + fprintf(dump, " - COMB2_VOL: %x\n", Cores[c].Revb.COMB2_VOL); + fprintf(dump, " - COMB3_VOL: %x\n", Cores[c].Revb.COMB3_VOL); + fprintf(dump, " - COMB4_VOL: %x\n", Cores[c].Revb.COMB4_VOL); + fprintf(dump, " - COMB1_L_SRC: %x\n", Cores[c].Revb.COMB1_L_SRC); + fprintf(dump, " - COMB1_R_SRC: %x\n", Cores[c].Revb.COMB1_R_SRC); + fprintf(dump, " - COMB2_L_SRC: %x\n", Cores[c].Revb.COMB2_L_SRC); + fprintf(dump, " - COMB2_R_SRC: %x\n", Cores[c].Revb.COMB2_R_SRC); + fprintf(dump, " - COMB3_L_SRC: %x\n", Cores[c].Revb.COMB3_L_SRC); + fprintf(dump, " - COMB3_R_SRC: %x\n", Cores[c].Revb.COMB3_R_SRC); + fprintf(dump, " - COMB4_L_SRC: %x\n", Cores[c].Revb.COMB4_L_SRC); + fprintf(dump, " - COMB4_R_SRC: %x\n", Cores[c].Revb.COMB4_R_SRC); - fprintf(dump, " - MIX_DEST_A0: %x\n", Cores[c].Revb.MIX_DEST_A0); - fprintf(dump, " - MIX_DEST_A1: %x\n", Cores[c].Revb.MIX_DEST_A1); - fprintf(dump, " - MIX_DEST_B0: %x\n", Cores[c].Revb.MIX_DEST_B0); - fprintf(dump, " - MIX_DEST_B1: %x\n", Cores[c].Revb.MIX_DEST_B1); + fprintf(dump, " - APF1_L_DST: %x\n", Cores[c].Revb.APF1_L_DST); + fprintf(dump, " - APF1_R_DST: %x\n", Cores[c].Revb.APF1_R_DST); + fprintf(dump, " - APF2_L_DST: %x\n", Cores[c].Revb.APF2_L_DST); + fprintf(dump, " - APF2_R_DST: %x\n", Cores[c].Revb.APF2_R_DST); fprintf(dump, "#### END OF DUMP.\n\n"); } fclose(dump); diff --git a/plugins/spu2-x/src/RegLog.cpp b/plugins/spu2-x/src/RegLog.cpp index f2e4a80cde..1914fc0f57 100644 --- a/plugins/spu2-x/src/RegLog.cpp +++ b/plugins/spu2-x/src/RegLog.cpp @@ -93,29 +93,29 @@ void SPU2writeLog(const char *action, u32 rmem, u16 value) case REG_P_MVOLXR: RegLog(2, "MVOLXR", rmem, core, value); break; - case R_IIR_ALPHA: - RegLog(2, "IIR_ALPHA", rmem, core, value); + case R_IIR_VOL: + RegLog(2, "IIR_VOL", rmem, core, value); break; - case R_ACC_COEF_A: - RegLog(2, "ACC_COEF_A", rmem, core, value); + case R_COMB1_VOL: + RegLog(2, "COMB1_VOL", rmem, core, value); break; - case R_ACC_COEF_B: - RegLog(2, "ACC_COEF_B", rmem, core, value); + case R_COMB2_VOL: + RegLog(2, "COMB2_VOL", rmem, core, value); break; - case R_ACC_COEF_C: - RegLog(2, "ACC_COEF_C", rmem, core, value); + case R_COMB3_VOL: + RegLog(2, "COMB3_VOL", rmem, core, value); break; - case R_ACC_COEF_D: - RegLog(2, "ACC_COEF_D", rmem, core, value); + case R_COMB4_VOL: + RegLog(2, "COMB4_VOL", rmem, core, value); break; - case R_IIR_COEF: - RegLog(2, "IIR_COEF", rmem, core, value); + case R_WALL_VOL: + RegLog(2, "WALL_VOL", rmem, core, value); break; - case R_FB_ALPHA: - RegLog(2, "FB_ALPHA", rmem, core, value); + case R_APF1_VOL: + RegLog(2, "APF1_VOL", rmem, core, value); break; - case R_FB_X: - RegLog(2, "FB_X", rmem, core, value); + case R_APF2_VOL: + RegLog(2, "APF2_VOL", rmem, core, value); break; case R_IN_COEF_L: RegLog(2, "IN_COEF_L", rmem, core, value); @@ -265,28 +265,28 @@ void SPU2writeLog(const char *action, u32 rmem, u16 value) RegLog(2, t "L", mem, core, value); \ break; - LOG_REVB_REG(FB_SIZE_A, "FB_SIZE_A") - LOG_REVB_REG(FB_SIZE_B, "FB_SIZE_B") - LOG_REVB_REG(IIR_SRC_A0, "IIR_SRC_A0") - LOG_REVB_REG(IIR_SRC_A1, "IIR_SRC_A1") - LOG_REVB_REG(IIR_SRC_B1, "IIR_SRC_B1") - LOG_REVB_REG(IIR_SRC_B0, "IIR_SRC_B0") - LOG_REVB_REG(IIR_DEST_A0, "IIR_DEST_A0") - LOG_REVB_REG(IIR_DEST_A1, "IIR_DEST_A1") - LOG_REVB_REG(IIR_DEST_B0, "IIR_DEST_B0") - LOG_REVB_REG(IIR_DEST_B1, "IIR_DEST_B1") - LOG_REVB_REG(ACC_SRC_A0, "ACC_SRC_A0") - LOG_REVB_REG(ACC_SRC_A1, "ACC_SRC_A1") - LOG_REVB_REG(ACC_SRC_B0, "ACC_SRC_B0") - LOG_REVB_REG(ACC_SRC_B1, "ACC_SRC_B1") - LOG_REVB_REG(ACC_SRC_C0, "ACC_SRC_C0") - LOG_REVB_REG(ACC_SRC_C1, "ACC_SRC_C1") - LOG_REVB_REG(ACC_SRC_D0, "ACC_SRC_D0") - LOG_REVB_REG(ACC_SRC_D1, "ACC_SRC_D1") - LOG_REVB_REG(MIX_DEST_A0, "MIX_DEST_A0") - LOG_REVB_REG(MIX_DEST_A1, "MIX_DEST_A1") - LOG_REVB_REG(MIX_DEST_B0, "MIX_DEST_B0") - LOG_REVB_REG(MIX_DEST_B1, "MIX_DEST_B1") + LOG_REVB_REG(APF1_SIZE, "APF1_SIZE") + LOG_REVB_REG(APF2_SIZE, "APF2_SIZE") + LOG_REVB_REG(SAME_L_SRC, "SAME_L_SRC") + LOG_REVB_REG(SAME_R_SRC, "SAME_R_SRC") + LOG_REVB_REG(DIFF_L_SRC, "DIFF_L_SRC") + LOG_REVB_REG(DIFF_R_SRC, "DIFF_R_SRC") + LOG_REVB_REG(SAME_L_DST, "SAME_L_DST") + LOG_REVB_REG(SAME_R_DST, "SAME_R_DST") + LOG_REVB_REG(DIFF_L_DST, "DIFF_L_DST") + LOG_REVB_REG(DIFF_R_DST, "DIFF_R_DST") + LOG_REVB_REG(COMB1_L_SRC, "COMB1_L_SRC") + LOG_REVB_REG(COMB1_R_SRC, "COMB1_R_SRC") + LOG_REVB_REG(COMB2_L_SRC, "COMB2_L_SRC") + LOG_REVB_REG(COMB2_R_SRC, "COMB2_R_SRC") + LOG_REVB_REG(COMB3_L_SRC, "COMB3_L_SRC") + LOG_REVB_REG(COMB3_R_SRC, "COMB3_R_SRC") + LOG_REVB_REG(COMB4_L_SRC, "COMB4_L_SRC") + LOG_REVB_REG(COMB4_R_SRC, "COMB4_R_SRC") + LOG_REVB_REG(APF1_L_DST, "APF1_L_DST") + LOG_REVB_REG(APF1_R_DST, "APF1_R_DST") + LOG_REVB_REG(APF2_L_DST, "APF2_L_DST") + LOG_REVB_REG(APF2_R_DST, "APF2_R_DST") default: RegLog(2, "UNKNOWN", rmem, core, value); diff --git a/plugins/spu2-x/src/RegTable.cpp b/plugins/spu2-x/src/RegTable.cpp index d3a0a5d6a1..665481cc39 100644 --- a/plugins/spu2-x/src/RegTable.cpp +++ b/plugins/spu2-x/src/RegTable.cpp @@ -99,28 +99,28 @@ u16 const *const regtable_original[0x401] = PCORE(0, ExtEffectsStartA) + 1, PCORE(0, ExtEffectsStartA), - PREVB_REG(0, FB_SIZE_A), - PREVB_REG(0, FB_SIZE_B), - PREVB_REG(0, IIR_DEST_A0), - PREVB_REG(0, IIR_DEST_A1), - PREVB_REG(0, ACC_SRC_A0), - PREVB_REG(0, ACC_SRC_A1), - PREVB_REG(0, ACC_SRC_B0), - PREVB_REG(0, ACC_SRC_B1), - PREVB_REG(0, IIR_SRC_A0), - PREVB_REG(0, IIR_SRC_A1), - PREVB_REG(0, IIR_DEST_B0), - PREVB_REG(0, IIR_DEST_B1), - PREVB_REG(0, ACC_SRC_C0), - PREVB_REG(0, ACC_SRC_C1), - PREVB_REG(0, ACC_SRC_D0), - PREVB_REG(0, ACC_SRC_D1), - PREVB_REG(0, IIR_SRC_B0), - PREVB_REG(0, IIR_SRC_B1), - PREVB_REG(0, MIX_DEST_A0), - PREVB_REG(0, MIX_DEST_A1), - PREVB_REG(0, MIX_DEST_B0), - PREVB_REG(0, MIX_DEST_B1), + PREVB_REG(0, APF1_SIZE), + PREVB_REG(0, APF2_SIZE), + PREVB_REG(0, SAME_L_DST), + PREVB_REG(0, SAME_R_DST), + PREVB_REG(0, COMB1_L_SRC), + PREVB_REG(0, COMB1_R_SRC), + PREVB_REG(0, COMB2_L_SRC), + PREVB_REG(0, COMB2_R_SRC), + PREVB_REG(0, SAME_L_SRC), + PREVB_REG(0, SAME_R_SRC), + PREVB_REG(0, DIFF_L_DST), + PREVB_REG(0, DIFF_R_DST), + PREVB_REG(0, COMB3_L_SRC), + PREVB_REG(0, COMB3_R_SRC), + PREVB_REG(0, COMB4_L_SRC), + PREVB_REG(0, COMB4_R_SRC), + PREVB_REG(0, DIFF_L_SRC), + PREVB_REG(0, DIFF_R_SRC), + PREVB_REG(0, APF1_L_DST), + PREVB_REG(0, APF1_R_DST), + PREVB_REG(0, APF2_L_DST), + PREVB_REG(0, APF2_R_DST), PCORE(0, ExtEffectsEndA) + 1, PCORE(0, ExtEffectsEndA), @@ -202,28 +202,28 @@ u16 const *const regtable_original[0x401] = PCORE(1, ExtEffectsStartA) + 1, PCORE(1, ExtEffectsStartA), - PREVB_REG(1, FB_SIZE_A), - PREVB_REG(1, FB_SIZE_B), - PREVB_REG(1, IIR_DEST_A0), - PREVB_REG(1, IIR_DEST_A1), - PREVB_REG(1, ACC_SRC_A0), - PREVB_REG(1, ACC_SRC_A1), - PREVB_REG(1, ACC_SRC_B0), - PREVB_REG(1, ACC_SRC_B1), - PREVB_REG(1, IIR_SRC_A0), - PREVB_REG(1, IIR_SRC_A1), - PREVB_REG(1, IIR_DEST_B0), - PREVB_REG(1, IIR_DEST_B1), - PREVB_REG(1, ACC_SRC_C0), - PREVB_REG(1, ACC_SRC_C1), - PREVB_REG(1, ACC_SRC_D0), - PREVB_REG(1, ACC_SRC_D1), - PREVB_REG(1, IIR_SRC_B0), - PREVB_REG(1, IIR_SRC_B1), - PREVB_REG(1, MIX_DEST_A0), - PREVB_REG(1, MIX_DEST_A1), - PREVB_REG(1, MIX_DEST_B0), - PREVB_REG(1, MIX_DEST_B1), + PREVB_REG(1, APF1_SIZE), + PREVB_REG(1, APF2_SIZE), + PREVB_REG(1, SAME_L_DST), + PREVB_REG(1, SAME_R_DST), + PREVB_REG(1, COMB1_L_SRC), + PREVB_REG(1, COMB1_R_SRC), + PREVB_REG(1, COMB2_L_SRC), + PREVB_REG(1, COMB2_R_SRC), + PREVB_REG(1, SAME_L_SRC), + PREVB_REG(1, SAME_R_SRC), + PREVB_REG(1, DIFF_L_DST), + PREVB_REG(1, DIFF_R_DST), + PREVB_REG(1, COMB3_L_SRC), + PREVB_REG(1, COMB3_R_SRC), + PREVB_REG(1, COMB4_L_SRC), + PREVB_REG(1, COMB4_R_SRC), + PREVB_REG(1, DIFF_L_SRC), + PREVB_REG(1, DIFF_R_SRC), + PREVB_REG(1, APF1_L_DST), + PREVB_REG(1, APF1_R_DST), + PREVB_REG(1, APF2_L_DST), + PREVB_REG(1, APF2_R_DST), PCORE(1, ExtEffectsEndA) + 1, PCORE(1, ExtEffectsEndA), @@ -248,14 +248,14 @@ u16 const *const regtable_original[0x401] = PCORE(0, InpVol.Right) + 1, PCORE(0, MasterVol.Left.Value) + 1, PCORE(0, MasterVol.Right.Value) + 1, - PCORE(0, Revb.IIR_ALPHA), - PCORE(0, Revb.ACC_COEF_A), - PCORE(0, Revb.ACC_COEF_B), - PCORE(0, Revb.ACC_COEF_C), - PCORE(0, Revb.ACC_COEF_D), - PCORE(0, Revb.IIR_COEF), - PCORE(0, Revb.FB_ALPHA), - PCORE(0, Revb.FB_X), + PCORE(0, Revb.IIR_VOL), + PCORE(0, Revb.COMB1_VOL), + PCORE(0, Revb.COMB2_VOL), + PCORE(0, Revb.COMB3_VOL), + PCORE(0, Revb.COMB4_VOL), + PCORE(0, Revb.WALL_VOL), + PCORE(0, Revb.APF1_VOL), + PCORE(0, Revb.APF2_VOL), PCORE(0, Revb.IN_COEF_L), PCORE(0, Revb.IN_COEF_R), @@ -269,14 +269,14 @@ u16 const *const regtable_original[0x401] = PCORE(1, InpVol.Right) + 1, PCORE(1, MasterVol.Left.Value) + 1, PCORE(1, MasterVol.Right.Value) + 1, - PCORE(1, Revb.IIR_ALPHA), - PCORE(1, Revb.ACC_COEF_A), - PCORE(1, Revb.ACC_COEF_B), - PCORE(1, Revb.ACC_COEF_C), - PCORE(1, Revb.ACC_COEF_D), - PCORE(1, Revb.IIR_COEF), - PCORE(1, Revb.FB_ALPHA), - PCORE(1, Revb.FB_X), + PCORE(1, Revb.IIR_VOL), + PCORE(1, Revb.COMB1_VOL), + PCORE(1, Revb.COMB2_VOL), + PCORE(1, Revb.COMB3_VOL), + PCORE(1, Revb.COMB4_VOL), + PCORE(1, Revb.WALL_VOL), + PCORE(1, Revb.APF1_VOL), + PCORE(1, Revb.APF2_VOL), PCORE(1, Revb.IN_COEF_L), PCORE(1, Revb.IN_COEF_R), diff --git a/plugins/spu2-x/src/Reverb.cpp b/plugins/spu2-x/src/Reverb.cpp index 05ac600dd8..025871d8bf 100644 --- a/plugins/spu2-x/src/Reverb.cpp +++ b/plugins/spu2-x/src/Reverb.cpp @@ -57,23 +57,23 @@ StereoOut32 V_Core::DoReverb(const StereoOut32 &Input) // Calculate the read/write addresses we'll be needing for this session of reverb. - const u32 same_src = RevbGetIndexer(R ? RevBuffers.IIR_SRC_A1 : RevBuffers.IIR_SRC_A0); - const u32 same_dst = RevbGetIndexer(R ? RevBuffers.IIR_DEST_A1 : RevBuffers.IIR_DEST_A0); + const u32 same_src = RevbGetIndexer(R ? RevBuffers.SAME_R_SRC : RevBuffers.SAME_L_SRC); + const u32 same_dst = RevbGetIndexer(R ? RevBuffers.SAME_R_DST : RevBuffers.SAME_L_DST); const u32 same_prv = RevbGetIndexer(R ? RevBuffers.SAME_R_PRV : RevBuffers.SAME_L_PRV); - const u32 diff_src = RevbGetIndexer(R ? RevBuffers.IIR_SRC_B0 : RevBuffers.IIR_SRC_B1); - const u32 diff_dst = RevbGetIndexer(R ? RevBuffers.IIR_DEST_B1 : RevBuffers.IIR_DEST_B0); + const u32 diff_src = RevbGetIndexer(R ? RevBuffers.DIFF_L_SRC : RevBuffers.DIFF_R_SRC); + const u32 diff_dst = RevbGetIndexer(R ? RevBuffers.DIFF_R_DST : RevBuffers.DIFF_L_DST); const u32 diff_prv = RevbGetIndexer(R ? RevBuffers.DIFF_R_PRV : RevBuffers.DIFF_L_PRV); - const u32 comb1_src = RevbGetIndexer(R ? RevBuffers.ACC_SRC_A1 : RevBuffers.ACC_SRC_A0); - const u32 comb2_src = RevbGetIndexer(R ? RevBuffers.ACC_SRC_B1 : RevBuffers.ACC_SRC_B0); - const u32 comb3_src = RevbGetIndexer(R ? RevBuffers.ACC_SRC_C1 : RevBuffers.ACC_SRC_C0); - const u32 comb4_src = RevbGetIndexer(R ? RevBuffers.ACC_SRC_D1 : RevBuffers.ACC_SRC_D0); + const u32 comb1_src = RevbGetIndexer(R ? RevBuffers.COMB1_R_SRC : RevBuffers.COMB1_L_SRC); + const u32 comb2_src = RevbGetIndexer(R ? RevBuffers.COMB2_R_SRC : RevBuffers.COMB2_L_SRC); + const u32 comb3_src = RevbGetIndexer(R ? RevBuffers.COMB3_R_SRC : RevBuffers.COMB3_L_SRC); + const u32 comb4_src = RevbGetIndexer(R ? RevBuffers.COMB4_R_SRC : RevBuffers.COMB4_L_SRC); const u32 apf1_src = RevbGetIndexer(R ? RevBuffers.APF1_R_SRC : RevBuffers.APF1_L_SRC); - const u32 apf1_dst = RevbGetIndexer(R ? RevBuffers.MIX_DEST_A1 : RevBuffers.MIX_DEST_A0); + const u32 apf1_dst = RevbGetIndexer(R ? RevBuffers.APF1_R_DST : RevBuffers.APF1_L_DST); const u32 apf2_src = RevbGetIndexer(R ? RevBuffers.APF2_R_SRC : RevBuffers.APF2_L_SRC); - const u32 apf2_dst = RevbGetIndexer(R ? RevBuffers.MIX_DEST_B1 : RevBuffers.MIX_DEST_B0); + const u32 apf2_dst = RevbGetIndexer(R ? RevBuffers.APF2_R_DST : RevBuffers.APF2_L_DST); // ----------------------------------------- // Optimized IRQ Testing ! @@ -109,15 +109,15 @@ StereoOut32 V_Core::DoReverb(const StereoOut32 &Input) #define MUL(x, y) ((x) * (y) >> 15) in = MUL(R ? Revb.IN_COEF_R : Revb.IN_COEF_L, R ? Input.Right : Input.Left); - same = MUL(Revb.IIR_ALPHA, in + MUL(Revb.IIR_COEF, _spu2mem[same_src]) - _spu2mem[same_prv]) + _spu2mem[same_prv]; - diff = MUL(Revb.IIR_ALPHA, in + MUL(Revb.IIR_COEF, _spu2mem[diff_src]) - _spu2mem[diff_prv]) + _spu2mem[diff_prv]; + same = MUL(Revb.IIR_VOL, in + MUL(Revb.WALL_VOL, _spu2mem[same_src]) - _spu2mem[same_prv]) + _spu2mem[same_prv]; + diff = MUL(Revb.IIR_VOL, in + MUL(Revb.WALL_VOL, _spu2mem[diff_src]) - _spu2mem[diff_prv]) + _spu2mem[diff_prv]; - out = MUL(Revb.ACC_COEF_A, _spu2mem[comb1_src]) + MUL(Revb.ACC_COEF_B, _spu2mem[comb2_src]) + MUL(Revb.ACC_COEF_C, _spu2mem[comb3_src]) + MUL(Revb.ACC_COEF_D, _spu2mem[comb4_src]); + out = MUL(Revb.COMB1_VOL, _spu2mem[comb1_src]) + MUL(Revb.COMB2_VOL, _spu2mem[comb2_src]) + MUL(Revb.COMB3_VOL, _spu2mem[comb3_src]) + MUL(Revb.COMB4_VOL, _spu2mem[comb4_src]); - apf1 = out - MUL(Revb.FB_ALPHA, _spu2mem[apf1_src]); - out = _spu2mem[apf1_src] + MUL(Revb.FB_ALPHA, apf1); - apf2 = out - MUL(Revb.FB_X, _spu2mem[apf2_src]); - out = _spu2mem[apf2_src] + MUL(Revb.FB_X, apf2); + apf1 = out - MUL(Revb.APF1_VOL, _spu2mem[apf1_src]); + out = _spu2mem[apf1_src] + MUL(Revb.APF1_VOL, apf1); + apf2 = out - MUL(Revb.APF2_VOL, _spu2mem[apf2_src]); + out = _spu2mem[apf2_src] + MUL(Revb.APF2_VOL, apf2); // According to no$psx the effects always run but don't always write back, see check in V_Core::Mix if (FxEnable) { diff --git a/plugins/spu2-x/src/defs.h b/plugins/spu2-x/src/defs.h index 037d633bd1..89e740065c 100644 --- a/plugins/spu2-x/src/defs.h +++ b/plugins/spu2-x/src/defs.h @@ -230,68 +230,68 @@ struct V_Reverb s16 IN_COEF_L; s16 IN_COEF_R; - u32 FB_SIZE_A; - u32 FB_SIZE_B; + u32 APF1_SIZE; + u32 APF2_SIZE; - s16 FB_ALPHA; - s16 FB_X; + s16 APF1_VOL; + s16 APF2_VOL; - u32 IIR_SRC_A0; - u32 IIR_SRC_A1; - u32 IIR_SRC_B1; - u32 IIR_SRC_B0; - u32 IIR_DEST_A0; - u32 IIR_DEST_A1; - u32 IIR_DEST_B0; - u32 IIR_DEST_B1; + u32 SAME_L_SRC; + u32 SAME_R_SRC; + u32 DIFF_L_SRC; + u32 DIFF_R_SRC; + u32 SAME_L_DST; + u32 SAME_R_DST; + u32 DIFF_L_DST; + u32 DIFF_R_DST; - s16 IIR_ALPHA; - s16 IIR_COEF; + s16 IIR_VOL; + s16 WALL_VOL; - u32 ACC_SRC_A0; - u32 ACC_SRC_A1; - u32 ACC_SRC_B0; - u32 ACC_SRC_B1; - u32 ACC_SRC_C0; - u32 ACC_SRC_C1; - u32 ACC_SRC_D0; - u32 ACC_SRC_D1; + u32 COMB1_L_SRC; + u32 COMB1_R_SRC; + u32 COMB2_L_SRC; + u32 COMB2_R_SRC; + u32 COMB3_L_SRC; + u32 COMB3_R_SRC; + u32 COMB4_L_SRC; + u32 COMB4_R_SRC; - s16 ACC_COEF_A; - s16 ACC_COEF_B; - s16 ACC_COEF_C; - s16 ACC_COEF_D; + s16 COMB1_VOL; + s16 COMB2_VOL; + s16 COMB3_VOL; + s16 COMB4_VOL; - u32 MIX_DEST_A0; - u32 MIX_DEST_A1; - u32 MIX_DEST_B0; - u32 MIX_DEST_B1; + u32 APF1_L_DST; + u32 APF1_R_DST; + u32 APF2_L_DST; + u32 APF2_R_DST; }; struct V_ReverbBuffers { - s32 IIR_SRC_A0; - s32 IIR_SRC_A1; - s32 IIR_SRC_B0; - s32 IIR_SRC_B1; - s32 IIR_DEST_A0; - s32 IIR_DEST_A1; - s32 IIR_DEST_B0; - s32 IIR_DEST_B1; + s32 SAME_L_SRC; + s32 SAME_R_SRC; + s32 DIFF_R_SRC; + s32 DIFF_L_SRC; + s32 SAME_L_DST; + s32 SAME_R_DST; + s32 DIFF_L_DST; + s32 DIFF_R_DST; - s32 ACC_SRC_A0; - s32 ACC_SRC_A1; - s32 ACC_SRC_B0; - s32 ACC_SRC_B1; - s32 ACC_SRC_C0; - s32 ACC_SRC_C1; - s32 ACC_SRC_D0; - s32 ACC_SRC_D1; + s32 COMB1_L_SRC; + s32 COMB1_R_SRC; + s32 COMB2_L_SRC; + s32 COMB2_R_SRC; + s32 COMB3_L_SRC; + s32 COMB3_R_SRC; + s32 COMB4_L_SRC; + s32 COMB4_R_SRC; - s32 MIX_DEST_A0; - s32 MIX_DEST_A1; - s32 MIX_DEST_B0; - s32 MIX_DEST_B1; + s32 APF1_L_DST; + s32 APF1_R_DST; + s32 APF2_L_DST; + s32 APF2_R_DST; s32 SAME_L_PRV; s32 SAME_R_PRV; diff --git a/plugins/spu2-x/src/regs.h b/plugins/spu2-x/src/regs.h index 1286796cca..73bdb4023e 100644 --- a/plugins/spu2-x/src/regs.h +++ b/plugins/spu2-x/src/regs.h @@ -62,28 +62,28 @@ // .. repeated for each voice .. #define REG_A_ESA 0x02E0 //Address: Top address of working area for effects processing -#define R_FB_SIZE_A 0x02E4 // Feedback Source A -#define R_FB_SIZE_B 0x02E8 // Feedback Source B -#define R_IIR_DEST_A0 0x02EC -#define R_IIR_DEST_A1 0x02F0 -#define R_ACC_SRC_A0 0x02F4 -#define R_ACC_SRC_A1 0x02F8 -#define R_ACC_SRC_B0 0x02FC -#define R_ACC_SRC_B1 0x0300 -#define R_IIR_SRC_A0 0x0304 -#define R_IIR_SRC_A1 0x0308 -#define R_IIR_DEST_B0 0x030C -#define R_IIR_DEST_B1 0x0310 -#define R_ACC_SRC_C0 0x0314 -#define R_ACC_SRC_C1 0x0318 -#define R_ACC_SRC_D0 0x031C -#define R_ACC_SRC_D1 0x0320 -#define R_IIR_SRC_B0 0x0324 // Some sources have R_IIR_SRC_B0 and R_IIR_SRC_B1 swapped >< -#define R_IIR_SRC_B1 0x0328 // Assume a typo in the docs and B0 is actually at 324, B1 at 328 in the HW. -#define R_MIX_DEST_A0 0x032C -#define R_MIX_DEST_A1 0x0330 -#define R_MIX_DEST_B0 0x0334 -#define R_MIX_DEST_B1 0x0338 +#define R_APF1_SIZE 0x02E4 // Feedback Source A +#define R_APF2_SIZE 0x02E8 // Feedback Source B +#define R_SAME_L_DST 0x02EC +#define R_SAME_R_DST 0x02F0 +#define R_COMB1_L_SRC 0x02F4 +#define R_COMB1_R_SRC 0x02F8 +#define R_COMB2_L_SRC 0x02FC +#define R_COMB2_R_SRC 0x0300 +#define R_SAME_L_SRC 0x0304 +#define R_SAME_R_SRC 0x0308 +#define R_DIFF_L_DST 0x030C +#define R_DIFF_R_DST 0x0310 +#define R_COMB3_L_SRC 0x0314 +#define R_COMB3_R_SRC 0x0318 +#define R_COMB4_L_SRC 0x031C +#define R_COMB4_R_SRC 0x0320 +#define R_DIFF_L_SRC 0x0324 // Some sources have R_DIFF_R_SRC and R_DIFF_L_SRC swapped >< +#define R_DIFF_R_SRC 0x0328 +#define R_APF1_L_DST 0x032C +#define R_APF1_R_DST 0x0330 +#define R_APF2_L_DST 0x0334 +#define R_APF2_R_DST 0x0338 #define REG_A_EEA 0x033C // Address: End address of working area for effects processing (upper part of address only!) #define REG_S_ENDX 0x0340 // End Point passed flag @@ -110,14 +110,14 @@ #define REG_P_MVOLXL 0x0770 // Current Master Volume Left #define REG_P_MVOLXR 0x0772 // Current Master Volume Right -#define R_IIR_ALPHA 0x0774 //IIR alpha (% used) -#define R_ACC_COEF_A 0x0776 -#define R_ACC_COEF_B 0x0778 -#define R_ACC_COEF_C 0x077A -#define R_ACC_COEF_D 0x077C -#define R_IIR_COEF 0x077E -#define R_FB_ALPHA 0x0780 //feedback alpha (% used) -#define R_FB_X 0x0782 //feedback +#define R_IIR_VOL 0x0774 +#define R_COMB1_VOL 0x0776 +#define R_COMB2_VOL 0x0778 +#define R_COMB3_VOL 0x077A +#define R_COMB4_VOL 0x077C +#define R_WALL_VOL 0x077E +#define R_APF1_VOL 0x0780 +#define R_APF2_VOL 0x0782 #define R_IN_COEF_L 0x0784 #define R_IN_COEF_R 0x0786 diff --git a/plugins/spu2-x/src/spu2sys.cpp b/plugins/spu2-x/src/spu2sys.cpp index 98e803bf72..a46cfface5 100644 --- a/plugins/spu2-x/src/spu2sys.cpp +++ b/plugins/spu2-x/src/spu2sys.cpp @@ -195,29 +195,29 @@ void V_Core::AnalyzeReverbPreset() ConLog("----------------------------------------------------------\n"); ConLog(" IN_COEF_L, IN_COEF_R 0x%08x, 0x%08x\n", Revb.IN_COEF_L, Revb.IN_COEF_R); - ConLog(" FB_SIZE_A, FB_SIZE_B 0x%08x, 0x%08x\n", Revb.FB_SIZE_A, Revb.FB_SIZE_B); - ConLog(" FB_ALPHA, FB_X 0x%08x, 0x%08x\n", Revb.FB_ALPHA, Revb.FB_X); + ConLog(" APF1_SIZE, APF2_SIZE 0x%08x, 0x%08x\n", Revb.APF1_SIZE, Revb.APF2_SIZE); + ConLog(" APF1_VOL, APF2_VOL 0x%08x, 0x%08x\n", Revb.APF1_VOL, Revb.APF2_VOL); - ConLog(" ACC_COEF_A 0x%08x\n", Revb.ACC_COEF_A); - ConLog(" ACC_COEF_B 0x%08x\n", Revb.ACC_COEF_B); - ConLog(" ACC_COEF_C 0x%08x\n", Revb.ACC_COEF_C); - ConLog(" ACC_COEF_D 0x%08x\n", Revb.ACC_COEF_D); + ConLog(" COMB1_VOL 0x%08x\n", Revb.COMB1_VOL); + ConLog(" COMB2_VOL 0x%08x\n", Revb.COMB2_VOL); + ConLog(" COMB3_VOL 0x%08x\n", Revb.COMB3_VOL); + ConLog(" COMB4_VOL 0x%08x\n", Revb.COMB4_VOL); - ConLog(" ACC_SRC_A0, ACC_SRC_A1 0x%08x, 0x%08x\n", Revb.ACC_SRC_A0, Revb.ACC_SRC_A1); - ConLog(" ACC_SRC_B0, ACC_SRC_B1 0x%08x, 0x%08x\n", Revb.ACC_SRC_B0, Revb.ACC_SRC_B1); - ConLog(" ACC_SRC_C0, ACC_SRC_C1 0x%08x, 0x%08x\n", Revb.ACC_SRC_C0, Revb.ACC_SRC_C1); - ConLog(" ACC_SRC_D0, ACC_SRC_D1 0x%08x, 0x%08x\n", Revb.ACC_SRC_D0, Revb.ACC_SRC_D1); + ConLog(" COMB1_L_SRC, COMB1_R_SRC 0x%08x, 0x%08x\n", Revb.COMB1_L_SRC, Revb.COMB1_R_SRC); + ConLog(" COMB2_L_SRC, COMB2_R_SRC 0x%08x, 0x%08x\n", Revb.COMB2_L_SRC, Revb.COMB2_R_SRC); + ConLog(" COMB3_L_SRC, COMB3_R_SRC 0x%08x, 0x%08x\n", Revb.COMB3_L_SRC, Revb.COMB3_R_SRC); + ConLog(" COMB4_L_SRC, COMB4_R_SRC 0x%08x, 0x%08x\n", Revb.COMB4_L_SRC, Revb.COMB4_R_SRC); - ConLog(" IIR_SRC_A0, IIR_SRC_A1 0x%08x, 0x%08x\n", Revb.IIR_SRC_A0, Revb.IIR_SRC_A1); - ConLog(" IIR_SRC_B0, IIR_SRC_B1 0x%08x, 0x%08x\n", Revb.IIR_SRC_B0, Revb.IIR_SRC_B1); - ConLog(" IIR_DEST_A0, IIR_DEST_A1 0x%08x, 0x%08x\n", Revb.IIR_DEST_A0, Revb.IIR_DEST_A1); - ConLog(" IIR_DEST_B0, IIR_DEST_B1 0x%08x, 0x%08x\n", Revb.IIR_DEST_B0, Revb.IIR_DEST_B1); - ConLog(" IIR_ALPHA, IIR_COEF 0x%08x, 0x%08x\n", Revb.IIR_ALPHA, Revb.IIR_COEF); + ConLog(" SAME_L_SRC, SAME_R_SRC 0x%08x, 0x%08x\n", Revb.SAME_L_SRC, Revb.SAME_R_SRC); + ConLog(" DIFF_L_SRC, DIFF_R_SRC 0x%08x, 0x%08x\n", Revb.DIFF_L_SRC, Revb.DIFF_R_SRC); + ConLog(" SAME_L_DST, SAME_R_DST 0x%08x, 0x%08x\n", Revb.SAME_L_DST, Revb.SAME_R_DST); + ConLog(" DIFF_L_DST, DIFF_R_DST 0x%08x, 0x%08x\n", Revb.DIFF_L_DST, Revb.DIFF_R_DST); + ConLog(" IIR_VOL, WALL_VOL 0x%08x, 0x%08x\n", Revb.IIR_VOL, Revb.WALL_VOL); - ConLog(" MIX_DEST_A0 0x%08x\n", Revb.MIX_DEST_A0); - ConLog(" MIX_DEST_A1 0x%08x\n", Revb.MIX_DEST_A1); - ConLog(" MIX_DEST_B0 0x%08x\n", Revb.MIX_DEST_B0); - ConLog(" MIX_DEST_B1 0x%08x\n", Revb.MIX_DEST_B1); + ConLog(" APF1_L_DST 0x%08x\n", Revb.APF1_L_DST); + ConLog(" APF1_R_DST 0x%08x\n", Revb.APF1_R_DST); + ConLog(" APF2_L_DST 0x%08x\n", Revb.APF2_L_DST); + ConLog(" APF2_R_DST 0x%08x\n", Revb.APF2_R_DST); ConLog(" EffectsBufferSize 0x%x\n", EffectsBufferSize); ConLog("----------------------------------------------------------\n"); @@ -269,39 +269,39 @@ void V_Core::UpdateEffectsBufferSize() AnalyzeReverbPreset(); // Rebuild buffer indexers. - RevBuffers.ACC_SRC_A0 = EffectsBufferIndexer(Revb.ACC_SRC_A0); - RevBuffers.ACC_SRC_A1 = EffectsBufferIndexer(Revb.ACC_SRC_A1); - RevBuffers.ACC_SRC_B0 = EffectsBufferIndexer(Revb.ACC_SRC_B0); - RevBuffers.ACC_SRC_B1 = EffectsBufferIndexer(Revb.ACC_SRC_B1); - RevBuffers.ACC_SRC_C0 = EffectsBufferIndexer(Revb.ACC_SRC_C0); - RevBuffers.ACC_SRC_C1 = EffectsBufferIndexer(Revb.ACC_SRC_C1); - RevBuffers.ACC_SRC_D0 = EffectsBufferIndexer(Revb.ACC_SRC_D0); - RevBuffers.ACC_SRC_D1 = EffectsBufferIndexer(Revb.ACC_SRC_D1); + RevBuffers.COMB1_L_SRC = EffectsBufferIndexer(Revb.COMB1_L_SRC); + RevBuffers.COMB1_R_SRC = EffectsBufferIndexer(Revb.COMB1_R_SRC); + RevBuffers.COMB2_L_SRC = EffectsBufferIndexer(Revb.COMB2_L_SRC); + RevBuffers.COMB2_R_SRC = EffectsBufferIndexer(Revb.COMB2_R_SRC); + RevBuffers.COMB3_L_SRC = EffectsBufferIndexer(Revb.COMB3_L_SRC); + RevBuffers.COMB3_R_SRC = EffectsBufferIndexer(Revb.COMB3_R_SRC); + RevBuffers.COMB4_L_SRC = EffectsBufferIndexer(Revb.COMB4_L_SRC); + RevBuffers.COMB4_R_SRC = EffectsBufferIndexer(Revb.COMB4_R_SRC); - RevBuffers.IIR_DEST_A0 = EffectsBufferIndexer(Revb.IIR_DEST_A0); - RevBuffers.IIR_DEST_A1 = EffectsBufferIndexer(Revb.IIR_DEST_A1); - RevBuffers.IIR_DEST_B0 = EffectsBufferIndexer(Revb.IIR_DEST_B0); - RevBuffers.IIR_DEST_B1 = EffectsBufferIndexer(Revb.IIR_DEST_B1); + RevBuffers.SAME_L_DST = EffectsBufferIndexer(Revb.SAME_L_DST); + RevBuffers.SAME_R_DST = EffectsBufferIndexer(Revb.SAME_R_DST); + RevBuffers.DIFF_L_DST = EffectsBufferIndexer(Revb.DIFF_L_DST); + RevBuffers.DIFF_R_DST = EffectsBufferIndexer(Revb.DIFF_R_DST); - RevBuffers.IIR_SRC_A0 = EffectsBufferIndexer(Revb.IIR_SRC_A0); - RevBuffers.IIR_SRC_A1 = EffectsBufferIndexer(Revb.IIR_SRC_A1); - RevBuffers.IIR_SRC_B0 = EffectsBufferIndexer(Revb.IIR_SRC_B0); - RevBuffers.IIR_SRC_B1 = EffectsBufferIndexer(Revb.IIR_SRC_B1); + RevBuffers.SAME_L_SRC = EffectsBufferIndexer(Revb.SAME_L_SRC); + RevBuffers.SAME_R_SRC = EffectsBufferIndexer(Revb.SAME_R_SRC); + RevBuffers.DIFF_L_SRC = EffectsBufferIndexer(Revb.DIFF_L_SRC); + RevBuffers.DIFF_R_SRC = EffectsBufferIndexer(Revb.DIFF_R_SRC); - RevBuffers.MIX_DEST_A0 = EffectsBufferIndexer(Revb.MIX_DEST_A0); - RevBuffers.MIX_DEST_A1 = EffectsBufferIndexer(Revb.MIX_DEST_A1); - RevBuffers.MIX_DEST_B0 = EffectsBufferIndexer(Revb.MIX_DEST_B0); - RevBuffers.MIX_DEST_B1 = EffectsBufferIndexer(Revb.MIX_DEST_B1); + RevBuffers.APF1_L_DST = EffectsBufferIndexer(Revb.APF1_L_DST); + RevBuffers.APF1_R_DST = EffectsBufferIndexer(Revb.APF1_R_DST); + RevBuffers.APF2_L_DST = EffectsBufferIndexer(Revb.APF2_L_DST); + RevBuffers.APF2_R_DST = EffectsBufferIndexer(Revb.APF2_R_DST); - RevBuffers.SAME_L_PRV = EffectsBufferIndexer(Revb.IIR_DEST_A0 - 1); - RevBuffers.SAME_R_PRV = EffectsBufferIndexer(Revb.IIR_DEST_A1 - 1); - RevBuffers.DIFF_L_PRV = EffectsBufferIndexer(Revb.IIR_DEST_B0 - 1); - RevBuffers.DIFF_R_PRV = EffectsBufferIndexer(Revb.IIR_DEST_B1 - 1); + RevBuffers.SAME_L_PRV = EffectsBufferIndexer(Revb.SAME_L_DST - 1); + RevBuffers.SAME_R_PRV = EffectsBufferIndexer(Revb.SAME_R_DST - 1); + RevBuffers.DIFF_L_PRV = EffectsBufferIndexer(Revb.DIFF_L_DST - 1); + RevBuffers.DIFF_R_PRV = EffectsBufferIndexer(Revb.DIFF_R_DST - 1); - RevBuffers.APF1_L_SRC = EffectsBufferIndexer(Revb.MIX_DEST_A0 - Revb.FB_SIZE_A); - RevBuffers.APF1_R_SRC = EffectsBufferIndexer(Revb.MIX_DEST_A1 - Revb.FB_SIZE_A); - RevBuffers.APF2_L_SRC = EffectsBufferIndexer(Revb.MIX_DEST_B0 - Revb.FB_SIZE_B); - RevBuffers.APF2_R_SRC = EffectsBufferIndexer(Revb.MIX_DEST_B1 - Revb.FB_SIZE_B); + RevBuffers.APF1_L_SRC = EffectsBufferIndexer(Revb.APF1_L_DST - Revb.APF1_SIZE); + RevBuffers.APF1_R_SRC = EffectsBufferIndexer(Revb.APF1_R_DST - Revb.APF1_SIZE); + RevBuffers.APF2_L_SRC = EffectsBufferIndexer(Revb.APF2_L_DST - Revb.APF2_SIZE); + RevBuffers.APF2_R_SRC = EffectsBufferIndexer(Revb.APF2_R_DST - Revb.APF2_SIZE); } void V_Voice::QueueStart() @@ -714,94 +714,94 @@ void V_Core::WriteRegPS1(u32 mem, u16 value) break; case 0x1DC0: - Revb.FB_SIZE_A = value * 4; + Revb.APF1_SIZE = value * 4; break; case 0x1DC2: - Revb.FB_SIZE_B = value * 4; + Revb.APF2_SIZE = value * 4; break; case 0x1DC4: - Revb.IIR_ALPHA = value; + Revb.IIR_VOL = value; break; case 0x1DC6: - Revb.ACC_COEF_A = value; + Revb.COMB1_VOL = value; break; case 0x1DC8: - Revb.ACC_COEF_B = value; + Revb.COMB2_VOL = value; break; case 0x1DCA: - Revb.ACC_COEF_C = value; + Revb.COMB3_VOL = value; break; case 0x1DCC: - Revb.ACC_COEF_D = value; + Revb.COMB4_VOL = value; break; case 0x1DCE: - Revb.IIR_COEF = value; + Revb.WALL_VOL = value; break; case 0x1DD0: - Revb.FB_ALPHA = value; + Revb.APF1_VOL = value; break; case 0x1DD2: - Revb.FB_X = value; + Revb.APF2_VOL = value; break; case 0x1DD4: - Revb.IIR_DEST_A0 = value * 4; + Revb.SAME_L_DST = value * 4; break; case 0x1DD6: - Revb.IIR_DEST_A1 = value * 4; + Revb.SAME_R_DST = value * 4; break; case 0x1DD8: - Revb.ACC_SRC_A0 = value * 4; + Revb.COMB1_L_SRC = value * 4; break; case 0x1DDA: - Revb.ACC_SRC_A1 = value * 4; + Revb.COMB1_R_SRC = value * 4; break; case 0x1DDC: - Revb.ACC_SRC_B0 = value * 4; + Revb.COMB2_L_SRC = value * 4; break; case 0x1DDE: - Revb.ACC_SRC_B1 = value * 4; + Revb.COMB2_R_SRC = value * 4; break; case 0x1DE0: - Revb.IIR_SRC_A0 = value * 4; + Revb.SAME_L_SRC = value * 4; break; case 0x1DE2: - Revb.IIR_SRC_A1 = value * 4; + Revb.SAME_R_SRC = value * 4; break; case 0x1DE4: - Revb.IIR_DEST_B0 = value * 4; + Revb.DIFF_L_DST = value * 4; break; case 0x1DE6: - Revb.IIR_DEST_B1 = value * 4; + Revb.DIFF_R_DST = value * 4; break; case 0x1DE8: - Revb.ACC_SRC_C0 = value * 4; + Revb.COMB3_L_SRC = value * 4; break; case 0x1DEA: - Revb.ACC_SRC_C1 = value * 4; + Revb.COMB3_R_SRC = value * 4; break; case 0x1DEC: - Revb.ACC_SRC_D0 = value * 4; + Revb.COMB4_L_SRC = value * 4; break; case 0x1DEE: - Revb.ACC_SRC_D1 = value * 4; + Revb.COMB4_R_SRC = value * 4; break; case 0x1DF0: - Revb.IIR_SRC_B0 = value * 4; - break; // IIR_SRC_B0 and IIR_SRC_B1 supposedly swapped on SPU2 + Revb.DIFF_L_SRC = value * 4; + break; // DIFF_R_SRC and DIFF_L_SRC supposedly swapped on SPU2 case 0x1DF2: - Revb.IIR_SRC_B1 = value * 4; + Revb.DIFF_R_SRC = value * 4; break; // but I don't believe it! (games in psxmode sound better unswapped) case 0x1DF4: - Revb.MIX_DEST_A0 = value * 4; + Revb.APF1_L_DST = value * 4; break; case 0x1DF6: - Revb.MIX_DEST_A1 = value * 4; + Revb.APF1_R_DST = value * 4; break; case 0x1DF8: - Revb.MIX_DEST_B0 = value * 4; + Revb.APF2_L_DST = value * 4; break; case 0x1DFA: - Revb.MIX_DEST_B1 = value * 4; + Revb.APF2_R_DST = value * 4; break; case 0x1DFC: Revb.IN_COEF_L = value; @@ -1545,28 +1545,28 @@ static RegWriteHandler *const tbl_reg_writes[0x401] = CoreParamsPair(0, REG_A_ESA), - ReverbPair(0, R_FB_SIZE_A), // 0x02E4 // Feedback Source A - ReverbPair(0, R_FB_SIZE_B), // 0x02E8 // Feedback Source B - ReverbPair(0, R_IIR_DEST_A0), // 0x02EC - ReverbPair(0, R_IIR_DEST_A1), // 0x02F0 - ReverbPair(0, R_ACC_SRC_A0), // 0x02F4 - ReverbPair(0, R_ACC_SRC_A1), // 0x02F8 - ReverbPair(0, R_ACC_SRC_B0), // 0x02FC - ReverbPair(0, R_ACC_SRC_B1), // 0x0300 - ReverbPair(0, R_IIR_SRC_A0), // 0x0304 - ReverbPair(0, R_IIR_SRC_A1), // 0x0308 - ReverbPair(0, R_IIR_DEST_B0), // 0x030C - ReverbPair(0, R_IIR_DEST_B1), // 0x0310 - ReverbPair(0, R_ACC_SRC_C0), // 0x0314 - ReverbPair(0, R_ACC_SRC_C1), // 0x0318 - ReverbPair(0, R_ACC_SRC_D0), // 0x031C - ReverbPair(0, R_ACC_SRC_D1), // 0x0320 - ReverbPair(0, R_IIR_SRC_B0), // 0x0324 - ReverbPair(0, R_IIR_SRC_B1), // 0x0328 - ReverbPair(0, R_MIX_DEST_A0), // 0x032C - ReverbPair(0, R_MIX_DEST_A1), // 0x0330 - ReverbPair(0, R_MIX_DEST_B0), // 0x0334 - ReverbPair(0, R_MIX_DEST_B1), // 0x0338 + ReverbPair(0, R_APF1_SIZE), // 0x02E4 // Feedback Source A + ReverbPair(0, R_APF2_SIZE), // 0x02E8 // Feedback Source B + ReverbPair(0, R_SAME_L_DST), // 0x02EC + ReverbPair(0, R_SAME_R_DST), // 0x02F0 + ReverbPair(0, R_COMB1_L_SRC), // 0x02F4 + ReverbPair(0, R_COMB1_R_SRC), // 0x02F8 + ReverbPair(0, R_COMB2_L_SRC), // 0x02FC + ReverbPair(0, R_COMB2_R_SRC), // 0x0300 + ReverbPair(0, R_SAME_L_SRC), // 0x0304 + ReverbPair(0, R_SAME_R_SRC), // 0x0308 + ReverbPair(0, R_DIFF_L_DST), // 0x030C + ReverbPair(0, R_DIFF_R_DST), // 0x0310 + ReverbPair(0, R_COMB3_L_SRC), // 0x0314 + ReverbPair(0, R_COMB3_R_SRC), // 0x0318 + ReverbPair(0, R_COMB4_L_SRC), // 0x031C + ReverbPair(0, R_COMB4_R_SRC), // 0x0320 + ReverbPair(0, R_DIFF_L_SRC), // 0x0324 + ReverbPair(0, R_DIFF_R_SRC), // 0x0328 + ReverbPair(0, R_APF1_L_DST), // 0x032C + ReverbPair(0, R_APF1_R_DST), // 0x0330 + ReverbPair(0, R_APF2_L_DST), // 0x0334 + ReverbPair(0, R_APF2_R_DST), // 0x0338 RegWrite_Core<0, REG_A_EEA>, RegWrite_Null, @@ -1635,28 +1635,28 @@ static RegWriteHandler *const tbl_reg_writes[0x401] = CoreParamsPair(1, REG_A_ESA), - ReverbPair(1, R_FB_SIZE_A), // 0x02E4 // Feedback Source A - ReverbPair(1, R_FB_SIZE_B), // 0x02E8 // Feedback Source B - ReverbPair(1, R_IIR_DEST_A0), // 0x02EC - ReverbPair(1, R_IIR_DEST_A1), // 0x02F0 - ReverbPair(1, R_ACC_SRC_A0), // 0x02F4 - ReverbPair(1, R_ACC_SRC_A1), // 0x02F8 - ReverbPair(1, R_ACC_SRC_B0), // 0x02FC - ReverbPair(1, R_ACC_SRC_B1), // 0x0300 - ReverbPair(1, R_IIR_SRC_A0), // 0x0304 - ReverbPair(1, R_IIR_SRC_A1), // 0x0308 - ReverbPair(1, R_IIR_DEST_B0), // 0x030C - ReverbPair(1, R_IIR_DEST_B1), // 0x0310 - ReverbPair(1, R_ACC_SRC_C0), // 0x0314 - ReverbPair(1, R_ACC_SRC_C1), // 0x0318 - ReverbPair(1, R_ACC_SRC_D0), // 0x031C - ReverbPair(1, R_ACC_SRC_D1), // 0x0320 - ReverbPair(1, R_IIR_SRC_B0), // 0x0324 - ReverbPair(1, R_IIR_SRC_B1), // 0x0328 - ReverbPair(1, R_MIX_DEST_A0), // 0x032C - ReverbPair(1, R_MIX_DEST_A1), // 0x0330 - ReverbPair(1, R_MIX_DEST_B0), // 0x0334 - ReverbPair(1, R_MIX_DEST_B1), // 0x0338 + ReverbPair(1, R_APF1_SIZE), // 0x02E4 // Feedback Source A + ReverbPair(1, R_APF2_SIZE), // 0x02E8 // Feedback Source B + ReverbPair(1, R_SAME_L_DST), // 0x02EC + ReverbPair(1, R_SAME_R_DST), // 0x02F0 + ReverbPair(1, R_COMB1_L_SRC), // 0x02F4 + ReverbPair(1, R_COMB1_R_SRC), // 0x02F8 + ReverbPair(1, R_COMB2_L_SRC), // 0x02FC + ReverbPair(1, R_COMB2_R_SRC), // 0x0300 + ReverbPair(1, R_SAME_L_SRC), // 0x0304 + ReverbPair(1, R_SAME_R_SRC), // 0x0308 + ReverbPair(1, R_DIFF_L_DST), // 0x030C + ReverbPair(1, R_DIFF_R_DST), // 0x0310 + ReverbPair(1, R_COMB3_L_SRC), // 0x0314 + ReverbPair(1, R_COMB3_R_SRC), // 0x0318 + ReverbPair(1, R_COMB4_L_SRC), // 0x031C + ReverbPair(1, R_COMB4_R_SRC), // 0x0320 + ReverbPair(1, R_DIFF_R_SRC), // 0x0324 + ReverbPair(1, R_DIFF_L_SRC), // 0x0328 + ReverbPair(1, R_APF1_L_DST), // 0x032C + ReverbPair(1, R_APF1_R_DST), // 0x0330 + ReverbPair(1, R_APF2_L_DST), // 0x0334 + ReverbPair(1, R_APF2_R_DST), // 0x0338 RegWrite_Core<1, REG_A_EEA>, RegWrite_Null, @@ -1681,16 +1681,16 @@ static RegWriteHandler *const tbl_reg_writes[0x401] = RegWrite_CoreExt<0, REG_P_MVOLXL>, // 0x0770 // Current Master Volume Left RegWrite_CoreExt<0, REG_P_MVOLXR>, // 0x0772 // Current Master Volume Right - RegWrite_CoreExt<0, R_IIR_ALPHA>, // 0x0774 //IIR alpha (% used) - RegWrite_CoreExt<0, R_ACC_COEF_A>, // 0x0776 - RegWrite_CoreExt<0, R_ACC_COEF_B>, // 0x0778 - RegWrite_CoreExt<0, R_ACC_COEF_C>, // 0x077A - RegWrite_CoreExt<0, R_ACC_COEF_D>, // 0x077C - RegWrite_CoreExt<0, R_IIR_COEF>, // 0x077E - RegWrite_CoreExt<0, R_FB_ALPHA>, // 0x0780 //feedback alpha (% used) - RegWrite_CoreExt<0, R_FB_X>, // 0x0782 //feedback - RegWrite_CoreExt<0, R_IN_COEF_L>, // 0x0784 - RegWrite_CoreExt<0, R_IN_COEF_R>, // 0x0786 + RegWrite_CoreExt<0, R_IIR_VOL>, // 0x0774 //IIR alpha (% used) + RegWrite_CoreExt<0, R_COMB1_VOL>, // 0x0776 + RegWrite_CoreExt<0, R_COMB2_VOL>, // 0x0778 + RegWrite_CoreExt<0, R_COMB3_VOL>, // 0x077A + RegWrite_CoreExt<0, R_COMB4_VOL>, // 0x077C + RegWrite_CoreExt<0, R_WALL_VOL>, // 0x077E + RegWrite_CoreExt<0, R_APF1_VOL>, // 0x0780 //feedback alpha (% used) + RegWrite_CoreExt<0, R_APF2_VOL>, // 0x0782 //feedback + RegWrite_CoreExt<0, R_IN_COEF_L>, // 0x0784 + RegWrite_CoreExt<0, R_IN_COEF_R>, // 0x0786 // ------ ------- @@ -1705,16 +1705,16 @@ static RegWriteHandler *const tbl_reg_writes[0x401] = RegWrite_CoreExt<1, REG_P_MVOLXL>, // 0x0770 // Current Master Volume Left RegWrite_CoreExt<1, REG_P_MVOLXR>, // 0x0772 // Current Master Volume Right - RegWrite_CoreExt<1, R_IIR_ALPHA>, // 0x0774 //IIR alpha (% used) - RegWrite_CoreExt<1, R_ACC_COEF_A>, // 0x0776 - RegWrite_CoreExt<1, R_ACC_COEF_B>, // 0x0778 - RegWrite_CoreExt<1, R_ACC_COEF_C>, // 0x077A - RegWrite_CoreExt<1, R_ACC_COEF_D>, // 0x077C - RegWrite_CoreExt<1, R_IIR_COEF>, // 0x077E - RegWrite_CoreExt<1, R_FB_ALPHA>, // 0x0780 //feedback alpha (% used) - RegWrite_CoreExt<1, R_FB_X>, // 0x0782 //feedback - RegWrite_CoreExt<1, R_IN_COEF_L>, // 0x0784 - RegWrite_CoreExt<1, R_IN_COEF_R>, // 0x0786 + RegWrite_CoreExt<1, R_IIR_VOL>, // 0x0774 //IIR alpha (% used) + RegWrite_CoreExt<1, R_COMB1_VOL>, // 0x0776 + RegWrite_CoreExt<1, R_COMB2_VOL>, // 0x0778 + RegWrite_CoreExt<1, R_COMB3_VOL>, // 0x077A + RegWrite_CoreExt<1, R_COMB4_VOL>, // 0x077C + RegWrite_CoreExt<1, R_WALL_VOL>, // 0x077E + RegWrite_CoreExt<1, R_APF1_VOL>, // 0x0780 //feedback alpha (% used) + RegWrite_CoreExt<1, R_APF2_VOL>, // 0x0782 //feedback + RegWrite_CoreExt<1, R_IN_COEF_L>, // 0x0784 + RegWrite_CoreExt<1, R_IN_COEF_R>, // 0x0786 REGRAW(0x7B0), REGRAW(0x7B2), REGRAW(0x7B4), REGRAW(0x7B6), REGRAW(0x7B8), REGRAW(0x7BA), REGRAW(0x7BC), REGRAW(0x7BE),