mirror of https://github.com/PCSX2/pcsx2.git
microVU:
- Fixed xmm reg corruption when calling console print functions from recompiler (win-vista+ clobber some xmm regs) - Tweaked and commented regalloc class git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3723 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
c2681d7baa
commit
147e4b8409
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@ -65,7 +65,7 @@ public:
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if (!thisBlock) {
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listI++;
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microBlockLink* newBlock = (microBlockLink*)_aligned_malloc(sizeof(microBlockLink), 16);
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memzero(*newBlock);
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newBlock->next = NULL;
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if (blockEnd) {
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blockEnd->next = newBlock;
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@ -160,8 +160,8 @@ struct microVU {
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__aligned16 u32 macFlag[4]; // 4 instances of mac flag (used in execution)
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__aligned16 u32 clipFlag[4]; // 4 instances of clip flag (used in execution)
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__aligned16 u32 xmmPQb[4]; // Backup for xmmPQ
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__aligned16 u32 xmmCTemp[4]; // Backup used in mVUclamp2()
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__aligned16 u32 xmmBackup[8][4]; // Backup for xmm0~xmm7
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u32 index; // VU Index (VU0 or VU1)
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u32 cop2; // VU is in COP2 mode? (No/Yes)
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@ -19,12 +19,12 @@
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// Messages Called at Execution Time...
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//------------------------------------------------------------------
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static void __fastcall mVUbadOp0(mV, u32 PC) { Console.Error("microVU0 Warning: Exiting... Block started with illegal opcode. [%04x] [%x]", PC, mVU->prog.cur->idx); }
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static void __fastcall mVUbadOp1(mV, u32 PC) { Console.Error("microVU1 Warning: Exiting... Block started with illegal opcode. [%04x] [%x]", PC, mVU->prog.cur->idx); }
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static void __fastcall mVUwarning0(mV) { Console.Error("microVU0 Warning: Exiting from Possible Infinite Loop [%04x] [%x]", mVU->prog.cur->idx); }
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static void __fastcall mVUwarning1(mV) { Console.Error("microVU1 Warning: Exiting from Possible Infinite Loop [%04x] [%x]", mVU->prog.cur->idx); }
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static void __fastcall mVUprintPC1(u32 PC) { Console.WriteLn("Block Start PC = 0x%04x", PC); }
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static void __fastcall mVUprintPC2(u32 PC) { Console.WriteLn("Block End PC = 0x%04x", PC); }
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static void __fastcall mVUbadOp0(u32 prog, u32 pc) { Console.Error("microVU0 Warning: Exiting... Block started with illegal opcode. [%04x] [%x]", pc, prog); }
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static void __fastcall mVUbadOp1(u32 prog, u32 pc) { Console.Error("microVU1 Warning: Exiting... Block started with illegal opcode. [%04x] [%x]", pc, prog); }
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static void __fastcall mVUwarning0(u32 prog) { Console.Error("microVU0 Warning: Exiting from Possible Infinite Loop [%04x] [%x]", prog); }
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static void __fastcall mVUwarning1(u32 prog) { Console.Error("microVU1 Warning: Exiting from Possible Infinite Loop [%04x] [%x]", prog); }
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static void __fastcall mVUprintPC1(u32 pc) { Console.WriteLn("Block Start PC = 0x%04x", pc); }
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static void __fastcall mVUprintPC2(u32 pc) { Console.WriteLn("Block End PC = 0x%04x", pc); }
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//------------------------------------------------------------------
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// Program Range Checking and Setting up Ranges
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@ -170,10 +170,12 @@ static __fi void mVUcheckBadOp(mV) {
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// Prints msg when exiting block early if 1st op was a bad opcode (Dawn of Mana Level 2)
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static __fi void handleBadOp(mV, int count) {
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if (mVUinfo.isBadOp && count == 0) {
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xMOV(gprT2, (uptr)mVU);
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mVUbackupRegs(mVU, true);
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xMOV(gprT2, mVU->prog.cur->idx);
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xMOV(gprT3, xPC);
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if (!isVU1) xCALL(mVUbadOp0);
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else xCALL(mVUbadOp1);
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mVUrestoreRegs(mVU, true);
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}
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}
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@ -313,9 +315,11 @@ void mVUsetCycles(mV) {
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// Prints Start/End PC of blocks executed, for debugging...
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static void mVUdebugPrintBlocks(microVU* mVU, bool isEndPC) {
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if (mVUdebugNow) {
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mVUbackupRegs(mVU, true);
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xMOV(gprT2, xPC);
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if (isEndPC) xCALL(mVUprintPC2);
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else xCALL(mVUprintPC1);
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mVUrestoreRegs(mVU, true);
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}
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}
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@ -341,15 +345,19 @@ static void mVUtestCycles(microVU* mVU) {
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if (isVU0) {
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// TEST32ItoM((uptr)&mVU->regs().flags, VUFLAG_MFLAGSET);
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// xFowardJZ32 vu0jmp;
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// xMOV(gprT2, (uptr)mVU);
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// mVUbackupRegs(mVU, true);
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// xMOV(gprT2, mVU->prog.cur->idx);
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// xCALL(mVUwarning0); // VU0 is allowed early exit for COP2 Interlock Simulation
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// mVUbackupRegs(mVU, true);
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mVUsavePipelineState(mVU);
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mVUendProgram(mVU, NULL, 0);
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// vu0jmp.SetTarget();
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}
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else {
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xMOV(gprT2, (uptr)mVU);
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mVUbackupRegs(mVU, true);
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xMOV(gprT2, mVU->prog.cur->idx);
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xCALL(mVUwarning1);
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mVUbackupRegs(mVU, true);
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mVUsavePipelineState(mVU);
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mVUendProgram(mVU, NULL, 0);
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}
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@ -28,7 +28,7 @@ union regInfo {
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// microRegInfo is carefully ordered for faster compares. The "important" information is
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// housed in a union that is accessed via 'quick32' so that several u8 fields can be compared
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// using a pair of 32-bit equalities.
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// vi15 is only used if microVU constprop is enabled (it is *not* by default). When constprop
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// vi15 is only used if microVU const-prop is enabled (it is *not* by default). When constprop
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// is disabled the vi15 field acts as additional padding that is required for 16 byte alignment
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// needed by the xmm compare.
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union __aligned16 microRegInfo {
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@ -44,6 +44,7 @@ union __aligned16 microRegInfo {
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u8 xgkick;
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u8 viBackUp; // VI reg number that was written to on branch-delay slot
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u8 blockType; // 0 = Normal; 1,2 = Compile one instruction (E-bit/Branch Ending)
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u8 r;
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};
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u32 quick32[2];
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};
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@ -51,7 +52,6 @@ union __aligned16 microRegInfo {
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struct {
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u8 VI[16];
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regInfo VF[32];
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u8 r;
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};
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};
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@ -60,7 +60,7 @@ union __aligned16 microRegInfo {
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u32 full32[160/sizeof(u32)];
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};
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C_ASSERT( sizeof(microRegInfo) == 160 );
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C_ASSERT(sizeof(microRegInfo) == 160);
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struct __aligned16 microBlock {
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microRegInfo pState; // Detailed State of Pipeline
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@ -202,7 +202,7 @@ protected:
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}
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int findFreeRegRec(int startIdx) {
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for (int i = startIdx; i < xmmTotal; i++) {
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for(int i = startIdx; i < xmmTotal; i++) {
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if (!xmmMap[i].isNeeded) {
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int x = findFreeRegRec(i+1);
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if (x == -1) return i;
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@ -213,7 +213,7 @@ protected:
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}
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int findFreeReg() {
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for (int i = 0; i < xmmTotal; i++) {
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for(int i = 0; i < xmmTotal; i++) {
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if (!xmmMap[i].isNeeded && (xmmMap[i].VFreg < 0)) {
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return i; // Reg is not needed and was a temp reg
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}
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@ -228,15 +228,19 @@ public:
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index = _index;
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}
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// Fully resets the regalloc by clearing all cached data
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void reset() {
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for (int i = 0; i < xmmTotal; i++) {
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for(int i = 0; i < xmmTotal; i++) {
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clearReg(i);
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}
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counter = 0;
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}
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// Flushes all allocated registers (i.e. writes-back to memory all modified registers).
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// If clearState is 0, then it keeps cached reg data valid
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// If clearState is 1, then it invalidates all cached reg data after write-back
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void flushAll(bool clearState = 1) {
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for (int i = 0; i < xmmTotal; i++) {
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for(int i = 0; i < xmmTotal; i++) {
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writeBackReg(xmm(i));
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if (clearState) clearReg(i);
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}
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@ -244,7 +248,7 @@ public:
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void clearReg(const xmm& reg) { clearReg(reg.Id); }
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void clearReg(int regId) {
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microMapXMM& clear( xmmMap[regId] );
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microMapXMM& clear = xmmMap[regId];
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clear.VFreg = -1;
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clear.count = 0;
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clear.xyzw = 0;
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@ -252,95 +256,115 @@ public:
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}
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void clearRegVF(int VFreg) {
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for (int i = 0; i < xmmTotal; i++) {
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for(int i = 0; i < xmmTotal; i++) {
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if (xmmMap[i].VFreg == VFreg) clearReg(i);
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}
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}
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// Writes back modified reg to memory.
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// If all vectors modified, then keeps the VF reg cached in the xmm register.
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// If reg was not modified, then keeps the VF reg cached in the xmm register.
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void writeBackReg(const xmm& reg, bool invalidateRegs = 1) {
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microMapXMM& write( xmmMap[reg.Id] );
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microMapXMM& mapX = xmmMap[reg.Id];
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if ((write.VFreg > 0) && write.xyzw) { // Reg was modified and not Temp or vf0
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if (write.VFreg == 33) xMOVSS(ptr32[&getVI(REG_I)], reg);
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else if (write.VFreg == 32) mVUsaveReg(reg, ptr[®s().ACC], write.xyzw, 1);
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else mVUsaveReg(reg, ptr[&getVF(write.VFreg)], write.xyzw, 1);
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if ((mapX.VFreg > 0) && mapX.xyzw) { // Reg was modified and not Temp or vf0
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if (mapX.VFreg == 33) xMOVSS(ptr32[&getVI(REG_I)], reg);
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elif (mapX.VFreg == 32) mVUsaveReg(reg, ptr[®s().ACC], mapX.xyzw, 1);
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else mVUsaveReg(reg, ptr[&getVF(mapX.VFreg)], mapX.xyzw, 1);
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if (invalidateRegs) {
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for (int i = 0; i < xmmTotal; i++) {
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microMapXMM& imap (xmmMap[i]);
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if ((i == reg.Id) || imap.isNeeded) continue;
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if (imap.VFreg == write.VFreg) {
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if (imap.xyzw && imap.xyzw < 0xf) DevCon.Error("microVU Error: writeBackReg() [%d]", imap.VFreg);
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for(int i = 0; i < xmmTotal; i++) {
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microMapXMM& mapI = xmmMap[i];
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if ((i == reg.Id) || mapI.isNeeded) continue;
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if (mapI.VFreg == mapX.VFreg) {
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if (mapI.xyzw && mapI.xyzw < 0xf) DevCon.Error("microVU Error: writeBackReg() [%d]", mapI.VFreg);
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clearReg(i); // Invalidate any Cached Regs of same vf Reg
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}
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}
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}
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if (write.xyzw == 0xf) { // Make Cached Reg if All Vectors were Modified
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write.count = counter;
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write.xyzw = 0;
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write.isNeeded = 0;
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if (mapX.xyzw == 0xf) { // Make Cached Reg if All Vectors were Modified
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mapX.count = counter;
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mapX.xyzw = 0;
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mapX.isNeeded = 0;
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return;
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}
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clearReg(reg);
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}
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clearReg(reg); // Clear Reg
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elif (mapX.xyzw) clearReg(reg); // Clear reg if modified and is VF0 or temp reg...
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}
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// Use this when done using the allocated register, it clears its "Needed" status.
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// The register that was written to, should be cleared before other registers are cleared.
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// This is to guarantee proper merging between registers... When a written-to reg is cleared,
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// it invalidates other cached registers of the same VF reg, and merges partial-vector
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// writes into them.
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void clearNeeded(const xmm& reg) {
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if ((reg.Id < 0) || (reg.Id >= xmmTotal)) return;
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if ((reg.Id < 0) || (reg.Id >= xmmTotal)) return; // Sometimes xmmPQ hits this
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microMapXMM& clear (xmmMap[reg.Id]);
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microMapXMM& clear = xmmMap[reg.Id];
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clear.isNeeded = 0;
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if (clear.xyzw) { // Reg was modified
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if (clear.VFreg > 0) {
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int mergeRegs = 0;
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if (clear.xyzw < 0xf) { mergeRegs = 1; } // Try to merge partial writes
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for (int i = 0; i < xmmTotal; i++) { // Invalidate any other read-only regs of same vfReg
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if (clear.xyzw < 0xf) mergeRegs = 1; // Try to merge partial writes
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for(int i = 0; i < xmmTotal; i++) { // Invalidate any other read-only regs of same vfReg
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if (i == reg.Id) continue;
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microMapXMM& imap (xmmMap[i]);
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if (imap.VFreg == clear.VFreg) {
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if (imap.xyzw && imap.xyzw < 0xf) DevCon.Error("microVU Error: clearNeeded() [%d]", imap.VFreg);
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microMapXMM& mapI = xmmMap[i];
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if (mapI.VFreg == clear.VFreg) {
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if (mapI.xyzw && mapI.xyzw < 0xf) {
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DevCon.Error("microVU Error: clearNeeded() [%d]", mapI.VFreg);
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}
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if (mergeRegs == 1) {
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mVUmergeRegs(xmm(i), reg, clear.xyzw, 1);
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imap.xyzw = 0xf;
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imap.count = counter;
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mapI.xyzw = 0xf;
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mapI.count = counter;
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mergeRegs = 2;
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}
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else clearReg(i);
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else clearReg(i); // Clears when mergeRegs is 0 or 2
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}
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}
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if (mergeRegs == 2) clearReg(reg); // Clear Current Reg if Merged
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else if (mergeRegs) writeBackReg(reg); // Write Back Partial Writes if couldn't merge
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if (mergeRegs==2) clearReg(reg); // Clear Current Reg if Merged
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elif (mergeRegs==1) writeBackReg(reg); // Write Back Partial Writes if couldn't merge
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}
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else clearReg(reg); // If Reg was temp or vf0, then invalidate itself
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}
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}
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// vfLoadReg = VF reg to be loaded to the xmm register
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// vfWriteReg = VF reg that the returned xmm register will be considered as
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// xyzw = XYZW vectors that will be modified (and loaded)
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// cloneWrite = When loading a reg that will be written to,
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// it copies it to its own xmm reg instead of overwriting the cached one...
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// Notes:
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// To load a temp reg use the default param values, vfLoadReg = -1 and vfWriteReg = -1.
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// To load a full reg which won't be modified and you want cached, specify vfLoadReg >= 0 and vfWriteReg = -1
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// To load a reg which you don't want written back or cached, specify vfLoadReg >= 0 and vfWriteReg = 0
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const xmm& allocReg(int vfLoadReg = -1, int vfWriteReg = -1, int xyzw = 0, bool cloneWrite = 1) {
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//DevCon.WriteLn("vfLoadReg = %02d, vfWriteReg = %02d, xyzw = %x, clone = %d",vfLoadReg,vfWriteReg,xyzw,(int)cloneWrite);
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counter++;
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if (vfLoadReg >= 0) { // Search For Cached Regs
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for (int i = 0; i < xmmTotal; i++) {
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const xmm& xmmi(xmm::GetInstance(i));
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microMapXMM& imap (xmmMap[i]);
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if ((imap.VFreg == vfLoadReg) && (!imap.xyzw // Reg Was Not Modified
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|| (imap.VFreg && (imap.xyzw==0xf)))) { // Reg Had All Vectors Modified and != VF0
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for(int i = 0; i < xmmTotal; i++) {
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const xmm& xmmI = xmm::GetInstance(i);
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microMapXMM& mapI = xmmMap[i];
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if ((mapI.VFreg == vfLoadReg) && (!mapI.xyzw // Reg Was Not Modified
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|| (mapI.VFreg && (mapI.xyzw==0xf)))) { // Reg Had All Vectors Modified and != VF0
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int z = i;
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if (vfWriteReg >= 0) { // Reg will be modified
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if (cloneWrite) { // Clone Reg so as not to use the same Cached Reg
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z = findFreeReg();
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const xmm& xmmz(xmm::GetInstance(z));
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writeBackReg(xmmz);
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if (z!=i && xyzw==8) xMOVAPS (xmmz, xmmi);
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else if (xyzw == 4) xPSHUF.D(xmmz, xmmi, 1);
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else if (xyzw == 2) xPSHUF.D(xmmz, xmmi, 2);
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else if (xyzw == 1) xPSHUF.D(xmmz, xmmi, 3);
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else if (z != i) xMOVAPS (xmmz, xmmi);
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imap.count = counter; // Reg i was used, so update counter
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const xmm& xmmZ = xmm::GetInstance(z);
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writeBackReg(xmmZ);
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if (xyzw == 4) xPSHUF.D(xmmZ, xmmI, 1);
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elif (xyzw == 2) xPSHUF.D(xmmZ, xmmI, 2);
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elif (xyzw == 1) xPSHUF.D(xmmZ, xmmI, 3);
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elif (z != i) xMOVAPS (xmmZ, xmmI);
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mapI.count = counter; // Reg i was used, so update counter
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}
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else { // Don't clone reg, but shuffle to adjust for SS ops
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if ((vfLoadReg != vfWriteReg) || (xyzw != 0xf)) { writeBackReg(xmmi); }
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if (xyzw == 4) xPSHUF.D(xmmi, xmmi, 1);
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else if (xyzw == 2) xPSHUF.D(xmmi, xmmi, 2);
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else if (xyzw == 1) xPSHUF.D(xmmi, xmmi, 3);
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if ((vfLoadReg!=vfWriteReg)||(xyzw!=0xf)) writeBackReg(xmmI);
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if (xyzw == 4) xPSHUF.D(xmmI, xmmI, 1);
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elif (xyzw == 2) xPSHUF.D(xmmI, xmmI, 2);
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elif (xyzw == 1) xPSHUF.D(xmmI, xmmI, 3);
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}
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xmmMap[z].VFreg = vfWriteReg;
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xmmMap[z].xyzw = xyzw;
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@ -352,26 +376,26 @@ public:
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}
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}
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int x = findFreeReg();
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const xmm& xmmx = xmm::GetInstance(x);
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writeBackReg(xmmx);
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const xmm& xmmX = xmm::GetInstance(x);
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writeBackReg(xmmX);
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if (vfWriteReg >= 0) { // Reg Will Be Modified (allow partial reg loading)
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if ((vfLoadReg == 0) && !(xyzw & 1)) { xPXOR(xmmx, xmmx); }
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else if (vfLoadReg == 33) loadIreg (xmmx, xyzw);
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else if (vfLoadReg == 32) mVUloadReg(xmmx, ptr[®s().ACC], xyzw);
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else if (vfLoadReg >= 0) mVUloadReg(xmmx, ptr[&getVF(vfLoadReg)], xyzw);
|
||||
if ((vfLoadReg == 0) && !(xyzw & 1)) xPXOR(xmmX, xmmX);
|
||||
elif (vfLoadReg == 33) loadIreg (xmmX, xyzw);
|
||||
elif (vfLoadReg == 32) mVUloadReg(xmmX, ptr[®s().ACC], xyzw);
|
||||
elif (vfLoadReg >= 0) mVUloadReg(xmmX, ptr[&getVF(vfLoadReg)], xyzw);
|
||||
xmmMap[x].VFreg = vfWriteReg;
|
||||
xmmMap[x].xyzw = xyzw;
|
||||
}
|
||||
else { // Reg Will Not Be Modified (always load full reg for caching)
|
||||
if (vfLoadReg == 33) loadIreg(xmmx, 0xf);
|
||||
else if (vfLoadReg == 32) xMOVAPS (xmmx, ptr128[®s().ACC]);
|
||||
else if (vfLoadReg >= 0) xMOVAPS (xmmx, ptr128[&getVF(vfLoadReg)]);
|
||||
if (vfLoadReg == 33) loadIreg(xmmX, 0xf);
|
||||
elif (vfLoadReg == 32) xMOVAPS (xmmX, ptr128[®s().ACC]);
|
||||
elif (vfLoadReg >= 0) xMOVAPS (xmmX, ptr128[&getVF(vfLoadReg)]);
|
||||
xmmMap[x].VFreg = vfLoadReg;
|
||||
xmmMap[x].xyzw = 0;
|
||||
}
|
||||
xmmMap[x].count = counter;
|
||||
xmmMap[x].isNeeded = 1;
|
||||
return xmmx;
|
||||
return xmmX;
|
||||
}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -213,8 +213,33 @@ void mVUmergeRegs(const xmm& dest, const xmm& src, int xyzw, bool modXYZW)
|
|||
// Micro VU - Misc Functions
|
||||
//------------------------------------------------------------------
|
||||
|
||||
// Backup Volatile Regs (EAX, ECX, EDX, MM0~7, XMM0~7, are all volatile according to 32bit Win/Linux ABI)
|
||||
__fi void mVUbackupRegs(microVU* mVU, bool toMemory = false)
|
||||
{
|
||||
if (toMemory) {
|
||||
for(int i = 0; i < 8; i++) {
|
||||
xMOVAPS(ptr128[&mVU->xmmBackup[i][0]], xmm(i));
|
||||
}
|
||||
}
|
||||
else {
|
||||
mVU->regAlloc->flushAll(); // Flush Regalloc
|
||||
xMOVAPS(ptr128[&mVU->xmmBackup[xmmPQ.Id][0]], xmmPQ);
|
||||
}
|
||||
}
|
||||
|
||||
// Restore Volatile Regs
|
||||
__fi void mVUrestoreRegs(microVU* mVU, bool fromMemory = false)
|
||||
{
|
||||
if (fromMemory) {
|
||||
for(int i = 0; i < 8; i++) {
|
||||
xMOVAPS(xmm(i), ptr128[&mVU->xmmBackup[i][0]]);
|
||||
}
|
||||
}
|
||||
else xMOVAPS(xmmPQ, ptr128[&mVU->xmmBackup[xmmPQ.Id][0]]);
|
||||
}
|
||||
|
||||
// Gets called by mVUaddrFix at execution-time
|
||||
static void __fastcall mVUwarningRegAccess(mV) { Console.Error("microVU0 Warning: Accessing VU1 Regs! [%04x] [%x]", xPC, mVU->prog.cur); }
|
||||
static void __fastcall mVUwarningRegAccess(u32 prog, u32 pc) { Console.Error("microVU0 Warning: Accessing VU1 Regs! [%04x] [%x]", pc, prog); }
|
||||
|
||||
// Transforms the Address in gprReg to valid VU0/VU1 Address
|
||||
__fi void mVUaddrFix(mV, const x32& gprReg)
|
||||
|
|
@ -224,6 +249,7 @@ __fi void mVUaddrFix(mV, const x32& gprReg)
|
|||
xSHL(gprReg, 4);
|
||||
}
|
||||
else {
|
||||
if (IsDevBuild && !isCOP2) mVUbackupRegs(mVU, true);
|
||||
xTEST(gprReg, 0x400);
|
||||
xForwardJNZ8 jmpA; // if addr & 0x4000, reads VU1's VF regs and VI regs
|
||||
xAND(gprReg, 0xff); // if !(addr & 0x4000), wrap around
|
||||
|
|
@ -233,32 +259,21 @@ __fi void mVUaddrFix(mV, const x32& gprReg)
|
|||
xPUSH(gprT1); // Note: Kernel does it via COP2 to initialize VU1!
|
||||
xPUSH(gprT2); // So we don't spam console, we'll only check micro-mode...
|
||||
xPUSH(gprT3);
|
||||
xMOV(gprT2, (uptr)mVU);
|
||||
xMOV (gprT2, mVU->prog.cur->idx);
|
||||
xMOV (gprT3, xPC);
|
||||
xCALL(mVUwarningRegAccess);
|
||||
xPOP(gprT3);
|
||||
xPOP(gprT2);
|
||||
xPOP(gprT1);
|
||||
xPOP (gprT3);
|
||||
xPOP (gprT2);
|
||||
xPOP (gprT1);
|
||||
}
|
||||
xAND(gprReg, 0x3f); // ToDo: theres a potential problem if VU0 overrides VU1's VF0/VI0 regs!
|
||||
xADD(gprReg, (u128*)VU1.VF - (u128*)VU0.Mem);
|
||||
jmpB.SetTarget();
|
||||
xSHL(gprReg, 4); // multiply by 16 (shift left by 4)
|
||||
if (IsDevBuild && !isCOP2) mVUrestoreRegs(mVU, true);
|
||||
}
|
||||
}
|
||||
|
||||
// Backup Volatile Regs (EAX, ECX, EDX, MM0~7, XMM0~7, are all volatile according to 32bit Win/Linux ABI)
|
||||
__fi void mVUbackupRegs(microVU* mVU)
|
||||
{
|
||||
mVU->regAlloc->flushAll();
|
||||
xMOVAPS(ptr128[mVU->xmmPQb], xmmPQ);
|
||||
}
|
||||
|
||||
// Restore Volatile Regs
|
||||
__fi void mVUrestoreRegs(microVU* mVU)
|
||||
{
|
||||
xMOVAPS(xmmPQ, ptr128[mVU->xmmPQb]);
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// Micro VU - Custom SSE Instructions
|
||||
//------------------------------------------------------------------
|
||||
|
|
|
|||
Loading…
Reference in New Issue