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microVU: 

-Finished operand logging, so microprogram logs are very detailed.
-Apparently XGkick specifies the address divided by 16 (thats how zerorecs handles it), so now microVU does the same thing.
-Zerorecs also saves '(PC+16)/8' instead of 'PC+16' in BAL/JALR instructions, so I did the same with microVU...

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1070 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes 2009-04-27 02:20:09 +00:00
parent a6cbab677f
commit 13cda40ec8
9 changed files with 116 additions and 101 deletions
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10
pcsx2/x86/microVU_Alloc.inl
View File

@ -72,7 +72,7 @@ microVUt(void) mVUallocFMAC2a(int& Fs, int& Ft) {
microVUt(void) mVUallocFMAC2b(int& Ft) { microVUt(void) mVUallocFMAC2b(int& Ft) {
microVU* mVU = mVUx; microVU* mVU = mVUx;
if (!_Ft_) { SysPrintf("microVU: If a game does this, its retarded...\n"); return; } if (!_Ft_) return;
//if (CHECK_VU_OVERFLOW) mVUclamp1<vuIndex>(Ft, xmmT1, _X_Y_Z_W); //if (CHECK_VU_OVERFLOW) mVUclamp1<vuIndex>(Ft, xmmT1, _X_Y_Z_W);
mVUsaveReg<vuIndex>(Ft, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); mVUsaveReg<vuIndex>(Ft, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1);
} }
@ -533,7 +533,7 @@ microVUt(void) mVUallocFMAC18b(int& ACC, int& Fs) {
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
// FMAC19 - OPMULA FMAC Opcode // FMAC19 - OPMSUB FMAC Opcode
//------------------------------------------------------------------ //------------------------------------------------------------------
microVUt(void) mVUallocFMAC19a(int& Fd, int& ACC, int& Fs, int& Ft) { microVUt(void) mVUallocFMAC19a(int& Fd, int& ACC, int& Fs, int& Ft) {
@ -727,9 +727,9 @@ microVUt(void) mVUallocVIb(int GPRreg, int _reg_) {
MOV32RtoM((uptr)&mVU->VIbackup[0], GPRreg); MOV32RtoM((uptr)&mVU->VIbackup[0], GPRreg);
MOV32MtoR(GPRreg, (uptr)&mVU->VIbackup[1]); MOV32MtoR(GPRreg, (uptr)&mVU->VIbackup[1]);
} }
if (_reg_ == 0) { return; } if (_reg_ == 0) { return; }
else if (_reg_ < 9) { MOVD32RtoMMX(mmVI(_reg_), GPRreg); } else if (_reg_ < 9) { MOVD32RtoMMX(mmVI(_reg_), GPRreg); }
else { MOV16RtoM((uptr)&mVU->regs->VI[_reg_].UL, GPRreg); } else if (_reg_ < 16) { MOV16RtoM((uptr)&mVU->regs->VI[_reg_].UL, GPRreg); }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------

13
pcsx2/x86/microVU_Analyze.inl
View File

@ -146,7 +146,6 @@ microVUt(void) mVUanalyzeIALU2(int Is, int It) {
microVUt(void) mVUanalyzeMR32(int Fs, int Ft) { microVUt(void) mVUanalyzeMR32(int Fs, int Ft) {
microVU* mVU = mVUx; microVU* mVU = mVUx;
mVUprint("microVU: MR32 Opcode");
if (!Ft) { mVUinfo |= _isNOP; } if (!Ft) { mVUinfo |= _isNOP; }
analyzeReg6(Fs); analyzeReg6(Fs);
analyzeReg2(Ft); analyzeReg2(Ft);
@ -202,7 +201,6 @@ microVUt(void) mVUanalyzeEFU2(int Fs, u8 xCycles) {
microVUt(void) mVUanalyzeMFP(int Ft) { microVUt(void) mVUanalyzeMFP(int Ft) {
microVU* mVU = mVUx; microVU* mVU = mVUx;
mVUprint("microVU: MFP Opcode");
if (!Ft) { mVUinfo |= _isNOP; } if (!Ft) { mVUinfo |= _isNOP; }
analyzeReg2(Ft); analyzeReg2(Ft);
} }
@ -239,14 +237,12 @@ microVUt(void) mVUanalyzeSQ(int Fs, int It, bool writeIt) {
microVUt(void) mVUanalyzeR1(int Fs, int Fsf) { microVUt(void) mVUanalyzeR1(int Fs, int Fsf) {
microVU* mVU = mVUx; microVU* mVU = mVUx;
mVUprint("microVU: R-reg Opcode");
analyzeReg5(Fs, Fsf); analyzeReg5(Fs, Fsf);
analyzeRreg(); analyzeRreg();
} }
microVUt(void) mVUanalyzeR2(int Ft, bool canBeNOP) { microVUt(void) mVUanalyzeR2(int Ft, bool canBeNOP) {
microVU* mVU = mVUx; microVU* mVU = mVUx;
mVUprint("microVU: R-reg Opcode");
if (!Ft) { mVUinfo |= ((canBeNOP) ? _isNOP : _noWriteVF); } if (!Ft) { mVUinfo |= ((canBeNOP) ? _isNOP : _noWriteVF); }
analyzeReg2(Ft); analyzeReg2(Ft);
analyzeRreg(); analyzeRreg();
@ -258,7 +254,6 @@ microVUt(void) mVUanalyzeR2(int Ft, bool canBeNOP) {
microVUt(void) mVUanalyzeSflag(int It) { microVUt(void) mVUanalyzeSflag(int It) {
microVU* mVU = mVUx; microVU* mVU = mVUx;
mVUprint("microVU: Sflag Opcode");
if (!It) { mVUinfo |= _isNOP; } if (!It) { mVUinfo |= _isNOP; }
else { // Sets _isSflag at instruction that FSxxx opcode reads it's status flag from else { // Sets _isSflag at instruction that FSxxx opcode reads it's status flag from
mVUinfo |= _swapOps; mVUinfo |= _swapOps;
@ -274,7 +269,6 @@ microVUt(void) mVUanalyzeSflag(int It) {
microVUt(void) mVUanalyzeFSSET() { microVUt(void) mVUanalyzeFSSET() {
microVU* mVU = mVUx; microVU* mVU = mVUx;
mVUinfo |= _isFSSET; mVUinfo |= _isFSSET;
mVUprint("microVU: FSSET Opcode");
// mVUinfo &= ~_doStatus; // mVUinfo &= ~_doStatus;
// Note: I'm not entirely sure if the non-sticky flags // Note: I'm not entirely sure if the non-sticky flags
// should be taken from the current upper instruction // should be taken from the current upper instruction
@ -288,7 +282,6 @@ microVUt(void) mVUanalyzeFSSET() {
microVUt(void) mVUanalyzeMflag(int Is, int It) { microVUt(void) mVUanalyzeMflag(int Is, int It) {
microVU* mVU = mVUx; microVU* mVU = mVUx;
mVUprint("microVU: Mflag Opcode");
if (!It) { mVUinfo |= _isNOP; } if (!It) { mVUinfo |= _isNOP; }
else { // Need set _doMac for 4 previous Ops (need to do all 4 because stalls could change the result needed) else { // Need set _doMac for 4 previous Ops (need to do all 4 because stalls could change the result needed)
mVUinfo |= _swapOps; mVUinfo |= _swapOps;
@ -324,13 +317,13 @@ microVUt(void) mVUanalyzeXGkick(int Fs, int xCycles) {
#define analyzeBranchVI(reg, infoVal) { \ #define analyzeBranchVI(reg, infoVal) { \
if (reg && (mVUcount > 0)) { /* Ensures branch is not first opcode in block */ \ if (reg && (mVUcount > 0)) { /* Ensures branch is not first opcode in block */ \
incPC(-2); \ incPC2(-2); \
if (writesVI && (reg == mVU->VIbackup[0])) { /* If prev Op modified VI reg */ \ if (writesVI && (reg == mVU->VIbackup[0])) { /* If prev Op modified VI reg */ \
mVUinfo |= _backupVI; \ mVUinfo |= _backupVI; \
incPC(2); \ incPC2(2); \
mVUinfo |= infoVal; \ mVUinfo |= infoVal; \
} \ } \
else { incPC(2); } \ else { incPC2(2); } \
} \ } \
} }

1
pcsx2/x86/microVU_Compile.inl
View File

@ -34,6 +34,7 @@
else { ajmp = JMPcc((uptr)0); } \ else { ajmp = JMPcc((uptr)0); } \
break break
// ToDo: Fix this properly.
#define flagSetMacro(xFlag, pFlag, xF, yF, zF) { \ #define flagSetMacro(xFlag, pFlag, xF, yF, zF) { \
yF += (mVUstall > 3) ? 3 : mVUstall; \ yF += (mVUstall > 3) ? 3 : mVUstall; \
if (yF > zF) { \ if (yF > zF) { \

2
pcsx2/x86/microVU_Execute.inl
View File

@ -144,6 +144,8 @@ microVUt(void*) __fastcall mVUexecute(u32 startPC, u32 cycles) {
microVUt(void) mVUcleanUp() { microVUt(void) mVUcleanUp() {
microVU* mVU = mVUx; microVU* mVU = mVUx;
//mVUprint("microVU: Program exited successfully!"); //mVUprint("microVU: Program exited successfully!");
//mVUprint("microVU: VF0 = {%x,%x,%x,%x}", params mVU->regs->VF[0].UL[0], mVU->regs->VF[0].UL[1], mVU->regs->VF[0].UL[2], mVU->regs->VF[0].UL[3]);
//mVUprint("microVU: VI0 = %x", params mVU->regs->VI[0].UL);
mVUcurProg.x86ptr = x86Ptr; mVUcurProg.x86ptr = x86Ptr;
mVUcacheCheck(x86Ptr, mVUcurProg.x86start, (uptr)(mVUcurProg.x86end - mVUcurProg.x86start)); mVUcacheCheck(x86Ptr, mVUcurProg.x86start, (uptr)(mVUcurProg.x86end - mVUcurProg.x86start));
} }

2
pcsx2/x86/microVU_Log.inl
View File

@ -47,7 +47,7 @@ microVUx(void) __mVULog(const char* fmt, ...) {
microVUt(void) __mVUdumpProgram(int progIndex) { microVUt(void) __mVUdumpProgram(int progIndex) {
microVU* mVU = mVUx; microVU* mVU = mVUx;
bool bitX[7]; bool bitX[7];
//mVU->prog.cur = progIndex; // Needed in order to set iPC
mVUlog("*********************\n", progIndex); mVUlog("*********************\n", progIndex);
mVUlog("* Micro-Program #%02d *\n", progIndex); mVUlog("* Micro-Program #%02d *\n", progIndex);
mVUlog("*********************\n\n", progIndex); mVUlog("*********************\n\n", progIndex);

103
pcsx2/x86/microVU_Lower.inl
View File

@ -76,7 +76,7 @@ microVUf(void) mVU_DIV() {
mVUunpack_xyzw<vuIndex>(xmmFs, xmmFs, 0); mVUunpack_xyzw<vuIndex>(xmmFs, xmmFs, 0);
mVUmergeRegs<vuIndex>(xmmPQ, xmmFs, writeQ ? 4 : 8); mVUmergeRegs<vuIndex>(xmmPQ, xmmFs, writeQ ? 4 : 8);
} }
pass3 { mVUlog("DIV"); } pass3 { mVUlog("DIV Q, vf%02d%s, vf%02d%s", _Fs_, _Fsf_String, _Ft_, _Ftf_String); }
} }
microVUf(void) mVU_SQRT() { microVUf(void) mVU_SQRT() {
@ -94,7 +94,7 @@ microVUf(void) mVU_SQRT() {
mVUunpack_xyzw<vuIndex>(xmmFt, xmmFt, 0); mVUunpack_xyzw<vuIndex>(xmmFt, xmmFt, 0);
mVUmergeRegs<vuIndex>(xmmPQ, xmmFt, writeQ ? 4 : 8); mVUmergeRegs<vuIndex>(xmmPQ, xmmFt, writeQ ? 4 : 8);
} }
pass3 { mVUlog("SQRT"); } pass3 { mVUlog("SQRT Q, vf%02d%s", _Ft_, _Ftf_String); }
} }
microVUf(void) mVU_RSQRT() { microVUf(void) mVU_RSQRT() {
@ -132,7 +132,7 @@ microVUf(void) mVU_RSQRT() {
mVUunpack_xyzw<vuIndex>(xmmFs, xmmFs, 0); mVUunpack_xyzw<vuIndex>(xmmFs, xmmFs, 0);
mVUmergeRegs<vuIndex>(xmmPQ, xmmFs, writeQ ? 4 : 8); mVUmergeRegs<vuIndex>(xmmPQ, xmmFs, writeQ ? 4 : 8);
} }
pass3 { mVUlog("RSQRT"); } pass3 { mVUlog("RSQRT Q, vf%02d%s, vf%02d%s", _Fs_, _Fsf_String, _Ft_, _Ftf_String); }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -181,7 +181,7 @@ microVUf(void) mVU_EATAN() {
mVU_EATAN_<vuIndex>(); mVU_EATAN_<vuIndex>();
} }
pass3 { mVUlog("EATAN"); } pass3 { mVUlog("EATAN P"); }
} }
microVUf(void) mVU_EATANxy() { microVUf(void) mVU_EATANxy() {
@ -199,7 +199,7 @@ microVUf(void) mVU_EATANxy() {
mVU_EATAN_<vuIndex>(); mVU_EATAN_<vuIndex>();
} }
pass3 { mVUlog("EATANxy"); } pass3 { mVUlog("EATANxy P"); }
} }
microVUf(void) mVU_EATANxz() { microVUf(void) mVU_EATANxz() {
@ -217,7 +217,7 @@ microVUf(void) mVU_EATANxz() {
mVU_EATAN_<vuIndex>(); mVU_EATAN_<vuIndex>();
} }
pass3 { mVUlog("EATANxz"); } pass3 { mVUlog("EATANxz P"); }
} }
#define eexpHelper(addr) { \ #define eexpHelper(addr) { \
@ -257,7 +257,7 @@ microVUf(void) mVU_EEXP() {
SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmT1); SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmT1);
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
} }
pass3 { mVUlog("EEXP"); } pass3 { mVUlog("EEXP P"); }
} }
microVUt(void) mVU_sumXYZ() { microVUt(void) mVU_sumXYZ() {
@ -286,7 +286,7 @@ microVUf(void) mVU_ELENG() {
SSE_SQRTSS_XMM_to_XMM(xmmPQ, xmmPQ); SSE_SQRTSS_XMM_to_XMM(xmmPQ, xmmPQ);
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
} }
pass3 { mVUlog("ELENG"); } pass3 { mVUlog("ELENG P"); }
} }
microVUf(void) mVU_ERCPR() { microVUf(void) mVU_ERCPR() {
@ -301,7 +301,7 @@ microVUf(void) mVU_ERCPR() {
SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs); SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs);
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
} }
pass3 { mVUlog("ERCPR"); } pass3 { mVUlog("ERCPR P"); }
} }
microVUf(void) mVU_ERLENG() { microVUf(void) mVU_ERLENG() {
@ -317,7 +317,7 @@ microVUf(void) mVU_ERLENG() {
SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs); SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs);
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
} }
pass3 { mVUlog("ERLENG"); } pass3 { mVUlog("ERLENG P"); }
} }
microVUf(void) mVU_ERSADD() { microVUf(void) mVU_ERSADD() {
@ -333,7 +333,7 @@ microVUf(void) mVU_ERSADD() {
SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs); SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs);
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
} }
pass3 { mVUlog("ERSADD"); } pass3 { mVUlog("ERSADD P"); }
} }
microVUf(void) mVU_ERSQRT() { microVUf(void) mVU_ERSQRT() {
@ -348,7 +348,7 @@ microVUf(void) mVU_ERSQRT() {
SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs); SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs);
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
} }
pass3 { mVUlog("ERSQRT"); } pass3 { mVUlog("ERSQRT P"); }
} }
microVUf(void) mVU_ESADD() { microVUf(void) mVU_ESADD() {
@ -360,7 +360,7 @@ microVUf(void) mVU_ESADD() {
mVU_sumXYZ<vuIndex>(); mVU_sumXYZ<vuIndex>();
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
} }
pass3 { mVUlog("ESADD"); } pass3 { mVUlog("ESADD P"); }
} }
#define esinHelper(addr) { \ #define esinHelper(addr) { \
@ -394,7 +394,7 @@ microVUf(void) mVU_ESIN() {
SSE_ADDSS_XMM_to_XMM(xmmPQ, xmmT1); SSE_ADDSS_XMM_to_XMM(xmmPQ, xmmT1);
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
} }
pass3 { mVUlog("ESIN"); } pass3 { mVUlog("ESIN P"); }
} }
microVUf(void) mVU_ESQRT() { microVUf(void) mVU_ESQRT() {
@ -406,7 +406,7 @@ microVUf(void) mVU_ESQRT() {
SSE_SQRTSS_XMM_to_XMM(xmmPQ, xmmFs); SSE_SQRTSS_XMM_to_XMM(xmmPQ, xmmFs);
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
} }
pass3 { mVUlog("ESQRT"); } pass3 { mVUlog("ESQRT P"); }
} }
microVUf(void) mVU_ESUM() { microVUf(void) mVU_ESUM() {
@ -422,7 +422,7 @@ microVUf(void) mVU_ESUM() {
SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs); SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs);
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
} }
pass3 { mVUlog("ESUM"); } pass3 { mVUlog("ESUM P"); }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -438,7 +438,7 @@ microVUf(void) mVU_FCAND() {
SHR32ItoR(gprT1, 24); SHR32ItoR(gprT1, 24);
mVUallocVIb<vuIndex>(gprT1, 1); mVUallocVIb<vuIndex>(gprT1, 1);
} }
pass3 { mVUlog("FCAND"); } pass3 { mVUlog("FCAND vi01, $%x", _Imm24_); }
} }
microVUf(void) mVU_FCEQ() { microVUf(void) mVU_FCEQ() {
@ -450,7 +450,7 @@ microVUf(void) mVU_FCEQ() {
SHR32ItoR(gprT1, 31); SHR32ItoR(gprT1, 31);
mVUallocVIb<vuIndex>(gprT1, 1); mVUallocVIb<vuIndex>(gprT1, 1);
} }
pass3 { mVUlog("FCEQ"); } pass3 { mVUlog("FCEQ vi01, $%x", _Imm24_); }
} }
microVUf(void) mVU_FCGET() { microVUf(void) mVU_FCGET() {
@ -460,7 +460,7 @@ microVUf(void) mVU_FCGET() {
AND32ItoR(gprT1, 0xfff); AND32ItoR(gprT1, 0xfff);
mVUallocVIb<vuIndex>(gprT1, _Ft_); mVUallocVIb<vuIndex>(gprT1, _Ft_);
} }
pass3 { mVUlog("FCGET"); } pass3 { mVUlog("FCGET vi%02d", _Ft_); }
} }
microVUf(void) mVU_FCOR() { microVUf(void) mVU_FCOR() {
@ -472,7 +472,7 @@ microVUf(void) mVU_FCOR() {
SHR32ItoR(gprT1, 24); // Get the 25th bit (also clears the rest of the garbage in the reg) SHR32ItoR(gprT1, 24); // Get the 25th bit (also clears the rest of the garbage in the reg)
mVUallocVIb<vuIndex>(gprT1, 1); mVUallocVIb<vuIndex>(gprT1, 1);
} }
pass3 { mVUlog("FCOR"); } pass3 { mVUlog("FCOR vi01, $%x", _Imm24_); }
} }
microVUf(void) mVU_FCSET() { microVUf(void) mVU_FCSET() {
@ -482,7 +482,7 @@ microVUf(void) mVU_FCSET() {
MOV32ItoR(gprT1, _Imm24_); MOV32ItoR(gprT1, _Imm24_);
mVUallocCFLAGb<vuIndex>(gprT1, fcInstance); mVUallocCFLAGb<vuIndex>(gprT1, fcInstance);
} }
pass3 { mVUlog("FCSET"); } pass3 { mVUlog("FCSET $%x", _Imm24_); }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -498,7 +498,7 @@ microVUf(void) mVU_FMAND() {
AND16RtoR(gprT1, gprT2); AND16RtoR(gprT1, gprT2);
mVUallocVIb<vuIndex>(gprT1, _Ft_); mVUallocVIb<vuIndex>(gprT1, _Ft_);
} }
pass3 { mVUlog("FMAND"); } pass3 { mVUlog("FMAND vi%02d, vi%02d", _Ft_, _Fs_); }
} }
microVUf(void) mVU_FMEQ() { microVUf(void) mVU_FMEQ() {
@ -512,7 +512,7 @@ microVUf(void) mVU_FMEQ() {
SHR32ItoR(gprT1, 31); SHR32ItoR(gprT1, 31);
mVUallocVIb<vuIndex>(gprT1, _Ft_); mVUallocVIb<vuIndex>(gprT1, _Ft_);
} }
pass3 { mVUlog("FMEQ"); } pass3 { mVUlog("FMEQ vi%02d, vi%02d", _Ft_, _Fs_); }
} }
microVUf(void) mVU_FMOR() { microVUf(void) mVU_FMOR() {
@ -524,7 +524,7 @@ microVUf(void) mVU_FMOR() {
OR16RtoR(gprT1, gprT2); OR16RtoR(gprT1, gprT2);
mVUallocVIb<vuIndex>(gprT1, _Ft_); mVUallocVIb<vuIndex>(gprT1, _Ft_);
} }
pass3 { mVUlog("FMOR"); } pass3 { mVUlog("FMOR vi%02d, vi%02d", _Ft_, _Fs_); }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -539,7 +539,7 @@ microVUf(void) mVU_FSAND() {
AND16ItoR(gprT1, _Imm12_); AND16ItoR(gprT1, _Imm12_);
mVUallocVIb<vuIndex>(gprT1, _Ft_); mVUallocVIb<vuIndex>(gprT1, _Ft_);
} }
pass3 { mVUlog("FSAND"); } pass3 { mVUlog("FSAND vi%02d, $%x", _Ft_, _Imm12_); }
} }
microVUf(void) mVU_FSEQ() { microVUf(void) mVU_FSEQ() {
@ -552,7 +552,7 @@ microVUf(void) mVU_FSEQ() {
SHR16ItoR(gprT1, 15); SHR16ItoR(gprT1, 15);
mVUallocVIb<vuIndex>(gprT1, _Ft_); mVUallocVIb<vuIndex>(gprT1, _Ft_);
} }
pass3 { mVUlog("FSEQ"); } pass3 { mVUlog("FSEQ vi%02d, $%x", _Ft_, _Imm12_); }
} }
microVUf(void) mVU_FSOR() { microVUf(void) mVU_FSOR() {
@ -563,7 +563,7 @@ microVUf(void) mVU_FSOR() {
OR16ItoR(gprT1, _Imm12_); OR16ItoR(gprT1, _Imm12_);
mVUallocVIb<vuIndex>(gprT1, _Ft_); mVUallocVIb<vuIndex>(gprT1, _Ft_);
} }
pass3 { mVUlog("FSOR"); } pass3 { mVUlog("FSOR vi%02d, $%x", _Ft_, _Imm12_); }
} }
microVUf(void) mVU_FSSET() { microVUf(void) mVU_FSSET() {
@ -576,7 +576,7 @@ microVUf(void) mVU_FSSET() {
AND16ItoR(flagReg1, 0x03f); // Remember not to modify upper 16 bits because of mac flag AND16ItoR(flagReg1, 0x03f); // Remember not to modify upper 16 bits because of mac flag
OR16ItoR (flagReg1, (_Imm12_ & 0xfc0)); OR16ItoR (flagReg1, (_Imm12_ & 0xfc0));
} }
pass3 { mVUlog("FSSET"); } pass3 { mVUlog("FSSET $%x", _Imm12_); }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -595,7 +595,7 @@ microVUf(void) mVU_IADD() {
else ADD16RtoR(gprT1, gprT1); else ADD16RtoR(gprT1, gprT1);
mVUallocVIb<vuIndex>(gprT1, _Fd_); mVUallocVIb<vuIndex>(gprT1, _Fd_);
} }
pass3 { mVUlog("IADD"); } pass3 { mVUlog("IADD vi%02d, vi%02d, vi%02d", _Fd_, _Fs_, _Ft_); }
} }
microVUf(void) mVU_IADDI() { microVUf(void) mVU_IADDI() {
@ -606,7 +606,7 @@ microVUf(void) mVU_IADDI() {
ADD16ItoR(gprT1, _Imm5_); ADD16ItoR(gprT1, _Imm5_);
mVUallocVIb<vuIndex>(gprT1, _Ft_); mVUallocVIb<vuIndex>(gprT1, _Ft_);
} }
pass3 { mVUlog("IADDI"); } pass3 { mVUlog("IADDI vi%02d, vi%02d, %d", _Ft_, _Fs_, _Imm5_); }
} }
microVUf(void) mVU_IADDIU() { microVUf(void) mVU_IADDIU() {
@ -617,7 +617,7 @@ microVUf(void) mVU_IADDIU() {
ADD16ItoR(gprT1, _Imm15_); ADD16ItoR(gprT1, _Imm15_);
mVUallocVIb<vuIndex>(gprT1, _Ft_); mVUallocVIb<vuIndex>(gprT1, _Ft_);
} }
pass3 { mVUlog("IADDIU"); } pass3 { mVUlog("IADDIU vi%02d, vi%02d, %d", _Ft_, _Fs_, _Imm15_); }
} }
microVUf(void) mVU_IAND() { microVUf(void) mVU_IAND() {
@ -631,7 +631,7 @@ microVUf(void) mVU_IAND() {
} }
mVUallocVIb<vuIndex>(gprT1, _Fd_); mVUallocVIb<vuIndex>(gprT1, _Fd_);
} }
pass3 { mVUlog("IAND"); } pass3 { mVUlog("IAND vi%02d, vi%02d, vi%02d", _Fd_, _Fs_, _Ft_); }
} }
microVUf(void) mVU_IOR() { microVUf(void) mVU_IOR() {
@ -645,7 +645,7 @@ microVUf(void) mVU_IOR() {
} }
mVUallocVIb<vuIndex>(gprT1, _Fd_); mVUallocVIb<vuIndex>(gprT1, _Fd_);
} }
pass3 { mVUlog("IOR"); } pass3 { mVUlog("IOR vi%02d, vi%02d, vi%02d", _Fd_, _Fs_, _Ft_); }
} }
microVUf(void) mVU_ISUB() { microVUf(void) mVU_ISUB() {
@ -664,7 +664,7 @@ microVUf(void) mVU_ISUB() {
} }
else { PXORRtoR(mmVI(_Fd_), mmVI(_Fd_)); } else { PXORRtoR(mmVI(_Fd_), mmVI(_Fd_)); }
} }
pass3 { mVUlog("ISUB"); } pass3 { mVUlog("ISUB vi%02d, vi%02d, vi%02d", _Fd_, _Fs_, _Ft_); }
} }
microVUf(void) mVU_ISUBIU() { microVUf(void) mVU_ISUBIU() {
@ -675,7 +675,7 @@ microVUf(void) mVU_ISUBIU() {
SUB16ItoR(gprT1, _Imm15_); SUB16ItoR(gprT1, _Imm15_);
mVUallocVIb<vuIndex>(gprT1, _Ft_); mVUallocVIb<vuIndex>(gprT1, _Ft_);
} }
pass3 { mVUlog("ISUBIU"); } pass3 { mVUlog("ISUBIU vi%02d, vi%02d, %d", _Ft_, _Fs_, _Imm15_); }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -692,7 +692,7 @@ microVUf(void) mVU_MFIR() {
if (!_XYZW_SS) { mVUunpack_xyzw<vuIndex>(xmmT1, xmmT1, 0); } if (!_XYZW_SS) { mVUunpack_xyzw<vuIndex>(xmmT1, xmmT1, 0); }
mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1);
} }
pass3 { mVUlog("MFIR"); } pass3 { mVUlog("MFIR.%s vf%02d, vi%02d", _XYZW_String, _Ft_, _Fs_); }
} }
microVUf(void) mVU_MFP() { microVUf(void) mVU_MFP() {
@ -702,7 +702,7 @@ microVUf(void) mVU_MFP() {
getPreg(xmmFt); getPreg(xmmFt);
mVUsaveReg<vuIndex>(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); mVUsaveReg<vuIndex>(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1);
} }
pass3 { mVUlog("MFP"); } pass3 { mVUlog("MFP.%s vf%02d, P", _XYZW_String, _Ft_); }
} }
microVUf(void) mVU_MOVE() { microVUf(void) mVU_MOVE() {
@ -712,7 +712,7 @@ microVUf(void) mVU_MOVE() {
mVUloadReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], _X_Y_Z_W); mVUloadReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], _X_Y_Z_W);
mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1);
} }
pass3 { mVUlog("MOVE"); } pass3 { mVUlog("MOVE.%s vf%02d, vf%02d", _XYZW_String, _Ft_, _Fs_); }
} }
microVUf(void) mVU_MR32() { microVUf(void) mVU_MR32() {
@ -723,7 +723,7 @@ microVUf(void) mVU_MR32() {
if (_X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(xmmT1, xmmT1, 0x39); } if (_X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(xmmT1, xmmT1, 0x39); }
mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 0); mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 0);
} }
pass3 { mVUlog("MR32"); } pass3 { mVUlog("MR32.%s vf%02d, vf%02d", _XYZW_String, _Ft_, _Fs_); }
} }
microVUf(void) mVU_MTIR() { microVUf(void) mVU_MTIR() {
@ -733,7 +733,7 @@ microVUf(void) mVU_MTIR() {
MOVZX32M16toR(gprT1, (uptr)&mVU->regs->VF[_Fs_].UL[_Fsf_]); MOVZX32M16toR(gprT1, (uptr)&mVU->regs->VF[_Fs_].UL[_Fsf_]);
mVUallocVIb<vuIndex>(gprT1, _Ft_); mVUallocVIb<vuIndex>(gprT1, _Ft_);
} }
pass3 { mVUlog("MTIR"); } pass3 { mVUlog("MTIR vi%02d, vf%02d%s", _Ft_, _Fs_, _Fsf_String); }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -757,7 +757,7 @@ microVUf(void) mVU_ILW() {
mVUallocVIb<vuIndex>(gprT1, _Ft_); mVUallocVIb<vuIndex>(gprT1, _Ft_);
} }
} }
pass3 { mVUlog("ILW"); } pass3 { mVUlog("ILW.%s vi%02d, vi%02d + %d", _XYZW_String, _Ft_, _Fs_, _Imm11_); }
} }
microVUf(void) mVU_ILWR() { microVUf(void) mVU_ILWR() {
@ -771,12 +771,11 @@ microVUf(void) mVU_ILWR() {
else { else {
mVUallocVIa<vuIndex>(gprT1, _Fs_); mVUallocVIa<vuIndex>(gprT1, _Fs_);
mVUaddrFix<vuIndex>(gprT1); mVUaddrFix<vuIndex>(gprT1);
MOV32RmtoR(gprT1, gprT1, (uptr)mVU->regs->Mem + offsetSS); MOVZX32Rm16toR(gprT1, gprT1, (uptr)mVU->regs->Mem + offsetSS);
if (isMMX(_Ft_)) AND32ItoR(gprT1, 0xffff);
mVUallocVIb<vuIndex>(gprT1, _Ft_); mVUallocVIb<vuIndex>(gprT1, _Ft_);
} }
} }
pass3 { mVUlog("ILWR"); } pass3 { mVUlog("ILWR.%s vi%02d, vi%02d", _XYZW_String, _Ft_, _Fs_); }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -806,7 +805,7 @@ microVUf(void) mVU_ISW() {
if (_W) MOV32RtoRm(gprT1, gprT2, (uptr)mVU->regs->Mem+12); if (_W) MOV32RtoRm(gprT1, gprT2, (uptr)mVU->regs->Mem+12);
} }
} }
pass3 { mVUlog("ISW"); } pass3 { mVUlog("ISW.%s vi%02d, vi%02d + %d", _XYZW_String, _Ft_, _Fs_, _Imm11_); }
} }
microVUf(void) mVU_ISWR() { microVUf(void) mVU_ISWR() {
@ -830,7 +829,7 @@ microVUf(void) mVU_ISWR() {
if (_W) MOV32RtoRm(gprT1, gprT2, (uptr)mVU->regs->Mem+12); if (_W) MOV32RtoRm(gprT1, gprT2, (uptr)mVU->regs->Mem+12);
} }
} }
pass3 { mVUlog("ISWR"); } pass3 { mVUlog("ISWR.%s vi%02d, vi%02d", _XYZW_String, _Ft_, _Fs_); }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -1081,6 +1080,7 @@ microVUf(void) mVU_XITOP() {
//------------------------------------------------------------------ //------------------------------------------------------------------
void __fastcall mVU_XGKICK_(u32 addr) { void __fastcall mVU_XGKICK_(u32 addr) {
addr = (addr<<4) & 0x3fff; // Multiply addr by 16 to get real address
u32 *data = (u32*)(microVU1.regs->Mem + (addr&0x3fff)); u32 *data = (u32*)(microVU1.regs->Mem + (addr&0x3fff));
u32 size = mtgsThread->PrepDataPacket( GIF_PATH_1, data, (0x4000-(addr&0x3fff)) >> 4); u32 size = mtgsThread->PrepDataPacket( GIF_PATH_1, data, (0x4000-(addr&0x3fff)) >> 4);
u8 *pDest = mtgsThread->GetDataPacketPtr(); u8 *pDest = mtgsThread->GetDataPacketPtr();
@ -1088,6 +1088,10 @@ void __fastcall mVU_XGKICK_(u32 addr) {
mtgsThread->SendDataPacket(); mtgsThread->SendDataPacket();
} }
void __fastcall mVU_XGKICK__(u32 addr) {
GSGIFTRANSFER1((u32*)microVU1.regs->Mem, ((addr<<4)&0x3fff));
}
microVUf(void) mVU_XGKICK() { microVUf(void) mVU_XGKICK() {
microVU* mVU = mVUx; microVU* mVU = mVUx;
pass1 { mVUanalyzeXGkick<vuIndex>(_Fs_, 4); } pass1 { mVUanalyzeXGkick<vuIndex>(_Fs_, 4); }
@ -1095,7 +1099,8 @@ microVUf(void) mVU_XGKICK() {
mVUprint("XGkick"); mVUprint("XGkick");
mVUallocVIa<vuIndex>(gprT2, _Fs_); // gprT2 = ECX for __fastcall mVUallocVIa<vuIndex>(gprT2, _Fs_); // gprT2 = ECX for __fastcall
PUSH32R(gprR); // gprR = EDX is volatile so backup PUSH32R(gprR); // gprR = EDX is volatile so backup
CALLFunc((uptr)mVU_XGKICK_); if (mtgsThread != NULL) CALLFunc((uptr)mVU_XGKICK_);
else CALLFunc((uptr)mVU_XGKICK__);
POP32R(gprR); // Restore POP32R(gprR); // Restore
} }
pass3 { mVUlog("XGKICK vi%02d", _Fs_); } pass3 { mVUlog("XGKICK vi%02d", _Fs_); }
@ -1197,6 +1202,8 @@ microVUf(void) mVU_JR() {
pass2 { pass2 {
if (memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]); if (memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]);
else mVUallocVIa<vuIndex>(gprT1, _Fs_); else mVUallocVIa<vuIndex>(gprT1, _Fs_);
SHL32ItoR(gprT1, 3);
AND32ItoR(gprT1, vuIndex ? 0x3ff8 : 0xff8);
MOV32RtoM((uptr)&mVU->branch, gprT1); MOV32RtoM((uptr)&mVU->branch, gprT1);
} }
pass3 { mVUlog("JR [vi%02d]", _Fs_); } pass3 { mVUlog("JR [vi%02d]", _Fs_); }
@ -1208,6 +1215,8 @@ microVUf(void) mVU_JALR() {
pass2 { pass2 {
if (memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]); if (memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]);
else mVUallocVIa<vuIndex>(gprT1, _Fs_); else mVUallocVIa<vuIndex>(gprT1, _Fs_);
SHL32ItoR(gprT1, 3);
AND32ItoR(gprT1, vuIndex ? 0x3ff8 : 0xff8);
MOV32RtoM((uptr)&mVU->branch, gprT1); MOV32RtoM((uptr)&mVU->branch, gprT1);
MOV32ItoR(gprT1, bSaveAddr); MOV32ItoR(gprT1, bSaveAddr);
mVUallocVIb<vuIndex>(gprT1, _Ft_); mVUallocVIb<vuIndex>(gprT1, _Ft_);

7
pcsx2/x86/microVU_Misc.h
View File

@ -88,7 +88,7 @@ declareAllVariables
#define _Fsf_ ((mVU->code >> 21) & 0x03) #define _Fsf_ ((mVU->code >> 21) & 0x03)
#define _Ftf_ ((mVU->code >> 23) & 0x03) #define _Ftf_ ((mVU->code >> 23) & 0x03)
#define _Imm5_ (((mVU->code & 0x400) ? 0xfff0 : 0) | ((mVU->code >> 6) & 0xf)) #define _Imm5_ (s16)(((mVU->code & 0x400) ? 0xfff0 : 0) | ((mVU->code >> 6) & 0xf))
#define _Imm11_ (s32)((mVU->code & 0x400) ? (0xfffffc00 | (mVU->code & 0x3ff)) : mVU->code & 0x3ff) #define _Imm11_ (s32)((mVU->code & 0x400) ? (0xfffffc00 | (mVU->code & 0x3ff)) : mVU->code & 0x3ff)
#define _Imm12_ (((mVU->code >> 21) & 0x1) << 11) | (mVU->code & 0x7ff) #define _Imm12_ (((mVU->code >> 21) & 0x1) << 11) | (mVU->code & 0x7ff)
#define _Imm15_ (((mVU->code >> 10) & 0x7800) | (mVU->code & 0x7ff)) #define _Imm15_ (((mVU->code >> 10) & 0x7800) | (mVU->code & 0x7ff))
@ -161,13 +161,14 @@ declareAllVariables
#define incPC(x) { iPC = ((iPC + x) & (mVU->progSize-1)); setCode(); } #define incPC(x) { iPC = ((iPC + x) & (mVU->progSize-1)); setCode(); }
#define incPC2(x) { iPC = ((iPC + x) & (mVU->progSize-1)); } #define incPC2(x) { iPC = ((iPC + x) & (mVU->progSize-1)); }
#define incCycles(x) { mVUincCycles<vuIndex>(x); } #define incCycles(x) { mVUincCycles<vuIndex>(x); }
#define bSaveAddr ((xPC + (2 * 8)) & ((vuIndex) ? 0x3ff8:0xff8)) #define bSaveAddr (((xPC + (2 * 8)) & ((vuIndex) ? 0x3ff8:0xff8)) / 8)
#define branchAddr ((xPC + 8 + (_Imm11_ * 8)) & ((vuIndex) ? 0x3ff8:0xff8)) #define branchAddr ((xPC + 8 + (_Imm11_ * 8)) & ((vuIndex) ? 0x3ff8:0xff8))
#define shufflePQ (((mVU->q) ? 0xb0 : 0xe0) | ((mVU->q) ? 0x01 : 0x04)) #define shufflePQ (((mVU->p) ? 0xb0 : 0xe0) | ((mVU->q) ? 0x01 : 0x04))
#define _Fsf_String ((_Fsf_ == 3) ? "w" : ((_Fsf_ == 2) ? "z" : ((_Fsf_ == 1) ? "y" : "x"))) #define _Fsf_String ((_Fsf_ == 3) ? "w" : ((_Fsf_ == 2) ? "z" : ((_Fsf_ == 1) ? "y" : "x")))
#define _Ftf_String ((_Ftf_ == 3) ? "w" : ((_Ftf_ == 2) ? "z" : ((_Ftf_ == 1) ? "y" : "x"))) #define _Ftf_String ((_Ftf_ == 3) ? "w" : ((_Ftf_ == 2) ? "z" : ((_Ftf_ == 1) ? "y" : "x")))
#define xyzwStr(x,s) (_X_Y_Z_W == x) ? s : #define xyzwStr(x,s) (_X_Y_Z_W == x) ? s :
#define _XYZW_String (xyzwStr(1, "w") (xyzwStr(2, "z") (xyzwStr(3, "zw") (xyzwStr(4, "y") (xyzwStr(5, "yw") (xyzwStr(6, "yz") (xyzwStr(7, "yzw") (xyzwStr(8, "x") (xyzwStr(9, "xw") (xyzwStr(10, "xz") (xyzwStr(11, "xzw") (xyzwStr(12, "xy") (xyzwStr(13, "xyw") (xyzwStr(14, "xyz") "xyzw")))))))))))))) #define _XYZW_String (xyzwStr(1, "w") (xyzwStr(2, "z") (xyzwStr(3, "zw") (xyzwStr(4, "y") (xyzwStr(5, "yw") (xyzwStr(6, "yz") (xyzwStr(7, "yzw") (xyzwStr(8, "x") (xyzwStr(9, "xw") (xyzwStr(10, "xz") (xyzwStr(11, "xzw") (xyzwStr(12, "xy") (xyzwStr(13, "xyw") (xyzwStr(14, "xyz") "xyzw"))))))))))))))
#define _BC_String (_bc_x ? "x" : (_bc_y ? "y" : (_bc_z ? "z" : "w")))
#define _isNOP (1<<0) // Skip Lower Instruction #define _isNOP (1<<0) // Skip Lower Instruction

2
pcsx2/x86/microVU_Misc.inl
View File

@ -264,7 +264,7 @@ microVUx(void) mVUmergeRegs(int dest, int src, int xyzw) {
// Transforms the Address in gprReg to valid VU0/VU1 Address // Transforms the Address in gprReg to valid VU0/VU1 Address
microVUt(void) mVUaddrFix(int gprReg) { microVUt(void) mVUaddrFix(int gprReg) {
if ( vuIndex == 1 ) { if (vuIndex) {
AND32ItoR(gprReg, 0x3ff); // wrap around AND32ItoR(gprReg, 0x3ff); // wrap around
SHL32ItoR(gprReg, 4); SHL32ItoR(gprReg, 4);
} }

77
pcsx2/x86/microVU_Upper.inl
View File

@ -78,6 +78,15 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
// Helper Macros // Helper Macros
//------------------------------------------------------------------ //------------------------------------------------------------------
#define mVUlogFtFs() { mVUlog(".%s vf%02d, vf%02d", _XYZW_String, _Ft_, _Fs_); }
#define mVUlogFd() { mVUlog(".%s vf%02d, vf%02d", _XYZW_String, _Fd_, _Fs_); }
#define mVUlogACC() { mVUlog(".%s ACC, vf%02d", _XYZW_String, _Fs_); }
#define mVUlogFt() { mVUlog(", vf%02d", _Ft_); }
#define mVUlogBC() { mVUlog(", vf%02d%s", _Ft_, _BC_String); }
#define mVUlogI() { mVUlog(", I"); }
#define mVUlogQ() { mVUlog(", Q"); }
#define mVUlogCLIP() { mVUlog("w.xyz vf%02d, vf%02dw", _Fs_, _Ft_); }
// FMAC1 - Normal FMAC Opcodes // FMAC1 - Normal FMAC Opcodes
#define mVU_FMAC1(operation, OPname) { \ #define mVU_FMAC1(operation, OPname) { \
microVU* mVU = mVUx; \ microVU* mVU = mVUx; \
@ -90,7 +99,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \ mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \
mVUallocFMAC1b<vuIndex>(Fd); \ mVUallocFMAC1b<vuIndex>(Fd); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogFt(); } \
} }
// FMAC3 - BC(xyzw) FMAC Opcodes // FMAC3 - BC(xyzw) FMAC Opcodes
#define mVU_FMAC3(operation, OPname) { \ #define mVU_FMAC3(operation, OPname) { \
@ -104,7 +113,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \ mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \
mVUallocFMAC3b<vuIndex>(Fd); \ mVUallocFMAC3b<vuIndex>(Fd); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogBC(); } \
} }
// FMAC4 - FMAC Opcodes Storing Result to ACC // FMAC4 - FMAC Opcodes Storing Result to ACC
#define mVU_FMAC4(operation, OPname) { \ #define mVU_FMAC4(operation, OPname) { \
@ -118,7 +127,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC4b<vuIndex>(ACC, Fs); \ mVUallocFMAC4b<vuIndex>(ACC, Fs); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogFt(); } \
} }
// FMAC5 - FMAC BC(xyzw) Opcodes Storing Result to ACC // FMAC5 - FMAC BC(xyzw) Opcodes Storing Result to ACC
#define mVU_FMAC5(operation, OPname) { \ #define mVU_FMAC5(operation, OPname) { \
@ -132,7 +141,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC5b<vuIndex>(ACC, Fs); \ mVUallocFMAC5b<vuIndex>(ACC, Fs); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogBC(); } \
} }
// FMAC6 - Normal FMAC Opcodes (I Reg) // FMAC6 - Normal FMAC Opcodes (I Reg)
#define mVU_FMAC6(operation, OPname) { \ #define mVU_FMAC6(operation, OPname) { \
@ -146,7 +155,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \ mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \
mVUallocFMAC6b<vuIndex>(Fd); \ mVUallocFMAC6b<vuIndex>(Fd); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogI(); } \
} }
// FMAC7 - FMAC Opcodes Storing Result to ACC (I Reg) // FMAC7 - FMAC Opcodes Storing Result to ACC (I Reg)
#define mVU_FMAC7(operation, OPname) { \ #define mVU_FMAC7(operation, OPname) { \
@ -160,7 +169,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC7b<vuIndex>(ACC, Fs); \ mVUallocFMAC7b<vuIndex>(ACC, Fs); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogI(); } \
} }
// FMAC8 - MADD FMAC Opcode Storing Result to Fd // FMAC8 - MADD FMAC Opcode Storing Result to Fd
#define mVU_FMAC8(operation, OPname) { \ #define mVU_FMAC8(operation, OPname) { \
@ -180,7 +189,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC8b<vuIndex>(Fd); \ mVUallocFMAC8b<vuIndex>(Fd); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogFt(); } \
} }
// FMAC9 - MSUB FMAC Opcode Storing Result to Fd // FMAC9 - MSUB FMAC Opcode Storing Result to Fd
#define mVU_FMAC9(operation, OPname) { \ #define mVU_FMAC9(operation, OPname) { \
@ -200,7 +209,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC9b<vuIndex>(Fd); \ mVUallocFMAC9b<vuIndex>(Fd); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogFt(); } \
} }
// FMAC10 - MADD FMAC BC(xyzw) Opcode Storing Result to Fd // FMAC10 - MADD FMAC BC(xyzw) Opcode Storing Result to Fd
#define mVU_FMAC10(operation, OPname) { \ #define mVU_FMAC10(operation, OPname) { \
@ -220,7 +229,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC10b<vuIndex>(Fd); \ mVUallocFMAC10b<vuIndex>(Fd); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogBC(); } \
} }
// FMAC11 - MSUB FMAC BC(xyzw) Opcode Storing Result to Fd // FMAC11 - MSUB FMAC BC(xyzw) Opcode Storing Result to Fd
#define mVU_FMAC11(operation, OPname) { \ #define mVU_FMAC11(operation, OPname) { \
@ -240,7 +249,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC11b<vuIndex>(Fd); \ mVUallocFMAC11b<vuIndex>(Fd); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogBC(); } \
} }
// FMAC12 - MADD FMAC Opcode Storing Result to Fd (I Reg) // FMAC12 - MADD FMAC Opcode Storing Result to Fd (I Reg)
#define mVU_FMAC12(operation, OPname) { \ #define mVU_FMAC12(operation, OPname) { \
@ -260,7 +269,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC12b<vuIndex>(Fd); \ mVUallocFMAC12b<vuIndex>(Fd); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogI(); } \
} }
// FMAC13 - MSUB FMAC Opcode Storing Result to Fd (I Reg) // FMAC13 - MSUB FMAC Opcode Storing Result to Fd (I Reg)
#define mVU_FMAC13(operation, OPname) { \ #define mVU_FMAC13(operation, OPname) { \
@ -280,7 +289,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC13b<vuIndex>(Fd); \ mVUallocFMAC13b<vuIndex>(Fd); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogI(); } \
} }
// FMAC14 - MADDA/MSUBA FMAC Opcode // FMAC14 - MADDA/MSUBA FMAC Opcode
#define mVU_FMAC14(operation, OPname) { \ #define mVU_FMAC14(operation, OPname) { \
@ -300,7 +309,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC14b<vuIndex>(ACCw, ACCr); \ mVUallocFMAC14b<vuIndex>(ACCw, ACCr); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogFt(); } \
} }
// FMAC15 - MADDA/MSUBA BC(xyzw) FMAC Opcode // FMAC15 - MADDA/MSUBA BC(xyzw) FMAC Opcode
#define mVU_FMAC15(operation, OPname) { \ #define mVU_FMAC15(operation, OPname) { \
@ -320,7 +329,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC15b<vuIndex>(ACCw, ACCr); \ mVUallocFMAC15b<vuIndex>(ACCw, ACCr); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogBC(); } \
} }
// FMAC16 - MADDA/MSUBA FMAC Opcode (I Reg) // FMAC16 - MADDA/MSUBA FMAC Opcode (I Reg)
#define mVU_FMAC16(operation, OPname) { \ #define mVU_FMAC16(operation, OPname) { \
@ -340,7 +349,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC16b<vuIndex>(ACCw, ACCr); \ mVUallocFMAC16b<vuIndex>(ACCw, ACCr); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogI(); } \
} }
// FMAC18 - OPMULA FMAC Opcode // FMAC18 - OPMULA FMAC Opcode
#define mVU_FMAC18(operation, OPname) { \ #define mVU_FMAC18(operation, OPname) { \
@ -353,9 +362,9 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC18b<vuIndex>(ACC, Fs); \ mVUallocFMAC18b<vuIndex>(ACC, Fs); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogFt(); } \
} }
// FMAC19 - OPMULA FMAC Opcode // FMAC19 - OPMSUB FMAC Opcode
#define mVU_FMAC19(operation, OPname) { \ #define mVU_FMAC19(operation, OPname) { \
microVU* mVU = mVUx; \ microVU* mVU = mVUx; \
pass1 { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, _Ft_); } \ pass1 { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, _Ft_); } \
@ -367,7 +376,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC19b<vuIndex>(Fd); \ mVUallocFMAC19b<vuIndex>(Fd); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogFt(); } \
} }
// FMAC22 - Normal FMAC Opcodes (Q Reg) // FMAC22 - Normal FMAC Opcodes (Q Reg)
#define mVU_FMAC22(operation, OPname) { \ #define mVU_FMAC22(operation, OPname) { \
@ -381,7 +390,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \ mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \
mVUallocFMAC22b<vuIndex>(Fd); \ mVUallocFMAC22b<vuIndex>(Fd); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogQ(); } \
} }
// FMAC23 - FMAC Opcodes Storing Result to ACC (Q Reg) // FMAC23 - FMAC Opcodes Storing Result to ACC (Q Reg)
#define mVU_FMAC23(operation, OPname) { \ #define mVU_FMAC23(operation, OPname) { \
@ -395,7 +404,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC23b<vuIndex>(ACC, Fs); \ mVUallocFMAC23b<vuIndex>(ACC, Fs); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogQ();} \
} }
// FMAC24 - MADD FMAC Opcode Storing Result to Fd (Q Reg) // FMAC24 - MADD FMAC Opcode Storing Result to Fd (Q Reg)
#define mVU_FMAC24(operation, OPname) { \ #define mVU_FMAC24(operation, OPname) { \
@ -415,7 +424,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC24b<vuIndex>(Fd); \ mVUallocFMAC24b<vuIndex>(Fd); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogQ(); } \
} }
// FMAC25 - MSUB FMAC Opcode Storing Result to Fd (Q Reg) // FMAC25 - MSUB FMAC Opcode Storing Result to Fd (Q Reg)
#define mVU_FMAC25(operation, OPname) { \ #define mVU_FMAC25(operation, OPname) { \
@ -435,7 +444,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC25b<vuIndex>(Fd); \ mVUallocFMAC25b<vuIndex>(Fd); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogQ(); } \
} }
// FMAC26 - MADDA/MSUBA FMAC Opcode (Q Reg) // FMAC26 - MADDA/MSUBA FMAC Opcode (Q Reg)
#define mVU_FMAC26(operation, OPname) { \ #define mVU_FMAC26(operation, OPname) { \
@ -455,7 +464,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \ mVUupdateFlags<vuIndex>(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC26b<vuIndex>(ACCw, ACCr); \ mVUallocFMAC26b<vuIndex>(ACCw, ACCr); \
} \ } \
pass3 { mVUlog(OPname); } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogQ(); } \
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -471,7 +480,7 @@ microVUf(void) mVU_ABS() {
SSE_ANDPS_M128_to_XMM(Fs, (uptr)mVU_absclip); SSE_ANDPS_M128_to_XMM(Fs, (uptr)mVU_absclip);
mVUallocFMAC2b<vuIndex>(Ft); mVUallocFMAC2b<vuIndex>(Ft);
} }
pass3 { mVUlog("ABS"); } pass3 { mVUlog("ABS"); mVUlogFtFs(); }
} }
microVUf(void) mVU_ADD() { mVU_FMAC1 (ADD, "ADD"); } microVUf(void) mVU_ADD() { mVU_FMAC1 (ADD, "ADD"); }
microVUf(void) mVU_ADDi() { mVU_FMAC6 (ADD, "ADDi"); } microVUf(void) mVU_ADDi() { mVU_FMAC6 (ADD, "ADDi"); }
@ -545,7 +554,7 @@ microVUf(void) mVU_MSUBAz() { mVU_FMAC15(SUB, "MSUBAz"); }
microVUf(void) mVU_MSUBAw() { mVU_FMAC15(SUB, "MSUBAw"); } microVUf(void) mVU_MSUBAw() { mVU_FMAC15(SUB, "MSUBAw"); }
microVUf(void) mVU_MAX() { mVU_FMAC1 (MAX, "MAX"); } microVUf(void) mVU_MAX() { mVU_FMAC1 (MAX, "MAX"); }
microVUf(void) mVU_MAXi() { mVU_FMAC6 (MAX, "MAXi"); } microVUf(void) mVU_MAXi() { mVU_FMAC6 (MAX, "MAXi"); }
microVUf(void) mVU_MAXx() { mVU_FMAC3 (MAX, "MAXq"); } microVUf(void) mVU_MAXx() { mVU_FMAC3 (MAX, "MAXx"); }
microVUf(void) mVU_MAXy() { mVU_FMAC3 (MAX, "MAXy"); } microVUf(void) mVU_MAXy() { mVU_FMAC3 (MAX, "MAXy"); }
microVUf(void) mVU_MAXz() { mVU_FMAC3 (MAX, "MAXz"); } microVUf(void) mVU_MAXz() { mVU_FMAC3 (MAX, "MAXz"); }
microVUf(void) mVU_MAXw() { mVU_FMAC3 (MAX, "MAXw"); } microVUf(void) mVU_MAXw() { mVU_FMAC3 (MAX, "MAXw"); }
@ -579,10 +588,10 @@ microVUq(void) mVU_FTOIx(uptr addr) {
mVUallocFMAC2b<vuIndex>(Ft); mVUallocFMAC2b<vuIndex>(Ft);
} }
} }
microVUf(void) mVU_FTOI0() { mVU_FTOIx<vuIndex, recPass>((uptr)0); pass3 { mVUlog("FTOI0"); } } microVUf(void) mVU_FTOI0() { mVU_FTOIx<vuIndex, recPass>((uptr)0); pass3 { microVU* mVU = mVUx; mVUlog("FTOI0"); mVUlogFtFs(); } }
microVUf(void) mVU_FTOI4() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_4); pass3 { mVUlog("FTOI4"); } } microVUf(void) mVU_FTOI4() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_4); pass3 { microVU* mVU = mVUx; mVUlog("FTOI4"); mVUlogFtFs(); } }
microVUf(void) mVU_FTOI12() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_12); pass3 { mVUlog("FTOI12"); } } microVUf(void) mVU_FTOI12() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_12); pass3 { microVU* mVU = mVUx; mVUlog("FTOI12"); mVUlogFtFs(); } }
microVUf(void) mVU_FTOI15() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_15); pass3 { mVUlog("FTOI15"); } } microVUf(void) mVU_FTOI15() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_15); pass3 { microVU* mVU = mVUx; mVUlog("FTOI15"); mVUlogFtFs(); } }
microVUq(void) mVU_ITOFx(uptr addr) { microVUq(void) mVU_ITOFx(uptr addr) {
microVU* mVU = mVUx; microVU* mVU = mVUx;
pass1 { mVUanalyzeFMAC2<vuIndex>(_Fs_, _Ft_); } pass1 { mVUanalyzeFMAC2<vuIndex>(_Fs_, _Ft_); }
@ -597,10 +606,10 @@ microVUq(void) mVU_ITOFx(uptr addr) {
mVUallocFMAC2b<vuIndex>(Ft); mVUallocFMAC2b<vuIndex>(Ft);
} }
} }
microVUf(void) mVU_ITOF0() { mVU_ITOFx<vuIndex, recPass>((uptr)0); pass3 { mVUlog("ITOF0"); } } microVUf(void) mVU_ITOF0() { mVU_ITOFx<vuIndex, recPass>((uptr)0); pass3 { microVU* mVU = mVUx; mVUlog("ITOF0"); mVUlogFtFs(); } }
microVUf(void) mVU_ITOF4() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_4); pass3 { mVUlog("ITOF4"); } } microVUf(void) mVU_ITOF4() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_4); pass3 { microVU* mVU = mVUx; mVUlog("ITOF4"); mVUlogFtFs(); } }
microVUf(void) mVU_ITOF12() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_12); pass3 { mVUlog("ITOF12"); } } microVUf(void) mVU_ITOF12() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_12); pass3 { microVU* mVU = mVUx; mVUlog("ITOF12"); mVUlogFtFs(); } }
microVUf(void) mVU_ITOF15() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_15); pass3 { mVUlog("ITOF15"); } } microVUf(void) mVU_ITOF15() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_15); pass3 { microVU* mVU = mVUx; mVUlog("ITOF15"); mVUlogFtFs(); } }
microVUf(void) mVU_CLIP() { microVUf(void) mVU_CLIP() {
microVU* mVU = mVUx; microVU* mVU = mVUx;
pass1 { mVUanalyzeFMAC4<vuIndex>(_Fs_, _Ft_); } pass1 { mVUanalyzeFMAC4<vuIndex>(_Fs_, _Ft_); }
@ -633,6 +642,6 @@ microVUf(void) mVU_CLIP() {
mVUallocCFLAGb<vuIndex>(gprT1, fcInstance); mVUallocCFLAGb<vuIndex>(gprT1, fcInstance);
} }
pass3 { mVUlog("CLIP"); } pass3 { mVUlog("CLIP"); mVUlogCLIP(); }
} }
#endif //PCSX2_MICROVU #endif //PCSX2_MICROVU