mirror of https://github.com/PCSX2/pcsx2.git
microVU:
-Finished operand logging, so microprogram logs are very detailed. -Apparently XGkick specifies the address divided by 16 (thats how zerorecs handles it), so now microVU does the same thing. -Zerorecs also saves '(PC+16)/8' instead of 'PC+16' in BAL/JALR instructions, so I did the same with microVU... git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1070 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
a6cbab677f
commit
13cda40ec8
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@ -72,7 +72,7 @@ microVUt(void) mVUallocFMAC2a(int& Fs, int& Ft) {
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microVUt(void) mVUallocFMAC2b(int& Ft) {
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microVU* mVU = mVUx;
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if (!_Ft_) { SysPrintf("microVU: If a game does this, its retarded...\n"); return; }
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if (!_Ft_) return;
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//if (CHECK_VU_OVERFLOW) mVUclamp1<vuIndex>(Ft, xmmT1, _X_Y_Z_W);
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mVUsaveReg<vuIndex>(Ft, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1);
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}
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@ -533,7 +533,7 @@ microVUt(void) mVUallocFMAC18b(int& ACC, int& Fs) {
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}
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//------------------------------------------------------------------
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// FMAC19 - OPMULA FMAC Opcode
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// FMAC19 - OPMSUB FMAC Opcode
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//------------------------------------------------------------------
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microVUt(void) mVUallocFMAC19a(int& Fd, int& ACC, int& Fs, int& Ft) {
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@ -727,9 +727,9 @@ microVUt(void) mVUallocVIb(int GPRreg, int _reg_) {
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MOV32RtoM((uptr)&mVU->VIbackup[0], GPRreg);
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MOV32MtoR(GPRreg, (uptr)&mVU->VIbackup[1]);
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}
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if (_reg_ == 0) { return; }
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else if (_reg_ < 9) { MOVD32RtoMMX(mmVI(_reg_), GPRreg); }
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else { MOV16RtoM((uptr)&mVU->regs->VI[_reg_].UL, GPRreg); }
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if (_reg_ == 0) { return; }
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else if (_reg_ < 9) { MOVD32RtoMMX(mmVI(_reg_), GPRreg); }
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else if (_reg_ < 16) { MOV16RtoM((uptr)&mVU->regs->VI[_reg_].UL, GPRreg); }
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}
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//------------------------------------------------------------------
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@ -146,7 +146,6 @@ microVUt(void) mVUanalyzeIALU2(int Is, int It) {
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microVUt(void) mVUanalyzeMR32(int Fs, int Ft) {
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microVU* mVU = mVUx;
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mVUprint("microVU: MR32 Opcode");
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if (!Ft) { mVUinfo |= _isNOP; }
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analyzeReg6(Fs);
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analyzeReg2(Ft);
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@ -202,7 +201,6 @@ microVUt(void) mVUanalyzeEFU2(int Fs, u8 xCycles) {
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microVUt(void) mVUanalyzeMFP(int Ft) {
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microVU* mVU = mVUx;
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mVUprint("microVU: MFP Opcode");
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if (!Ft) { mVUinfo |= _isNOP; }
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analyzeReg2(Ft);
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}
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@ -239,14 +237,12 @@ microVUt(void) mVUanalyzeSQ(int Fs, int It, bool writeIt) {
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microVUt(void) mVUanalyzeR1(int Fs, int Fsf) {
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microVU* mVU = mVUx;
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mVUprint("microVU: R-reg Opcode");
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analyzeReg5(Fs, Fsf);
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analyzeRreg();
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}
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microVUt(void) mVUanalyzeR2(int Ft, bool canBeNOP) {
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microVU* mVU = mVUx;
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mVUprint("microVU: R-reg Opcode");
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if (!Ft) { mVUinfo |= ((canBeNOP) ? _isNOP : _noWriteVF); }
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analyzeReg2(Ft);
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analyzeRreg();
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@ -258,7 +254,6 @@ microVUt(void) mVUanalyzeR2(int Ft, bool canBeNOP) {
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microVUt(void) mVUanalyzeSflag(int It) {
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microVU* mVU = mVUx;
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mVUprint("microVU: Sflag Opcode");
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if (!It) { mVUinfo |= _isNOP; }
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else { // Sets _isSflag at instruction that FSxxx opcode reads it's status flag from
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mVUinfo |= _swapOps;
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@ -274,7 +269,6 @@ microVUt(void) mVUanalyzeSflag(int It) {
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microVUt(void) mVUanalyzeFSSET() {
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microVU* mVU = mVUx;
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mVUinfo |= _isFSSET;
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mVUprint("microVU: FSSET Opcode");
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// mVUinfo &= ~_doStatus;
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// Note: I'm not entirely sure if the non-sticky flags
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// should be taken from the current upper instruction
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@ -288,7 +282,6 @@ microVUt(void) mVUanalyzeFSSET() {
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microVUt(void) mVUanalyzeMflag(int Is, int It) {
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microVU* mVU = mVUx;
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mVUprint("microVU: Mflag Opcode");
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if (!It) { mVUinfo |= _isNOP; }
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else { // Need set _doMac for 4 previous Ops (need to do all 4 because stalls could change the result needed)
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mVUinfo |= _swapOps;
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@ -324,13 +317,13 @@ microVUt(void) mVUanalyzeXGkick(int Fs, int xCycles) {
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#define analyzeBranchVI(reg, infoVal) { \
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if (reg && (mVUcount > 0)) { /* Ensures branch is not first opcode in block */ \
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incPC(-2); \
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incPC2(-2); \
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if (writesVI && (reg == mVU->VIbackup[0])) { /* If prev Op modified VI reg */ \
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mVUinfo |= _backupVI; \
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incPC(2); \
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incPC2(2); \
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mVUinfo |= infoVal; \
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} \
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else { incPC(2); } \
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else { incPC2(2); } \
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} \
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}
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@ -34,6 +34,7 @@
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else { ajmp = JMPcc((uptr)0); } \
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break
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// ToDo: Fix this properly.
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#define flagSetMacro(xFlag, pFlag, xF, yF, zF) { \
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yF += (mVUstall > 3) ? 3 : mVUstall; \
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if (yF > zF) { \
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@ -144,6 +144,8 @@ microVUt(void*) __fastcall mVUexecute(u32 startPC, u32 cycles) {
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microVUt(void) mVUcleanUp() {
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microVU* mVU = mVUx;
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//mVUprint("microVU: Program exited successfully!");
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//mVUprint("microVU: VF0 = {%x,%x,%x,%x}", params mVU->regs->VF[0].UL[0], mVU->regs->VF[0].UL[1], mVU->regs->VF[0].UL[2], mVU->regs->VF[0].UL[3]);
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//mVUprint("microVU: VI0 = %x", params mVU->regs->VI[0].UL);
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mVUcurProg.x86ptr = x86Ptr;
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mVUcacheCheck(x86Ptr, mVUcurProg.x86start, (uptr)(mVUcurProg.x86end - mVUcurProg.x86start));
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}
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@ -47,7 +47,7 @@ microVUx(void) __mVULog(const char* fmt, ...) {
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microVUt(void) __mVUdumpProgram(int progIndex) {
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microVU* mVU = mVUx;
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bool bitX[7];
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//mVU->prog.cur = progIndex; // Needed in order to set iPC
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mVUlog("*********************\n", progIndex);
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mVUlog("* Micro-Program #%02d *\n", progIndex);
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mVUlog("*********************\n\n", progIndex);
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@ -76,7 +76,7 @@ microVUf(void) mVU_DIV() {
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mVUunpack_xyzw<vuIndex>(xmmFs, xmmFs, 0);
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mVUmergeRegs<vuIndex>(xmmPQ, xmmFs, writeQ ? 4 : 8);
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}
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pass3 { mVUlog("DIV"); }
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pass3 { mVUlog("DIV Q, vf%02d%s, vf%02d%s", _Fs_, _Fsf_String, _Ft_, _Ftf_String); }
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}
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microVUf(void) mVU_SQRT() {
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@ -94,7 +94,7 @@ microVUf(void) mVU_SQRT() {
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mVUunpack_xyzw<vuIndex>(xmmFt, xmmFt, 0);
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mVUmergeRegs<vuIndex>(xmmPQ, xmmFt, writeQ ? 4 : 8);
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}
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pass3 { mVUlog("SQRT"); }
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pass3 { mVUlog("SQRT Q, vf%02d%s", _Ft_, _Ftf_String); }
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}
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microVUf(void) mVU_RSQRT() {
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@ -132,7 +132,7 @@ microVUf(void) mVU_RSQRT() {
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mVUunpack_xyzw<vuIndex>(xmmFs, xmmFs, 0);
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mVUmergeRegs<vuIndex>(xmmPQ, xmmFs, writeQ ? 4 : 8);
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}
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pass3 { mVUlog("RSQRT"); }
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pass3 { mVUlog("RSQRT Q, vf%02d%s, vf%02d%s", _Fs_, _Fsf_String, _Ft_, _Ftf_String); }
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}
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//------------------------------------------------------------------
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@ -181,7 +181,7 @@ microVUf(void) mVU_EATAN() {
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mVU_EATAN_<vuIndex>();
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}
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pass3 { mVUlog("EATAN"); }
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pass3 { mVUlog("EATAN P"); }
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}
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microVUf(void) mVU_EATANxy() {
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@ -199,7 +199,7 @@ microVUf(void) mVU_EATANxy() {
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mVU_EATAN_<vuIndex>();
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}
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pass3 { mVUlog("EATANxy"); }
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pass3 { mVUlog("EATANxy P"); }
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}
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microVUf(void) mVU_EATANxz() {
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@ -217,7 +217,7 @@ microVUf(void) mVU_EATANxz() {
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mVU_EATAN_<vuIndex>();
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}
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pass3 { mVUlog("EATANxz"); }
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pass3 { mVUlog("EATANxz P"); }
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}
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#define eexpHelper(addr) { \
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@ -257,7 +257,7 @@ microVUf(void) mVU_EEXP() {
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SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmT1);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
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}
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pass3 { mVUlog("EEXP"); }
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pass3 { mVUlog("EEXP P"); }
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}
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microVUt(void) mVU_sumXYZ() {
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@ -286,7 +286,7 @@ microVUf(void) mVU_ELENG() {
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SSE_SQRTSS_XMM_to_XMM(xmmPQ, xmmPQ);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
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}
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pass3 { mVUlog("ELENG"); }
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pass3 { mVUlog("ELENG P"); }
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}
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microVUf(void) mVU_ERCPR() {
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@ -301,7 +301,7 @@ microVUf(void) mVU_ERCPR() {
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SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
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}
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pass3 { mVUlog("ERCPR"); }
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pass3 { mVUlog("ERCPR P"); }
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}
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microVUf(void) mVU_ERLENG() {
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@ -317,7 +317,7 @@ microVUf(void) mVU_ERLENG() {
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SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
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}
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pass3 { mVUlog("ERLENG"); }
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pass3 { mVUlog("ERLENG P"); }
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}
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microVUf(void) mVU_ERSADD() {
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@ -333,7 +333,7 @@ microVUf(void) mVU_ERSADD() {
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SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
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}
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pass3 { mVUlog("ERSADD"); }
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pass3 { mVUlog("ERSADD P"); }
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}
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microVUf(void) mVU_ERSQRT() {
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@ -348,7 +348,7 @@ microVUf(void) mVU_ERSQRT() {
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SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
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}
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pass3 { mVUlog("ERSQRT"); }
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pass3 { mVUlog("ERSQRT P"); }
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}
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microVUf(void) mVU_ESADD() {
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@ -360,7 +360,7 @@ microVUf(void) mVU_ESADD() {
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mVU_sumXYZ<vuIndex>();
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
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}
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pass3 { mVUlog("ESADD"); }
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pass3 { mVUlog("ESADD P"); }
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}
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#define esinHelper(addr) { \
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@ -394,7 +394,7 @@ microVUf(void) mVU_ESIN() {
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SSE_ADDSS_XMM_to_XMM(xmmPQ, xmmT1);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
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}
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pass3 { mVUlog("ESIN"); }
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pass3 { mVUlog("ESIN P"); }
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}
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microVUf(void) mVU_ESQRT() {
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@ -406,7 +406,7 @@ microVUf(void) mVU_ESQRT() {
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SSE_SQRTSS_XMM_to_XMM(xmmPQ, xmmFs);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
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}
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pass3 { mVUlog("ESQRT"); }
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pass3 { mVUlog("ESQRT P"); }
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}
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microVUf(void) mVU_ESUM() {
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@ -422,7 +422,7 @@ microVUf(void) mVU_ESUM() {
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SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
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}
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pass3 { mVUlog("ESUM"); }
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pass3 { mVUlog("ESUM P"); }
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}
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//------------------------------------------------------------------
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@ -438,7 +438,7 @@ microVUf(void) mVU_FCAND() {
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SHR32ItoR(gprT1, 24);
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mVUallocVIb<vuIndex>(gprT1, 1);
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}
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pass3 { mVUlog("FCAND"); }
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pass3 { mVUlog("FCAND vi01, $%x", _Imm24_); }
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}
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microVUf(void) mVU_FCEQ() {
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@ -450,7 +450,7 @@ microVUf(void) mVU_FCEQ() {
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SHR32ItoR(gprT1, 31);
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mVUallocVIb<vuIndex>(gprT1, 1);
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}
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pass3 { mVUlog("FCEQ"); }
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pass3 { mVUlog("FCEQ vi01, $%x", _Imm24_); }
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}
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microVUf(void) mVU_FCGET() {
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@ -460,7 +460,7 @@ microVUf(void) mVU_FCGET() {
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AND32ItoR(gprT1, 0xfff);
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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pass3 { mVUlog("FCGET"); }
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pass3 { mVUlog("FCGET vi%02d", _Ft_); }
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}
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microVUf(void) mVU_FCOR() {
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@ -472,7 +472,7 @@ microVUf(void) mVU_FCOR() {
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SHR32ItoR(gprT1, 24); // Get the 25th bit (also clears the rest of the garbage in the reg)
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mVUallocVIb<vuIndex>(gprT1, 1);
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}
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pass3 { mVUlog("FCOR"); }
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pass3 { mVUlog("FCOR vi01, $%x", _Imm24_); }
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}
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microVUf(void) mVU_FCSET() {
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@ -482,7 +482,7 @@ microVUf(void) mVU_FCSET() {
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MOV32ItoR(gprT1, _Imm24_);
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mVUallocCFLAGb<vuIndex>(gprT1, fcInstance);
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}
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pass3 { mVUlog("FCSET"); }
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pass3 { mVUlog("FCSET $%x", _Imm24_); }
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}
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//------------------------------------------------------------------
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@ -498,7 +498,7 @@ microVUf(void) mVU_FMAND() {
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AND16RtoR(gprT1, gprT2);
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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pass3 { mVUlog("FMAND"); }
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pass3 { mVUlog("FMAND vi%02d, vi%02d", _Ft_, _Fs_); }
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}
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microVUf(void) mVU_FMEQ() {
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@ -512,7 +512,7 @@ microVUf(void) mVU_FMEQ() {
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SHR32ItoR(gprT1, 31);
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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pass3 { mVUlog("FMEQ"); }
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pass3 { mVUlog("FMEQ vi%02d, vi%02d", _Ft_, _Fs_); }
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}
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microVUf(void) mVU_FMOR() {
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@ -524,7 +524,7 @@ microVUf(void) mVU_FMOR() {
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OR16RtoR(gprT1, gprT2);
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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pass3 { mVUlog("FMOR"); }
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pass3 { mVUlog("FMOR vi%02d, vi%02d", _Ft_, _Fs_); }
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}
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//------------------------------------------------------------------
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@ -539,7 +539,7 @@ microVUf(void) mVU_FSAND() {
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AND16ItoR(gprT1, _Imm12_);
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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pass3 { mVUlog("FSAND"); }
|
||||
pass3 { mVUlog("FSAND vi%02d, $%x", _Ft_, _Imm12_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_FSEQ() {
|
||||
|
|
@ -552,7 +552,7 @@ microVUf(void) mVU_FSEQ() {
|
|||
SHR16ItoR(gprT1, 15);
|
||||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
}
|
||||
pass3 { mVUlog("FSEQ"); }
|
||||
pass3 { mVUlog("FSEQ vi%02d, $%x", _Ft_, _Imm12_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_FSOR() {
|
||||
|
|
@ -563,7 +563,7 @@ microVUf(void) mVU_FSOR() {
|
|||
OR16ItoR(gprT1, _Imm12_);
|
||||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
}
|
||||
pass3 { mVUlog("FSOR"); }
|
||||
pass3 { mVUlog("FSOR vi%02d, $%x", _Ft_, _Imm12_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_FSSET() {
|
||||
|
|
@ -576,7 +576,7 @@ microVUf(void) mVU_FSSET() {
|
|||
AND16ItoR(flagReg1, 0x03f); // Remember not to modify upper 16 bits because of mac flag
|
||||
OR16ItoR (flagReg1, (_Imm12_ & 0xfc0));
|
||||
}
|
||||
pass3 { mVUlog("FSSET"); }
|
||||
pass3 { mVUlog("FSSET $%x", _Imm12_); }
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
|
|
@ -595,7 +595,7 @@ microVUf(void) mVU_IADD() {
|
|||
else ADD16RtoR(gprT1, gprT1);
|
||||
mVUallocVIb<vuIndex>(gprT1, _Fd_);
|
||||
}
|
||||
pass3 { mVUlog("IADD"); }
|
||||
pass3 { mVUlog("IADD vi%02d, vi%02d, vi%02d", _Fd_, _Fs_, _Ft_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_IADDI() {
|
||||
|
|
@ -606,7 +606,7 @@ microVUf(void) mVU_IADDI() {
|
|||
ADD16ItoR(gprT1, _Imm5_);
|
||||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
}
|
||||
pass3 { mVUlog("IADDI"); }
|
||||
pass3 { mVUlog("IADDI vi%02d, vi%02d, %d", _Ft_, _Fs_, _Imm5_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_IADDIU() {
|
||||
|
|
@ -617,7 +617,7 @@ microVUf(void) mVU_IADDIU() {
|
|||
ADD16ItoR(gprT1, _Imm15_);
|
||||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
}
|
||||
pass3 { mVUlog("IADDIU"); }
|
||||
pass3 { mVUlog("IADDIU vi%02d, vi%02d, %d", _Ft_, _Fs_, _Imm15_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_IAND() {
|
||||
|
|
@ -631,7 +631,7 @@ microVUf(void) mVU_IAND() {
|
|||
}
|
||||
mVUallocVIb<vuIndex>(gprT1, _Fd_);
|
||||
}
|
||||
pass3 { mVUlog("IAND"); }
|
||||
pass3 { mVUlog("IAND vi%02d, vi%02d, vi%02d", _Fd_, _Fs_, _Ft_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_IOR() {
|
||||
|
|
@ -645,7 +645,7 @@ microVUf(void) mVU_IOR() {
|
|||
}
|
||||
mVUallocVIb<vuIndex>(gprT1, _Fd_);
|
||||
}
|
||||
pass3 { mVUlog("IOR"); }
|
||||
pass3 { mVUlog("IOR vi%02d, vi%02d, vi%02d", _Fd_, _Fs_, _Ft_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_ISUB() {
|
||||
|
|
@ -664,7 +664,7 @@ microVUf(void) mVU_ISUB() {
|
|||
}
|
||||
else { PXORRtoR(mmVI(_Fd_), mmVI(_Fd_)); }
|
||||
}
|
||||
pass3 { mVUlog("ISUB"); }
|
||||
pass3 { mVUlog("ISUB vi%02d, vi%02d, vi%02d", _Fd_, _Fs_, _Ft_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_ISUBIU() {
|
||||
|
|
@ -675,7 +675,7 @@ microVUf(void) mVU_ISUBIU() {
|
|||
SUB16ItoR(gprT1, _Imm15_);
|
||||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
}
|
||||
pass3 { mVUlog("ISUBIU"); }
|
||||
pass3 { mVUlog("ISUBIU vi%02d, vi%02d, %d", _Ft_, _Fs_, _Imm15_); }
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
|
|
@ -692,7 +692,7 @@ microVUf(void) mVU_MFIR() {
|
|||
if (!_XYZW_SS) { mVUunpack_xyzw<vuIndex>(xmmT1, xmmT1, 0); }
|
||||
mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1);
|
||||
}
|
||||
pass3 { mVUlog("MFIR"); }
|
||||
pass3 { mVUlog("MFIR.%s vf%02d, vi%02d", _XYZW_String, _Ft_, _Fs_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_MFP() {
|
||||
|
|
@ -702,7 +702,7 @@ microVUf(void) mVU_MFP() {
|
|||
getPreg(xmmFt);
|
||||
mVUsaveReg<vuIndex>(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1);
|
||||
}
|
||||
pass3 { mVUlog("MFP"); }
|
||||
pass3 { mVUlog("MFP.%s vf%02d, P", _XYZW_String, _Ft_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_MOVE() {
|
||||
|
|
@ -712,7 +712,7 @@ microVUf(void) mVU_MOVE() {
|
|||
mVUloadReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], _X_Y_Z_W);
|
||||
mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1);
|
||||
}
|
||||
pass3 { mVUlog("MOVE"); }
|
||||
pass3 { mVUlog("MOVE.%s vf%02d, vf%02d", _XYZW_String, _Ft_, _Fs_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_MR32() {
|
||||
|
|
@ -723,7 +723,7 @@ microVUf(void) mVU_MR32() {
|
|||
if (_X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(xmmT1, xmmT1, 0x39); }
|
||||
mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 0);
|
||||
}
|
||||
pass3 { mVUlog("MR32"); }
|
||||
pass3 { mVUlog("MR32.%s vf%02d, vf%02d", _XYZW_String, _Ft_, _Fs_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_MTIR() {
|
||||
|
|
@ -733,7 +733,7 @@ microVUf(void) mVU_MTIR() {
|
|||
MOVZX32M16toR(gprT1, (uptr)&mVU->regs->VF[_Fs_].UL[_Fsf_]);
|
||||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
}
|
||||
pass3 { mVUlog("MTIR"); }
|
||||
pass3 { mVUlog("MTIR vi%02d, vf%02d%s", _Ft_, _Fs_, _Fsf_String); }
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
|
|
@ -757,7 +757,7 @@ microVUf(void) mVU_ILW() {
|
|||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
}
|
||||
}
|
||||
pass3 { mVUlog("ILW"); }
|
||||
pass3 { mVUlog("ILW.%s vi%02d, vi%02d + %d", _XYZW_String, _Ft_, _Fs_, _Imm11_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_ILWR() {
|
||||
|
|
@ -771,12 +771,11 @@ microVUf(void) mVU_ILWR() {
|
|||
else {
|
||||
mVUallocVIa<vuIndex>(gprT1, _Fs_);
|
||||
mVUaddrFix<vuIndex>(gprT1);
|
||||
MOV32RmtoR(gprT1, gprT1, (uptr)mVU->regs->Mem + offsetSS);
|
||||
if (isMMX(_Ft_)) AND32ItoR(gprT1, 0xffff);
|
||||
MOVZX32Rm16toR(gprT1, gprT1, (uptr)mVU->regs->Mem + offsetSS);
|
||||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
}
|
||||
}
|
||||
pass3 { mVUlog("ILWR"); }
|
||||
pass3 { mVUlog("ILWR.%s vi%02d, vi%02d", _XYZW_String, _Ft_, _Fs_); }
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
|
|
@ -806,7 +805,7 @@ microVUf(void) mVU_ISW() {
|
|||
if (_W) MOV32RtoRm(gprT1, gprT2, (uptr)mVU->regs->Mem+12);
|
||||
}
|
||||
}
|
||||
pass3 { mVUlog("ISW"); }
|
||||
pass3 { mVUlog("ISW.%s vi%02d, vi%02d + %d", _XYZW_String, _Ft_, _Fs_, _Imm11_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_ISWR() {
|
||||
|
|
@ -830,7 +829,7 @@ microVUf(void) mVU_ISWR() {
|
|||
if (_W) MOV32RtoRm(gprT1, gprT2, (uptr)mVU->regs->Mem+12);
|
||||
}
|
||||
}
|
||||
pass3 { mVUlog("ISWR"); }
|
||||
pass3 { mVUlog("ISWR.%s vi%02d, vi%02d", _XYZW_String, _Ft_, _Fs_); }
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
|
|
@ -1081,6 +1080,7 @@ microVUf(void) mVU_XITOP() {
|
|||
//------------------------------------------------------------------
|
||||
|
||||
void __fastcall mVU_XGKICK_(u32 addr) {
|
||||
addr = (addr<<4) & 0x3fff; // Multiply addr by 16 to get real address
|
||||
u32 *data = (u32*)(microVU1.regs->Mem + (addr&0x3fff));
|
||||
u32 size = mtgsThread->PrepDataPacket( GIF_PATH_1, data, (0x4000-(addr&0x3fff)) >> 4);
|
||||
u8 *pDest = mtgsThread->GetDataPacketPtr();
|
||||
|
|
@ -1088,6 +1088,10 @@ void __fastcall mVU_XGKICK_(u32 addr) {
|
|||
mtgsThread->SendDataPacket();
|
||||
}
|
||||
|
||||
void __fastcall mVU_XGKICK__(u32 addr) {
|
||||
GSGIFTRANSFER1((u32*)microVU1.regs->Mem, ((addr<<4)&0x3fff));
|
||||
}
|
||||
|
||||
microVUf(void) mVU_XGKICK() {
|
||||
microVU* mVU = mVUx;
|
||||
pass1 { mVUanalyzeXGkick<vuIndex>(_Fs_, 4); }
|
||||
|
|
@ -1095,7 +1099,8 @@ microVUf(void) mVU_XGKICK() {
|
|||
mVUprint("XGkick");
|
||||
mVUallocVIa<vuIndex>(gprT2, _Fs_); // gprT2 = ECX for __fastcall
|
||||
PUSH32R(gprR); // gprR = EDX is volatile so backup
|
||||
CALLFunc((uptr)mVU_XGKICK_);
|
||||
if (mtgsThread != NULL) CALLFunc((uptr)mVU_XGKICK_);
|
||||
else CALLFunc((uptr)mVU_XGKICK__);
|
||||
POP32R(gprR); // Restore
|
||||
}
|
||||
pass3 { mVUlog("XGKICK vi%02d", _Fs_); }
|
||||
|
|
@ -1197,6 +1202,8 @@ microVUf(void) mVU_JR() {
|
|||
pass2 {
|
||||
if (memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]);
|
||||
else mVUallocVIa<vuIndex>(gprT1, _Fs_);
|
||||
SHL32ItoR(gprT1, 3);
|
||||
AND32ItoR(gprT1, vuIndex ? 0x3ff8 : 0xff8);
|
||||
MOV32RtoM((uptr)&mVU->branch, gprT1);
|
||||
}
|
||||
pass3 { mVUlog("JR [vi%02d]", _Fs_); }
|
||||
|
|
@ -1208,6 +1215,8 @@ microVUf(void) mVU_JALR() {
|
|||
pass2 {
|
||||
if (memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]);
|
||||
else mVUallocVIa<vuIndex>(gprT1, _Fs_);
|
||||
SHL32ItoR(gprT1, 3);
|
||||
AND32ItoR(gprT1, vuIndex ? 0x3ff8 : 0xff8);
|
||||
MOV32RtoM((uptr)&mVU->branch, gprT1);
|
||||
MOV32ItoR(gprT1, bSaveAddr);
|
||||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
|
|
|
|||
|
|
@ -88,7 +88,7 @@ declareAllVariables
|
|||
#define _Fsf_ ((mVU->code >> 21) & 0x03)
|
||||
#define _Ftf_ ((mVU->code >> 23) & 0x03)
|
||||
|
||||
#define _Imm5_ (((mVU->code & 0x400) ? 0xfff0 : 0) | ((mVU->code >> 6) & 0xf))
|
||||
#define _Imm5_ (s16)(((mVU->code & 0x400) ? 0xfff0 : 0) | ((mVU->code >> 6) & 0xf))
|
||||
#define _Imm11_ (s32)((mVU->code & 0x400) ? (0xfffffc00 | (mVU->code & 0x3ff)) : mVU->code & 0x3ff)
|
||||
#define _Imm12_ (((mVU->code >> 21) & 0x1) << 11) | (mVU->code & 0x7ff)
|
||||
#define _Imm15_ (((mVU->code >> 10) & 0x7800) | (mVU->code & 0x7ff))
|
||||
|
|
@ -161,13 +161,14 @@ declareAllVariables
|
|||
#define incPC(x) { iPC = ((iPC + x) & (mVU->progSize-1)); setCode(); }
|
||||
#define incPC2(x) { iPC = ((iPC + x) & (mVU->progSize-1)); }
|
||||
#define incCycles(x) { mVUincCycles<vuIndex>(x); }
|
||||
#define bSaveAddr ((xPC + (2 * 8)) & ((vuIndex) ? 0x3ff8:0xff8))
|
||||
#define bSaveAddr (((xPC + (2 * 8)) & ((vuIndex) ? 0x3ff8:0xff8)) / 8)
|
||||
#define branchAddr ((xPC + 8 + (_Imm11_ * 8)) & ((vuIndex) ? 0x3ff8:0xff8))
|
||||
#define shufflePQ (((mVU->q) ? 0xb0 : 0xe0) | ((mVU->q) ? 0x01 : 0x04))
|
||||
#define shufflePQ (((mVU->p) ? 0xb0 : 0xe0) | ((mVU->q) ? 0x01 : 0x04))
|
||||
#define _Fsf_String ((_Fsf_ == 3) ? "w" : ((_Fsf_ == 2) ? "z" : ((_Fsf_ == 1) ? "y" : "x")))
|
||||
#define _Ftf_String ((_Ftf_ == 3) ? "w" : ((_Ftf_ == 2) ? "z" : ((_Ftf_ == 1) ? "y" : "x")))
|
||||
#define xyzwStr(x,s) (_X_Y_Z_W == x) ? s :
|
||||
#define _XYZW_String (xyzwStr(1, "w") (xyzwStr(2, "z") (xyzwStr(3, "zw") (xyzwStr(4, "y") (xyzwStr(5, "yw") (xyzwStr(6, "yz") (xyzwStr(7, "yzw") (xyzwStr(8, "x") (xyzwStr(9, "xw") (xyzwStr(10, "xz") (xyzwStr(11, "xzw") (xyzwStr(12, "xy") (xyzwStr(13, "xyw") (xyzwStr(14, "xyz") "xyzw"))))))))))))))
|
||||
#define _BC_String (_bc_x ? "x" : (_bc_y ? "y" : (_bc_z ? "z" : "w")))
|
||||
|
||||
|
||||
#define _isNOP (1<<0) // Skip Lower Instruction
|
||||
|
|
|
|||
|
|
@ -264,7 +264,7 @@ microVUx(void) mVUmergeRegs(int dest, int src, int xyzw) {
|
|||
|
||||
// Transforms the Address in gprReg to valid VU0/VU1 Address
|
||||
microVUt(void) mVUaddrFix(int gprReg) {
|
||||
if ( vuIndex == 1 ) {
|
||||
if (vuIndex) {
|
||||
AND32ItoR(gprReg, 0x3ff); // wrap around
|
||||
SHL32ItoR(gprReg, 4);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -78,6 +78,15 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
// Helper Macros
|
||||
//------------------------------------------------------------------
|
||||
|
||||
#define mVUlogFtFs() { mVUlog(".%s vf%02d, vf%02d", _XYZW_String, _Ft_, _Fs_); }
|
||||
#define mVUlogFd() { mVUlog(".%s vf%02d, vf%02d", _XYZW_String, _Fd_, _Fs_); }
|
||||
#define mVUlogACC() { mVUlog(".%s ACC, vf%02d", _XYZW_String, _Fs_); }
|
||||
#define mVUlogFt() { mVUlog(", vf%02d", _Ft_); }
|
||||
#define mVUlogBC() { mVUlog(", vf%02d%s", _Ft_, _BC_String); }
|
||||
#define mVUlogI() { mVUlog(", I"); }
|
||||
#define mVUlogQ() { mVUlog(", Q"); }
|
||||
#define mVUlogCLIP() { mVUlog("w.xyz vf%02d, vf%02dw", _Fs_, _Ft_); }
|
||||
|
||||
// FMAC1 - Normal FMAC Opcodes
|
||||
#define mVU_FMAC1(operation, OPname) { \
|
||||
microVU* mVU = mVUx; \
|
||||
|
|
@ -90,7 +99,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \
|
||||
mVUallocFMAC1b<vuIndex>(Fd); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogFd(); mVUlogFt(); } \
|
||||
}
|
||||
// FMAC3 - BC(xyzw) FMAC Opcodes
|
||||
#define mVU_FMAC3(operation, OPname) { \
|
||||
|
|
@ -104,7 +113,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \
|
||||
mVUallocFMAC3b<vuIndex>(Fd); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogFd(); mVUlogBC(); } \
|
||||
}
|
||||
// FMAC4 - FMAC Opcodes Storing Result to ACC
|
||||
#define mVU_FMAC4(operation, OPname) { \
|
||||
|
|
@ -118,7 +127,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC4b<vuIndex>(ACC, Fs); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogACC(); mVUlogFt(); } \
|
||||
}
|
||||
// FMAC5 - FMAC BC(xyzw) Opcodes Storing Result to ACC
|
||||
#define mVU_FMAC5(operation, OPname) { \
|
||||
|
|
@ -132,7 +141,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC5b<vuIndex>(ACC, Fs); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogACC(); mVUlogBC(); } \
|
||||
}
|
||||
// FMAC6 - Normal FMAC Opcodes (I Reg)
|
||||
#define mVU_FMAC6(operation, OPname) { \
|
||||
|
|
@ -146,7 +155,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \
|
||||
mVUallocFMAC6b<vuIndex>(Fd); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogFd(); mVUlogI(); } \
|
||||
}
|
||||
// FMAC7 - FMAC Opcodes Storing Result to ACC (I Reg)
|
||||
#define mVU_FMAC7(operation, OPname) { \
|
||||
|
|
@ -160,7 +169,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC7b<vuIndex>(ACC, Fs); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogACC(); mVUlogI(); } \
|
||||
}
|
||||
// FMAC8 - MADD FMAC Opcode Storing Result to Fd
|
||||
#define mVU_FMAC8(operation, OPname) { \
|
||||
|
|
@ -180,7 +189,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC8b<vuIndex>(Fd); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogFd(); mVUlogFt(); } \
|
||||
}
|
||||
// FMAC9 - MSUB FMAC Opcode Storing Result to Fd
|
||||
#define mVU_FMAC9(operation, OPname) { \
|
||||
|
|
@ -200,7 +209,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC9b<vuIndex>(Fd); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogFd(); mVUlogFt(); } \
|
||||
}
|
||||
// FMAC10 - MADD FMAC BC(xyzw) Opcode Storing Result to Fd
|
||||
#define mVU_FMAC10(operation, OPname) { \
|
||||
|
|
@ -220,7 +229,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC10b<vuIndex>(Fd); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogFd(); mVUlogBC(); } \
|
||||
}
|
||||
// FMAC11 - MSUB FMAC BC(xyzw) Opcode Storing Result to Fd
|
||||
#define mVU_FMAC11(operation, OPname) { \
|
||||
|
|
@ -240,7 +249,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC11b<vuIndex>(Fd); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogFd(); mVUlogBC(); } \
|
||||
}
|
||||
// FMAC12 - MADD FMAC Opcode Storing Result to Fd (I Reg)
|
||||
#define mVU_FMAC12(operation, OPname) { \
|
||||
|
|
@ -260,7 +269,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC12b<vuIndex>(Fd); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogFd(); mVUlogI(); } \
|
||||
}
|
||||
// FMAC13 - MSUB FMAC Opcode Storing Result to Fd (I Reg)
|
||||
#define mVU_FMAC13(operation, OPname) { \
|
||||
|
|
@ -280,7 +289,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC13b<vuIndex>(Fd); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogFd(); mVUlogI(); } \
|
||||
}
|
||||
// FMAC14 - MADDA/MSUBA FMAC Opcode
|
||||
#define mVU_FMAC14(operation, OPname) { \
|
||||
|
|
@ -300,7 +309,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC14b<vuIndex>(ACCw, ACCr); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogACC(); mVUlogFt(); } \
|
||||
}
|
||||
// FMAC15 - MADDA/MSUBA BC(xyzw) FMAC Opcode
|
||||
#define mVU_FMAC15(operation, OPname) { \
|
||||
|
|
@ -320,7 +329,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC15b<vuIndex>(ACCw, ACCr); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogACC(); mVUlogBC(); } \
|
||||
}
|
||||
// FMAC16 - MADDA/MSUBA FMAC Opcode (I Reg)
|
||||
#define mVU_FMAC16(operation, OPname) { \
|
||||
|
|
@ -340,7 +349,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC16b<vuIndex>(ACCw, ACCr); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogACC(); mVUlogI(); } \
|
||||
}
|
||||
// FMAC18 - OPMULA FMAC Opcode
|
||||
#define mVU_FMAC18(operation, OPname) { \
|
||||
|
|
@ -353,9 +362,9 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC18b<vuIndex>(ACC, Fs); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogACC(); mVUlogFt(); } \
|
||||
}
|
||||
// FMAC19 - OPMULA FMAC Opcode
|
||||
// FMAC19 - OPMSUB FMAC Opcode
|
||||
#define mVU_FMAC19(operation, OPname) { \
|
||||
microVU* mVU = mVUx; \
|
||||
pass1 { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, _Ft_); } \
|
||||
|
|
@ -367,7 +376,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC19b<vuIndex>(Fd); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogFd(); mVUlogFt(); } \
|
||||
}
|
||||
// FMAC22 - Normal FMAC Opcodes (Q Reg)
|
||||
#define mVU_FMAC22(operation, OPname) { \
|
||||
|
|
@ -381,7 +390,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \
|
||||
mVUallocFMAC22b<vuIndex>(Fd); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogFd(); mVUlogQ(); } \
|
||||
}
|
||||
// FMAC23 - FMAC Opcodes Storing Result to ACC (Q Reg)
|
||||
#define mVU_FMAC23(operation, OPname) { \
|
||||
|
|
@ -395,7 +404,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC23b<vuIndex>(ACC, Fs); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogACC(); mVUlogQ();} \
|
||||
}
|
||||
// FMAC24 - MADD FMAC Opcode Storing Result to Fd (Q Reg)
|
||||
#define mVU_FMAC24(operation, OPname) { \
|
||||
|
|
@ -415,7 +424,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC24b<vuIndex>(Fd); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogFd(); mVUlogQ(); } \
|
||||
}
|
||||
// FMAC25 - MSUB FMAC Opcode Storing Result to Fd (Q Reg)
|
||||
#define mVU_FMAC25(operation, OPname) { \
|
||||
|
|
@ -435,7 +444,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC25b<vuIndex>(Fd); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogFd(); mVUlogQ(); } \
|
||||
}
|
||||
// FMAC26 - MADDA/MSUBA FMAC Opcode (Q Reg)
|
||||
#define mVU_FMAC26(operation, OPname) { \
|
||||
|
|
@ -455,7 +464,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUupdateFlags<vuIndex>(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \
|
||||
mVUallocFMAC26b<vuIndex>(ACCw, ACCr); \
|
||||
} \
|
||||
pass3 { mVUlog(OPname); } \
|
||||
pass3 { mVUlog(OPname); mVUlogACC(); mVUlogQ(); } \
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
|
|
@ -471,7 +480,7 @@ microVUf(void) mVU_ABS() {
|
|||
SSE_ANDPS_M128_to_XMM(Fs, (uptr)mVU_absclip);
|
||||
mVUallocFMAC2b<vuIndex>(Ft);
|
||||
}
|
||||
pass3 { mVUlog("ABS"); }
|
||||
pass3 { mVUlog("ABS"); mVUlogFtFs(); }
|
||||
}
|
||||
microVUf(void) mVU_ADD() { mVU_FMAC1 (ADD, "ADD"); }
|
||||
microVUf(void) mVU_ADDi() { mVU_FMAC6 (ADD, "ADDi"); }
|
||||
|
|
@ -545,7 +554,7 @@ microVUf(void) mVU_MSUBAz() { mVU_FMAC15(SUB, "MSUBAz"); }
|
|||
microVUf(void) mVU_MSUBAw() { mVU_FMAC15(SUB, "MSUBAw"); }
|
||||
microVUf(void) mVU_MAX() { mVU_FMAC1 (MAX, "MAX"); }
|
||||
microVUf(void) mVU_MAXi() { mVU_FMAC6 (MAX, "MAXi"); }
|
||||
microVUf(void) mVU_MAXx() { mVU_FMAC3 (MAX, "MAXq"); }
|
||||
microVUf(void) mVU_MAXx() { mVU_FMAC3 (MAX, "MAXx"); }
|
||||
microVUf(void) mVU_MAXy() { mVU_FMAC3 (MAX, "MAXy"); }
|
||||
microVUf(void) mVU_MAXz() { mVU_FMAC3 (MAX, "MAXz"); }
|
||||
microVUf(void) mVU_MAXw() { mVU_FMAC3 (MAX, "MAXw"); }
|
||||
|
|
@ -579,10 +588,10 @@ microVUq(void) mVU_FTOIx(uptr addr) {
|
|||
mVUallocFMAC2b<vuIndex>(Ft);
|
||||
}
|
||||
}
|
||||
microVUf(void) mVU_FTOI0() { mVU_FTOIx<vuIndex, recPass>((uptr)0); pass3 { mVUlog("FTOI0"); } }
|
||||
microVUf(void) mVU_FTOI4() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_4); pass3 { mVUlog("FTOI4"); } }
|
||||
microVUf(void) mVU_FTOI12() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_12); pass3 { mVUlog("FTOI12"); } }
|
||||
microVUf(void) mVU_FTOI15() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_15); pass3 { mVUlog("FTOI15"); } }
|
||||
microVUf(void) mVU_FTOI0() { mVU_FTOIx<vuIndex, recPass>((uptr)0); pass3 { microVU* mVU = mVUx; mVUlog("FTOI0"); mVUlogFtFs(); } }
|
||||
microVUf(void) mVU_FTOI4() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_4); pass3 { microVU* mVU = mVUx; mVUlog("FTOI4"); mVUlogFtFs(); } }
|
||||
microVUf(void) mVU_FTOI12() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_12); pass3 { microVU* mVU = mVUx; mVUlog("FTOI12"); mVUlogFtFs(); } }
|
||||
microVUf(void) mVU_FTOI15() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_15); pass3 { microVU* mVU = mVUx; mVUlog("FTOI15"); mVUlogFtFs(); } }
|
||||
microVUq(void) mVU_ITOFx(uptr addr) {
|
||||
microVU* mVU = mVUx;
|
||||
pass1 { mVUanalyzeFMAC2<vuIndex>(_Fs_, _Ft_); }
|
||||
|
|
@ -597,10 +606,10 @@ microVUq(void) mVU_ITOFx(uptr addr) {
|
|||
mVUallocFMAC2b<vuIndex>(Ft);
|
||||
}
|
||||
}
|
||||
microVUf(void) mVU_ITOF0() { mVU_ITOFx<vuIndex, recPass>((uptr)0); pass3 { mVUlog("ITOF0"); } }
|
||||
microVUf(void) mVU_ITOF4() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_4); pass3 { mVUlog("ITOF4"); } }
|
||||
microVUf(void) mVU_ITOF12() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_12); pass3 { mVUlog("ITOF12"); } }
|
||||
microVUf(void) mVU_ITOF15() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_15); pass3 { mVUlog("ITOF15"); } }
|
||||
microVUf(void) mVU_ITOF0() { mVU_ITOFx<vuIndex, recPass>((uptr)0); pass3 { microVU* mVU = mVUx; mVUlog("ITOF0"); mVUlogFtFs(); } }
|
||||
microVUf(void) mVU_ITOF4() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_4); pass3 { microVU* mVU = mVUx; mVUlog("ITOF4"); mVUlogFtFs(); } }
|
||||
microVUf(void) mVU_ITOF12() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_12); pass3 { microVU* mVU = mVUx; mVUlog("ITOF12"); mVUlogFtFs(); } }
|
||||
microVUf(void) mVU_ITOF15() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_15); pass3 { microVU* mVU = mVUx; mVUlog("ITOF15"); mVUlogFtFs(); } }
|
||||
microVUf(void) mVU_CLIP() {
|
||||
microVU* mVU = mVUx;
|
||||
pass1 { mVUanalyzeFMAC4<vuIndex>(_Fs_, _Ft_); }
|
||||
|
|
@ -633,6 +642,6 @@ microVUf(void) mVU_CLIP() {
|
|||
|
||||
mVUallocCFLAGb<vuIndex>(gprT1, fcInstance);
|
||||
}
|
||||
pass3 { mVUlog("CLIP"); }
|
||||
pass3 { mVUlog("CLIP"); mVUlogCLIP(); }
|
||||
}
|
||||
#endif //PCSX2_MICROVU
|
||||
|
|
|
|||
Loading…
Reference in New Issue