mirror of https://github.com/PCSX2/pcsx2.git
iop: fix division on the interpreter
Recompiler is still completely broken just add tons of FIXME
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@ -71,14 +71,36 @@ void psxSLTU() { if (!_Rd_) return; _rRd_ = _u32(_rRs_) < _u32(_rRt_); } // Rd
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* Format: OP rs, rt *
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*********************************************************/
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void psxDIV() {
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if (_rRt_ != 0) {
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if (_rRt_ == 0) {
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// Division by 0
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_rLo_ = _i32(_rRs_) < 0 ? 1 : 0xFFFFFFFFu;
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_rHi_ = _rRs_;
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} else if (_rRs_ == 0x80000000u && _rRt_ == 0xFFFFFFFFu) {
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// x86 overflow
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_rLo_ = 0x80000000u;
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_rHi_ = 0;
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} else {
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// Normal behavior
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_rLo_ = _i32(_rRs_) / _i32(_rRt_);
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_rHi_ = _i32(_rRs_) % _i32(_rRt_);
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}
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}
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void psxDIVU() {
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if (_rRt_ != 0) {
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if (_rRt_ == 0) {
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// Division by 0
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_rLo_ = 0xFFFFFFFFu;
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_rHi_ = _rRs_;
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} else if (_rRs_ == 0x80000000u && _rRt_ == 0xFFFFFFFFu) {
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// x86 overflow
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_rLo_ = 0;
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_rHi_ = 0x80000000u;
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} else {
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// Normal behavior
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_rLo_ = _rRs_ / _rRt_;
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_rHi_ = _rRs_ % _rRt_;
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}
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@ -506,11 +506,18 @@ void rpsxDIV_const()
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*/
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// Of course x86 cpu does overflow !
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if (g_psxConstRegs[_Rs_] == 0x80000000u && g_psxConstRegs[_Rt_] == 0xFFFFFFFFu) {
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// FIXME depends if div/divu
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xMOV(ptr32[&psxRegs.GPR.n.hi], 0);
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xMOV(ptr32[&psxRegs.GPR.n.lo], 0x80000000);
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return;
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}
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if (g_psxConstRegs[_Rt_] == 0) {
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// FIXME
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// hi must be rs
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// lo must be 0xFFFF_FFFFF is rs >= 0, 0x1 otherwise if rs < 0 and sign
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}
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if (g_psxConstRegs[_Rt_] != 0) {
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lo = *(int*)&g_psxConstRegs[_Rs_] / *(int*)&g_psxConstRegs[_Rt_];
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hi = *(int*)&g_psxConstRegs[_Rs_] % *(int*)&g_psxConstRegs[_Rt_];
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@ -523,6 +530,15 @@ void rpsxDIVsuperconsts(int info, int sign)
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{
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u32 imm = g_psxConstRegs[_Rs_];
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if (imm == 0x80000000u) {
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// FIXME if RT is 0xFFFFFFFFu
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// hi must be 0
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// lo must be 0x80000000
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// FIXME depends if div/divu
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//
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// Otherwise standard division
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}
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if( imm ) {
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// Lo/Hi = Rs / Rt (signed)
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rt_]]);
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@ -549,6 +565,7 @@ void rpsxDIVsuperconsts(int info, int sign)
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xXOR(eax, eax);
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xMOV(ptr[&psxRegs.GPR.n.hi], eax);
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xMOV(ptr[&psxRegs.GPR.n.lo], eax);
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// FIXME lo must be 0xFFFF_FFFFF if rt is 0
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}
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}
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@ -556,6 +573,15 @@ void rpsxDIVsuperconstt(int info, int sign)
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{
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u32 imm = g_psxConstRegs[_Rt_];
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if (imm == 0xFFFFFFFFu) {
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// FIXME if RS is 0x80000000
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// hi must be 0
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// lo must be 0x80000000
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// FIXME depends if div/divu
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//
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// Otherwise standard division
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}
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if( imm ) {
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xMOV(eax, ptr[&psxRegs.GPR.r[_Rs_]]);
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xMOV(ecx, imm);
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@ -573,6 +599,10 @@ void rpsxDIVsuperconstt(int info, int sign)
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xMOV(ptr[&psxRegs.GPR.n.lo], eax);
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xMOV(ptr[&psxRegs.GPR.n.hi], edx);
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} else {
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// FIXME
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// hi must be rs
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// lo must be 0xFFFF_FFFFF is rs >= 0, 0x1 otherwise if rs < 0 and sign
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}
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}
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@ -596,6 +626,15 @@ void rpsxDIVsuper(int info, int sign)
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xMOV(ptr[&psxRegs.GPR.n.lo], eax);
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xMOV(ptr[&psxRegs.GPR.n.hi], edx);
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x86SetJ8(j8Ptr[0]);
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// FIXME if RS is 0x80000000 and RT is 0xFFFF_FFFFF
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// hi must be 0
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// lo must be 0x80000000
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// FIXME depends if div/divu
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// FIXME
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// hi must be rs
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// lo must be 0xFFFF_FFFFF is rs >= 0, 0x1 otherwise
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}
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void rpsxDIV_consts(int info) { rpsxDIVsuperconsts(info, 1); }
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