mirror of https://github.com/PCSX2/pcsx2.git
newHostVM: Sync with trunk (r4010-4019)
git-svn-id: http://pcsx2.googlecode.com/svn/branches/newHostVM@4024 96395faa-99c1-11dd-bbfe-3dabce05a288
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commit
127ca00492
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@ -29,7 +29,7 @@
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#include "CDVDisoReader.h"
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static u8 *pbuffer;
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static u8 cdbuffer[2352] = {0};
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static u8 cdbuffer[CD_FRAMESIZE_RAW] = {0};
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static isoFile iso;
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static int psize, cdtype;
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@ -107,17 +107,36 @@ __fi void vif0SetupTransfer()
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if (vif0ch.chcr.TTE)
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{
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// Transfer dma tag if tte is set
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bool ret;
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if (vif0.vifstalled)
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ret = VIF0transfer((u32*)ptag + (2 + vif0.irqoffset), 2 - vif0.irqoffset); //Transfer Tag on stall
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else
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ret = VIF0transfer((u32*)ptag + 2, 2); //Transfer Tag
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static __aligned16 u128 masked_tag;
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if ((ret == false) && vif0.irqoffset < 2)
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masked_tag._u64[0] = 0;
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masked_tag._u64[1] = *((u64*)ptag + 1);
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VIF_LOG("\tVIF0 SrcChain TTE=1, data = 0x%08x.%08x", masked_tag._u32[3], masked_tag._u32[2]);
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if (vif0.vifstalled)
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{
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ret = VIF0transfer((u32*)&masked_tag + vif0.irqoffset, 4 - vif0.irqoffset, true); //Transfer Tag on stall
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//ret = VIF0transfer((u32*)ptag + (2 + vif0.irqoffset), 2 - vif0.irqoffset); //Transfer Tag on stall
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}
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else
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{
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//Some games (like killzone) do Tags mid unpack, the nops will just write blank data
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//to the VU's, which breaks stuff, this is where the 128bit packet will fail, so we ignore the first 2 words
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vif0.irqoffset = 2;
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ret = VIF0transfer((u32*)&masked_tag + 2, 2, true); //Transfer Tag
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//ret = VIF0transfer((u32*)ptag + 2, 2); //Transfer Tag
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}
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if (!ret && vif0.irqoffset)
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{
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vif0.inprogress = 0; //Better clear this so it has to do it again (Jak 1)
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return; //There has been an error or an interrupt
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return; //IRQ set by VIFTransfer
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}
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}
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@ -205,7 +205,7 @@ __fi void vif1SetupTransfer()
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bool ret;
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static __aligned16 u128 masked_tag;
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masked_tag._u64[0] = 0;
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masked_tag._u64[1] = *((u64*)ptag + 1);
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@ -218,7 +218,10 @@ __fi void vif1SetupTransfer()
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}
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else
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{
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ret = VIF1transfer((u32*)&masked_tag, 4, true); //Transfer Tag
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//Some games (like killzone) do Tags mid unpack, the nops will just write blank data
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//to the VU's, which breaks stuff, this is where the 128bit packet will fail, so we ignore the first 2 words
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vif1.irqoffset = 2;
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ret = VIF1transfer((u32*)&masked_tag + 2, 2, true); //Transfer Tag
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//ret = VIF1transfer((u32*)ptag + 2, 2); //Transfer Tag
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}
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@ -226,8 +229,7 @@ __fi void vif1SetupTransfer()
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{
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vif1.inprogress &= ~1; //Better clear this so it has to do it again (Jak 1)
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return; //IRQ set by VIFTransfer
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} //else vif1.vifstalled = false;
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}
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}
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vif1.irqoffset = 0;
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@ -124,7 +124,7 @@ static __fi void mfifo_VIF1chain()
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}
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}
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int NextTADR = 0; //Bodge for Clock Tower 3 (see below)
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void mfifoVIF1transfer(int qwc)
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{
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@ -178,6 +178,7 @@ void mfifoVIF1transfer(int qwc)
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return; //IRQ set by VIFTransfer
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} //else vif1.vifstalled = false;
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g_vifCycles += 2;
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}
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vif1.irqoffset = 0;
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@ -193,13 +194,13 @@ void mfifoVIF1transfer(int qwc)
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switch (ptag->ID)
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{
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case TAG_REFE: // Refe - Transfer Packet According to ADDR field
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vif1ch.tadr = qwctag(vif1ch.tadr + 16);
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NextTADR = qwctag(vif1ch.tadr + 16);
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vif1.done = true; //End Transfer
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break;
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case TAG_CNT: // CNT - Transfer QWC following the tag.
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vif1ch.madr = qwctag(vif1ch.tadr + 16); //Set MADR to QW after Tag
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vif1ch.tadr = qwctag(vif1ch.madr + (vif1ch.qwc << 4)); //Set TADR to QW following the data
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NextTADR = qwctag(vif1ch.madr + (vif1ch.qwc << 4)); //Set TADR to QW following the data
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vif1.done = false;
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break;
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@ -207,7 +208,7 @@ void mfifoVIF1transfer(int qwc)
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{
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int temp = vif1ch.madr; //Temporarily Store ADDR
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vif1ch.madr = qwctag(vif1ch.tadr + 16); //Set MADR to QW following the tag
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vif1ch.tadr = temp; //Copy temporarily stored ADDR to Tag
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NextTADR = temp; //Copy temporarily stored ADDR to Tag
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if ((temp & dmacRegs.rbsr.RMSK) != dmacRegs.rbor.ADDR) Console.WriteLn("Next tag = %x outside ring %x size %x", temp, psHu32(DMAC_RBOR), psHu32(DMAC_RBSR));
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vif1.done = false;
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break;
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@ -215,13 +216,13 @@ void mfifoVIF1transfer(int qwc)
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case TAG_REF: // Ref - Transfer QWC from ADDR field
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case TAG_REFS: // Refs - Transfer QWC from ADDR field (Stall Control)
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vif1ch.tadr = qwctag(vif1ch.tadr + 16); //Set TADR to next tag
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NextTADR = qwctag(vif1ch.tadr + 16); //Set TADR to next tag
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vif1.done = false;
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break;
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case TAG_END: // End - Transfer QWC following the tag
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vif1ch.madr = qwctag(vif1ch.tadr + 16); //Set MADR to data following the tag
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vif1ch.tadr = qwctag(vif1ch.madr + (vif1ch.qwc << 4)); //Set TADR to QW following the data
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NextTADR = qwctag(vif1ch.madr + (vif1ch.qwc << 4)); //Set TADR to QW following the data
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vif1.done = true; //End Transfer
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break;
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}
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@ -245,6 +246,17 @@ void vifMFIFOInterrupt()
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g_vifCycles = 0;
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VIF_LOG("vif mfifo interrupt");
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if(NextTADR != 0 && vif1ch.qwc == 0)
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{
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// Clock Tower 3 Note!
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/* If the DMA starts the transfer then hammers the TADR to see when the transfer has finished(as clock tower does)
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and we have preincremented before all data has arrived, it breaks. Idealy we increment this as we transfer the data.
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"NextTADR" bodge in for the moment! - Refraction */
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vif1ch.tadr = NextTADR;
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NextTADR = 0;
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}
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if(GSTransferStatus.PTH2 == STOPPED_MODE && gifRegs.stat.APATH == GIF_APATH2)
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{
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GSTransferStatus.PTH2 = STOPPED_MODE;
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@ -304,6 +316,8 @@ void vifMFIFOInterrupt()
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}
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mfifoVIF1transfer(0);
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CPU_INT(DMAC_MFIFO_VIF, 4);
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return;
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@ -112,7 +112,7 @@ _vifT static __fi bool vifTransfer(u32 *data, int size, bool TTE) {
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vifStruct& vifX = GetVifX;
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// irqoffset necessary to add up the right qws, or else will spin (spiderman)
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int transferred = vifX.vifstalled ? vifX.irqoffset : 0;
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int transferred = vifX.irqoffset;
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vifX.irqoffset = 0;
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vifX.vifstalled = false;
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@ -139,26 +139,28 @@ _vifT static __fi bool vifTransfer(u32 *data, int size, bool TTE) {
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vifX.irqoffset = transferred % 4; // cannot lose the offset
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if (TTE) return !vifX.vifstalled;
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if (!TTE) // *WARNING* - Tags CAN have interrupts! so lets just ignore the dma modifying stuffs (GT4)
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{
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transferred = transferred >> 2;
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transferred = transferred >> 2;
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vifXch.madr +=(transferred << 4);
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vifXch.qwc -= transferred;
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}
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vifXch.madr +=(transferred << 4);
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vifXch.qwc -= transferred;
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if (!vifXch.qwc && !vifX.irqoffset) vifX.inprogress &= ~0x1;
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if (!vifXch.qwc && !vifX.irqoffset)
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{
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vifX.inprogress &= ~0x1;
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vifX.vifstalled = false;
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}
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if (vifX.irq && vifX.cmd == 0) {
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//DevCon.WriteLn("Vif IRQ!");
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if(((vifXRegs.code >> 24) & 0x7f) != 0x7)
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{
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vifX.vifstalled = true;
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vifXRegs.stat.VIS = true; // Note: commenting this out fixes WALL-E?
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}
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if (!vifXch.qwc && !vifX.irqoffset) vifX.inprogress &= ~1;
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return false;
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}
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vifX.vifstalled = true;
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}
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}
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return !vifX.vifstalled;
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}
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